JPS60142566A - Insulated gate thin film transistor and manufacture thereof - Google Patents
Insulated gate thin film transistor and manufacture thereofInfo
- Publication number
- JPS60142566A JPS60142566A JP25009083A JP25009083A JPS60142566A JP S60142566 A JPS60142566 A JP S60142566A JP 25009083 A JP25009083 A JP 25009083A JP 25009083 A JP25009083 A JP 25009083A JP S60142566 A JPS60142566 A JP S60142566A
- Authority
- JP
- Japan
- Prior art keywords
- film
- thin film
- film transistor
- layer
- insulated gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 title claims description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 7
- 239000012535 impurity Substances 0.000 claims description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 7
- 239000011521 glass Substances 0.000 abstract description 6
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 abstract description 5
- 229910001120 nichrome Inorganic materials 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 2
- 230000004913 activation Effects 0.000 abstract 3
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000010408 film Substances 0.000 description 26
- 239000010409 thin film Substances 0.000 description 12
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 230000031700 light absorption Effects 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000002834 transmittance Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910018487 Ni—Cr Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
- H01L29/78687—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
（１）発明の技術分野
本発明は、背面露光に好適し、素子の特性が向上した絶
縁ゲート薄膜トランジスタとその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to an insulated gate thin film transistor that is suitable for back exposure and has improved device characteristics, and a method for manufacturing the same.
（２）発明の背景
絶縁ゲート薄膜トランジスタは、絶縁基板上にゲート電
極、絶縁ゲート層、半導体層、ソース・ドレイン電極を
債催して構成される。この絶縁ゲート薄膜トランジスタ
は１例えば液晶表示パネルの画素毎にスイッチング素子
として用いられるが。(2) Background of the Invention An insulated gate thin film transistor is constructed by bonding a gate electrode, an insulated gate layer, a semiconductor layer, and source/drain electrodes on an insulating substrate. This insulated gate thin film transistor is used as a switching element for each pixel of a liquid crystal display panel, for example.
例えばＡ４サイズの液晶表示パネルを構成する場合、一
画素は２００μ９程度となり、これに伴い１個の薄膜ト
ランジスタのサイズも小形化する必要がある。この薄膜
トランジスタは、液晶表示パネルに用いられる場合、透
過光のシールドとなる虞れがあるから小形化の要請は増
加する。For example, when constructing an A4-sized liquid crystal display panel, one pixel is approximately 200 μ9, and accordingly, the size of one thin film transistor must also be reduced. When this thin film transistor is used in a liquid crystal display panel, there is a risk that it may become a shield for transmitted light, so there is an increasing demand for miniaturization.
（３）従来技術と問題点
従来の絶縁ゲート薄膜トランジスタには半導体層をａ−
３ｉ（アモルファスシリコン）によって形成するものが
あった。しかしながら、この種の薄膜トランジスタは画
素の面積が小となる領域ではオフ電流が十分に低くない
という欠点があった。(3) Conventional technology and problems Conventional insulated gate thin film transistors have a semiconductor layer a-
There was one made of 3i (amorphous silicon). However, this type of thin film transistor has a drawback that its off-state current is not sufficiently low in regions where the pixel area is small.
また、薄膜トランジスタを高精度かつ大面積にてバター
ニングするため、絶縁基板の背面からの露光によりセル
フアライメントによって薄膜トランジスタを製造する際
には、レジストの感光波長域（６００ｎｍ以下）ではａ
−３ｉの光吸収が大であるため、十分な露光を行なうた
めにはａ−３ｉの半導体層を１０００Å以下に薄くしな
ければならず。In addition, in order to pattern thin film transistors with high precision and over a large area, when manufacturing thin film transistors by self-alignment using exposure from the back side of an insulating substrate, in the photosensitive wavelength range of the resist (600 nm or less),
Since light absorption of -3i is large, the semiconductor layer of a-3i must be thinned to 1000 Å or less in order to perform sufficient exposure.
このため薄膜トランジスタの闇値電圧が不安定になる等
のトランジスク特性の劣化を招き、さらにａ−３ｉを介
して露光するためには、露光時間を通電の１００倍程度
にしなければならないという問題があった。This causes deterioration of the transistor characteristics such as the dark voltage of the thin film transistor becoming unstable, and furthermore, there is the problem that in order to expose through the a-3i, the exposure time has to be about 100 times the energization time. Ta.
（４）発明の目的
本発明は、半導体層のａ−５ｉ膜の一部または全部をａ
−３ｉｘＣ＋−ｘ：Ｈ（水素を含んだアモルファスシリ
コンと炭素の合金）におきかえることにより、オフ電流
を低減できるとともに、闇値電圧等の半導体の素子特性
が安定し、かつ製造時において露光時間を短縮できる絶
縁ゲート薄膜トランジスタとその製造方法を提供するこ
とを目的とする。(4) Purpose of the Invention The present invention provides a method for converting part or all of the a-5i film of the semiconductor layer into a
By replacing -3ixC+-x:H (an alloy of amorphous silicon and carbon containing hydrogen), it is possible to reduce off-current, stabilize semiconductor device characteristics such as dark voltage, and reduce exposure time during manufacturing. An object of the present invention is to provide an insulated gate thin film transistor that can be shortened and a manufacturing method thereof.
（５）発明の構成
そして上記目的は本発明によれば、絶縁基板上にソース
、ドレイン電極、半導体層、ゲート絶縁層、ゲート電極
を積層してなり、前記半導体層がａ−３ｉｘＣ＋−ｘ：
Ｈよりなることを特徴とする絶縁ゲートＦ４？膜トラン
ジスタを提供することによって達成される。(5) Structure of the invention and the above-mentioned object is that according to the present invention, a source, a drain electrode, a semiconductor layer, a gate insulating layer, and a gate electrode are stacked on an insulating substrate, and the semiconductor layer is a-3ixC+-x:
Insulated gate F4 characterized by consisting of H? This is achieved by providing a membrane transistor.
即ち５本発明の薄膜トランジスタは半導体層に用いられ
るａ−３ｉｘＣ＋−ｘ：Ｈはａ−３ｉに比べて、導電率
が低いので、オフ電流を低減でき。That is, in the thin film transistor of the present invention, the a-3ixC+-x:H used in the semiconductor layer has a lower conductivity than a-3i, so the off-state current can be reduced.
レジスト感光波長付近の光吸収が少ないので、半導体層
を厚くできるから素子特性が安定しかつ製造の露光時間
も短縮できるのである。。Since there is little light absorption near the resist photosensitive wavelength, the semiconductor layer can be made thicker, resulting in stable device characteristics and shorter manufacturing exposure time. .
（６）発明の実施例 以下１図面を参照して１本発明の一実施例を説明する。(6) Examples of the invention An embodiment of the present invention will be described below with reference to the drawings.
第１図において２例えば、ガラス基板１よりなる透明な
絶縁基板上にゲート金属として１例えば。In FIG. 1, a gate metal layer 1 is formed on a transparent insulating substrate made of, for example, a glass substrate 1.
ＮｉＣｒ にッケルクロム）パターンを７００への厚さ
に形成し、ゲート電極２とする（ａ図）。A NiCr (nickel chromium) pattern is formed to a thickness of about 700 nm to form the gate electrode 2 (Figure a).
次にプラズマＣＶＤ法によりゲート絶縁層となる３ｉ３
Ｎ４ （窒化シリコン）膜３あるいは５ｉ０２（酸化シ
リコン）膜を３０００人の厚さに形成し。Next, 3i3 which becomes the gate insulating layer by plasma CVD method.
A N4 (silicon nitride) film 3 or a 5i02 (silicon oxide) film is formed to a thickness of 3000 nm.
これに接してその上にａ−３ｔ：Ｈ（水素を含んだアモ
ルファスシリコン）膜４を１００人程度の厚さに形成し
、その上に、ａ−３ｉｘＣ＋−ｘ：Ｈ１１央５を３００
０〜５０００人の厚さに順次真空中にて成膜する（ｂ図
）。ここでａ −Ｓ ｉ ： Ｉ−１膜４及びａ−３ｉ
ｘ Ｃ＋ −ｘ ： Ｈ膜５ば半導体活性層を構成す
る。次に、ポジ型のフォトレジスト６を１．５μｍ厚に
塗布し、ガラス基板１の背面より、〜６０００人（２ｅ
ｖ）以下の波長の光にて露光する（０図）。In contact with this, an a-3t:H (amorphous silicon containing hydrogen) film 4 is formed to a thickness of about 100 mm, and a-3ixC+-x:H11 center 5 is formed on it to a thickness of 300 mm.
Films are sequentially formed in a vacuum to a thickness of 0 to 5000 mm (Figure b). where a-S i : I-1 film 4 and a-3i
xC+-x: H film 5 constitutes a semiconductor active layer. Next, a positive type photoresist 6 is applied to a thickness of 1.5 μm, and ~6000 people (2e
v) Expose with light of the following wavelengths (Figure 0).
次にフォトレジストを現像し、セルフアライメントプロ
セスによって、ゲート電極２に対応するフォトレジスト
６のみを残し、他の部分のレジストを除去する。表面に
リンがドープされたｎ ａ −３ｉｘＣ＋−ｘｌＱ７を
１００〜５００人厚に形成し。Next, the photoresist is developed, and by a self-alignment process, only the photoresist 6 corresponding to the gate electrode 2 is left, and the other portions of the resist are removed. A layer of na-3ixC+-xlQ7 doped with phosphorus on the surface is formed to a thickness of 100 to 500 layers.
その上にＮｉＣｒよりなるソース・ドレイン電極８を成
膜する（ｄ図）。そして、リフトオフ工程によって例え
ばアセＩ・ンによりフォトレジスト６を除去し、ソース
・ドレイン電極８のパターニングを行なって、絶縁ゲー
ト薄膜トランジスタを形成する（ｅ図）。A source/drain electrode 8 made of NiCr is formed thereon (Fig. d). Then, the photoresist 6 is removed by a lift-off process, for example, by acetic acid, and the source/drain electrodes 8 are patterned to form an insulated gate thin film transistor (see figure e).
上述の工程によって製造された本発明の絶縁ゲート薄膜
トランジスタでは、ａ−３ｉ：Ｈ膜４の上にａ−３ｉ
ｘＣ’＋−ｘ ： Ｈ賎５を形成し、ａ−３ｉｘＣ＋−
ｘ：Ｈ膜の組成比をｘ＝ｏからＯ〈Ｘく１の範囲へと階
段状に変化させているのでオプチイ力ルギャソプＥ６Ｐ
が１．６ｅＶから２゜５ｅＶへと高エネルギー側にシフ
トする。 このため、ａ−３ｉ ：Ｈ膜だけで半導体活
性層を形成した場合に比べて半導体活性層を厚くしても
容易に露光が行なえる。即ち光透過率が悪いａ−８ｉ：
Ｈ膜４を薄＜シ、光透過率の良いａ−３ｉｘＣ＋−ｘ；
Ｈ膜５を厚く形成したからである。半導体活性層の膜厚
が厚いので闇値電圧等の素子特性を安定化し。In the insulated gate thin film transistor of the present invention manufactured by the above-mentioned process, a-3i is formed on the a-3i:H film 4.
xC'+-x: Forms H-5, a-3ixC+-
The composition ratio of the x:H film is changed stepwise from x = o to O <
shifts from 1.6 eV to 2°5 eV toward higher energy. Therefore, even if the semiconductor active layer is made thicker, exposure can be performed more easily than when the semiconductor active layer is formed using only the a-3i:H film. That is, a-8i with poor light transmittance:
H film 4 is thin and has good light transmittance a-3ixC+-x;
This is because the H film 5 is formed thick. The thick semiconductor active layer stabilizes device characteristics such as dark voltage.
ａ−Ｓｉ：Ｈ膜４が薄いのでガラス基板ｌの背面から半
導体活性層を介してレジストを露光することに適し、か
つ導電率の低いａ−３ｉｘＣ＋−ｘ：Ｈ膜５が素子の表
面近くに厚く形成されているので９表面の電荷が薄膜ト
ランジスタ素子内部に移動しオフ電流を流すことをブロ
ックできる。Since the a-Si:H film 4 is thin, it is suitable for exposing the resist from the back side of the glass substrate l through the semiconductor active layer, and the a-3ixC+-x:H film 5 with low conductivity is placed near the surface of the element. Since it is formed thickly, it is possible to block the charge on the surface from moving into the thin film transistor element and causing an off-state current to flow.
第２図は１本発明の薄膜トランジスタの他の製造プロセ
スを示すもので、このプロセスでは各層を成膜してい（
順序が、第１図の実施例と逆となるだけで、各層を形成
する材質及び厚さ等の形成条件は同様であるから対応す
る層には第１の実施例と同一番号を付し詳細な説明は省
略する。 まず、ガラス基板１上にソース・ドレイン電
極８を形成し、その上にｎ” ａ−３ｉｘＣ＋−ｘ：Ｈ
膜７を形成し、（ａ図）、−その上にａ−３ｔｘＣ＋−
ｘ ： Ｈ膜５．ａ−３ｉｘ：Ｈ膜４．ゲート絶縁１＊
３の順に形成する（ｂ図）。 次にポジレジスト６を塗
布し、ガラス基板１の背面より露光しく０図）、ソース
・ドレイン電極８においてゲート電極２に応対して切欠
かれ部分に関してセルフアライメントによって現像し、
ゲート電極２を形成しくｄ図）、そのゲート電極２以外
の部分のレジスト６をリーフトオフして２本発明の薄膜
トランジスタを形成する（ｅ図）。 第２図に示した実
施例も、第１図に示した実施例と同様に動作する。Figure 2 shows another manufacturing process for the thin film transistor of the present invention, in which each layer is formed (
The order is just reversed from the embodiment shown in Fig. 1, but the forming conditions such as the material and thickness for forming each layer are the same, so the corresponding layers are given the same numbers as in the first embodiment, and the details are explained below. Further explanation will be omitted. First, source/drain electrodes 8 are formed on a glass substrate 1, and n''a-3ixC+-x:H
Form a film 7, (Figure a), -a-3txC+- on it.
x: H film5. a-3ix: H film 4. Gate insulation 1*
3 (Figure b). Next, a positive resist 6 is applied, exposed to light from the back side of the glass substrate 1 (Fig. 0), and developed by self-alignment at the notch portion corresponding to the gate electrode 2 in the source/drain electrode 8.
A gate electrode 2 is formed (Fig. d), and a portion of the resist 6 other than the gate electrode 2 is leafed off to form a thin film transistor of the present invention (Fig. e). The embodiment shown in FIG. 2 operates similarly to the embodiment shown in FIG.
上記第１．第２の実施例において、ａ−３ｉｘＣＩ−ｘ
：Ｈ膜５の膜抵抗がａ−３ｔ：Ｈ膜４よりも高いため、
ソース・ドレイン電極８付近の膜厚方向の抵抗のため薄
膜トランジスタのオン電流も低下してしまうことがある
。この場合には、ａ−３ｉ’ｘｃ ＋ −ｘ ： Ｈ膜
５にリンやポロンの如き不純物を適量ドープすれば、か
かるオン電流の低下を防止できる。この際、ａ−３ｉｘ
Ｃ＋−ｘ：■（膜５のオプティカルギャップがａ−３ｔ
膜４よりも大きいという本発明の特徴は、失われないか
ら、第１．第２の実施例と同様の効果を奏することがで
きる。Above 1st. In a second embodiment, a-3ixCI-x
:H film 5 has a higher film resistance than a-3t:H film 4, so
Due to the resistance in the film thickness direction near the source/drain electrodes 8, the on-current of the thin film transistor may also decrease. In this case, if the a-3i'xc + -x :H film 5 is doped with an appropriate amount of impurity such as phosphorus or poron, such a decrease in on-current can be prevented. At this time, a-3ix
C+-x:■(Optical gap of film 5 is a-3t
The feature of the present invention that it is larger than the membrane 4 is not lost, so the first. The same effects as the second embodiment can be achieved.
（７）発明の効果
本発明によれば、オフ電流を低減できかつ、裏面露光の
際半導体層を透過してフォトレジストに到達する光量を
増加でき、従って露光時間を１／２０〜１／３０に短縮
でき、さらに、半導体層を厚く形成して闇値電圧等の素
子の特性の安定化した絶縁ゲートトランジスタを提供で
きる。(7) Effects of the Invention According to the present invention, it is possible to reduce the off-state current, and increase the amount of light that passes through the semiconductor layer and reaches the photoresist during backside exposure, thus reducing the exposure time by 1/20 to 1/30. Furthermore, by forming a thick semiconductor layer, it is possible to provide an insulated gate transistor in which device characteristics such as dark value voltage are stabilized.
第１図は本発明の絶縁デーｌ−薄膜トランジスタの製造
工程の一実施例を示す断面図、第２図は本発明の製造工
程の他の実施例を示す断面図である。
１・・・ガラス基板 ２・・・ゲート電極 ３・・・ゲ
ート絶縁膜
４・−ａ−３ｔ：Ｈ膜
５・−・ａ−３ｔｘＣ＋−ｘ：Ｈ膜
６・・・フォトレジスト ７・・・
ｎ”ａ−３ｉｘＣ＋−ｘ：Ｈ膜
８・・・ソース・ｌ”レイン電極
第１図
ｉ 光
第２因
露 光FIG. 1 is a cross-sectional view showing one embodiment of the manufacturing process of an insulated thin film transistor of the present invention, and FIG. 2 is a cross-sectional view showing another example of the manufacturing process of the present invention. 1...Glass substrate 2...Gate electrode 3...Gate insulating film 4.-a-3t:H film 5.-.a-3txC+-x:H film 6...Photoresist 7... n"a-3ixC+-x:H film 8...source/l"rain electrode Figure 1i Light second factor exposure
Claims (4)
、ゲート絶縁層、ゲート電極を積層してなり、前記半導
体層がａ−３ｉｘＣ＋−ｘ：Ｈよりなることを特徴とす
る絶縁ゲート薄膜トランジスタ。(1) An insulated gate thin film transistor comprising a source, a drain electrode, a semiconductor layer, a gate insulating layer, and a gate electrode stacked on an insulating substrate, the semiconductor layer comprising a-3ixC+-x:H.
： ＩＩのうちデーｌ−絶縁層に接する部分のＸの値
をＸ＝１とし、ゲート絶縁層から離れた部分を０＜Ｘ＜
１の範囲とすることによりＸの値を階段状に変化させた
ことを特徴とする特許請求の範囲第１項記載の絶縁ゲー
ト薄膜トランジスタ。(2) a-3ix, C+-x constituting the semiconductor layer
: The value of X in the portion of II that is in contact with the dielectric layer is set to X=1, and the portion away from the gate insulating layer is set to 0<X<
2. The insulated gate thin film transistor according to claim 1, wherein the value of
とする特許請求の範囲第１項記載の絶縁ゲート薄膜トラ
ンジスタ。(3) The insulated gate thin film transistor according to claim 1, wherein the semiconductor layer is doped with an impurity.
ｘＣ＋−ｘ：ＩＩからなる半導体層、ゲート絶縁層、ゲ
ート電極を、前記絶縁基板の裏面より露光してセルフア
ライメントによって形成することを特徴とする絶縁ゲー
ト薄膜トランジスタの製造方法。(4) Source and drain electrodes, a-3i, on the insulating substrate
A method for manufacturing an insulated gate thin film transistor, characterized in that a semiconductor layer, a gate insulating layer, and a gate electrode made of xC+-x:II are formed by self-alignment by exposure from the back surface of the insulating substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25009083A JPS60142566A (en) | 1983-12-28 | 1983-12-28 | Insulated gate thin film transistor and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25009083A JPS60142566A (en) | 1983-12-28 | 1983-12-28 | Insulated gate thin film transistor and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60142566A true JPS60142566A (en) | 1985-07-27 |
Family
ID=17202661
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25009083A Pending JPS60142566A (en) | 1983-12-28 | 1983-12-28 | Insulated gate thin film transistor and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60142566A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6230376A (en) * | 1985-07-31 | 1987-02-09 | Fujitsu Ltd | Manufacture of thin film transistor |
| FR2601801A1 (en) * | 1986-07-16 | 1988-01-22 | Morin Francois | ACTIVE MATRIX DISPLAY SCREEN USING HYDROGENIC AMORPHOUS SILICON CARBIDE AND METHOD OF MANUFACTURING THE SAME |
| JPS6341077A (en) * | 1986-08-06 | 1988-02-22 | Nippon Sheet Glass Co Ltd | Manufacture of thin-film transistor |
| EP0276002A2 (en) * | 1987-01-23 | 1988-07-27 | Hosiden Corporation | Thin film transistor |
| JPH01115162A (en) * | 1987-10-29 | 1989-05-08 | Matsushita Electric Ind Co Ltd | Thin film transistor and manufacture thereof |
| EP0322590A2 (en) * | 1988-01-04 | 1989-07-05 | International Business Machines Corporation | Thin film semiconductor device |
| JPH02275672A (en) * | 1989-03-30 | 1990-11-09 | Nippon Steel Corp | Thin film transistor |
-
1983
- 1983-12-28 JP JP25009083A patent/JPS60142566A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6230376A (en) * | 1985-07-31 | 1987-02-09 | Fujitsu Ltd | Manufacture of thin film transistor |
| FR2601801A1 (en) * | 1986-07-16 | 1988-01-22 | Morin Francois | ACTIVE MATRIX DISPLAY SCREEN USING HYDROGENIC AMORPHOUS SILICON CARBIDE AND METHOD OF MANUFACTURING THE SAME |
| JPS6341077A (en) * | 1986-08-06 | 1988-02-22 | Nippon Sheet Glass Co Ltd | Manufacture of thin-film transistor |
| EP0276002A2 (en) * | 1987-01-23 | 1988-07-27 | Hosiden Corporation | Thin film transistor |
| JPH01115162A (en) * | 1987-10-29 | 1989-05-08 | Matsushita Electric Ind Co Ltd | Thin film transistor and manufacture thereof |
| EP0322590A2 (en) * | 1988-01-04 | 1989-07-05 | International Business Machines Corporation | Thin film semiconductor device |
| JPH02275672A (en) * | 1989-03-30 | 1990-11-09 | Nippon Steel Corp | Thin film transistor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5920772A (en) | Method of fabricating a hybrid polysilicon/amorphous silicon TFT | |
| US6537843B2 (en) | Thin film transistor and method of manufacturing the same | |
| US5061648A (en) | Method of fabricating a thin-film transistor | |
| JP2656495B2 (en) | Method for manufacturing thin film transistor | |
| JPH06148685A (en) | Liquid crystal display device | |
| JP2739642B2 (en) | Thin film transistor and method of manufacturing the same | |
| JPH08172202A (en) | Thin film transistor and manufacture thereof | |
| US6124153A (en) | Method for manufacturing a polysilicon TFT with a variable thickness gate oxide | |
| CN112086561A (en) | Light sensing device, manufacturing method thereof and display panel | |
| CN109300841B (en) | The manufacturing method of array substrate | |
| US10629834B2 (en) | Thin film transistor, method for preparing the same, and display device | |
| KR0171648B1 (en) | Thin film device and method of producing the same | |
| JPS60142566A (en) | Insulated gate thin film transistor and manufacture thereof | |
| US20040086807A1 (en) | Method of fabricating thin film transistor | |
| JPH023308B2 (en) | ||
| JP3163844B2 (en) | Method of manufacturing inverted staggered thin film field effect transistor | |
| JP3093314B2 (en) | Thin film transistor and method of manufacturing the same | |
| JP2000036603A (en) | Manufacture of thin-film transistor | |
| JP2862737B2 (en) | Thin film transistor and method of manufacturing the same | |
| JP2630195B2 (en) | Thin film field effect transistor and method of manufacturing the same | |
| JPH0534837B2 (en) | ||
| JP3179160B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH07142737A (en) | Manufacture of thin-film transistor | |
| JPH01115162A (en) | Thin film transistor and manufacture thereof | |
| JPH05343690A (en) | Thin film transistor and manufacture thereof |