JPS6080600U - Electrically erasable PROM - Google Patents

Electrically erasable PROM

Info

Publication number
JPS6080600U
JPS6080600U JP17255583U JP17255583U JPS6080600U JP S6080600 U JPS6080600 U JP S6080600U JP 17255583 U JP17255583 U JP 17255583U JP 17255583 U JP17255583 U JP 17255583U JP S6080600 U JPS6080600 U JP S6080600U
Authority
JP
Japan
Prior art keywords
electrically erasable
erasable prom
write operation
built
completed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17255583U
Other languages
Japanese (ja)
Inventor
市田 憲治
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP17255583U priority Critical patent/JPS6080600U/en
Publication of JPS6080600U publication Critical patent/JPS6080600U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本実施例のブロック図を示し、第2図は動作
のタイミングチャート図を示す。 尚、図において、1・・・・・・クロック発生回路、2
・・・・・・カウンター回路、3・・・・・・フリップ
フロップである。
FIG. 1 shows a block diagram of this embodiment, and FIG. 2 shows a timing chart of the operation. In the figure, 1... clock generation circuit, 2
. . . Counter circuit, 3 . . . Flip-flop.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 書込み動作後、書込まれたデータを読み出し、書込みデ
ータと比較する事により、書込み動作の完了を確認する
マージン測定回路番内蔵した電気的消去型FROMにて
、設定された時間内に書込み動作が完了しない時のみ、
読み出し禁止信号を出力する回路を内蔵した事を特徴と
する電気的消去型FROM0
After the write operation, the written data is read and compared with the write data to confirm the completion of the write operation.The write operation is completed within the set time using the electrically erasable FROM with a built-in margin measurement circuit number. Only if it is not completed,
Electrically erasable FROM0 featuring a built-in circuit that outputs a read inhibit signal
JP17255583U 1983-11-08 1983-11-08 Electrically erasable PROM Pending JPS6080600U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17255583U JPS6080600U (en) 1983-11-08 1983-11-08 Electrically erasable PROM

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17255583U JPS6080600U (en) 1983-11-08 1983-11-08 Electrically erasable PROM

Publications (1)

Publication Number Publication Date
JPS6080600U true JPS6080600U (en) 1985-06-04

Family

ID=30376115

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17255583U Pending JPS6080600U (en) 1983-11-08 1983-11-08 Electrically erasable PROM

Country Status (1)

Country Link
JP (1) JPS6080600U (en)

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