JPS60131700A - Non-volatile semiconductor memory - Google Patents
Non-volatile semiconductor memoryInfo
- Publication number
- JPS60131700A JPS60131700A JP58240316A JP24031683A JPS60131700A JP S60131700 A JPS60131700 A JP S60131700A JP 58240316 A JP58240316 A JP 58240316A JP 24031683 A JP24031683 A JP 24031683A JP S60131700 A JPS60131700 A JP S60131700A
- Authority
- JP
- Japan
- Prior art keywords
- test
- row
- column
- cells
- row decoder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- Read Only Memory (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
（技術分野）
本発明は不揮発性半導体メモリに係ね、特に紫外線照射
等によりメモリ内容を消去可能な不揮発性半導体メモリ
に関する。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a nonvolatile semiconductor memory, and more particularly to a nonvolatile semiconductor memory whose memory contents can be erased by ultraviolet irradiation or the like.
（従来技術）
近年マイクロコンピュータの急激な発展につれて太きく
伸びてきた分野としてリードオンリーメモリ（以下、Ｒ
ＯＭという。）示ある。ＲＯＭは構造が比較的簡単で集
積度が高く、コストが安く、又書込み機能はないか、あ
ってもランダムアクセス−モリに比較してやや性能的に
は低くても良いとするメモリである。(Prior art) Read-only memory (hereinafter referred to as R
It's called OM. ) is shown. ROM is a memory that has a relatively simple structure, high degree of integration, low cost, and has no write function, or even if it does have a write function, its performance may be slightly lower than that of random access memory.
最も基本的なＲＯＭはＩＣ製造工程で使用するマスクの
パ□ターンに情報を入れておくもので、マス、？）（、
ＯＭと呼ばれる。メモリ内容の変更は不可ｍｌであるが
、書込みの確実性、メモリの安定性に優□れており、同
一記憶内容のものを大量に作る場合には単価が安くなる
利点があるが、・少量多品種には適さず、ユーザからそ
のパターン情報を入手にてから製品となるまで一定期間
を髪するため利便性にも欠ける。一方、使用者がフィー
ルドで自由にメモリ内容を書込める、ようにしたＲＯＭ
がプログラム可能ＲＯＭで、本発明における紫外線等に
よりメモリ内容を消去可能なＦＲＯＭ（以下、ＥＰＲＯ
Ｍという。）はこの種のものである。ＢＦＲＯＭは紫外
線照射のために特殊なパッケージが必要であり、ＲＯＭ
に比べ単価が高いという欠点がある。The most basic ROM stores information in the mask pattern used in the IC manufacturing process. )(,
It is called OM. Although the memory contents cannot be changed, it has superior writing reliability and memory stability, and has the advantage of being cheaper per unit when producing large quantities of the same memory contents. It is not suitable for a wide variety of products, and it lacks convenience because it takes a certain period of time from the time the pattern information is obtained from the user until it is made into a product. On the other hand, ROM allows the user to freely write the memory contents in the field.
is a programmable ROM, and in the present invention, FROM (hereinafter referred to as EPRO) whose memory contents can be erased by ultraviolet rays etc.
It's called M. ) is of this kind. BFROM requires a special package for UV irradiation, and ROM
The disadvantage is that the unit price is higher than that of .
しかしフィールドでの利便性に優れており大きな市場が
形成されている。However, it is highly convenient in the field, and a large market has been formed.
ところで、ＥＦＲＯＭのメモリの安定性、すなわち情報
書込み後の保持特性は極めて良好であり、ＲＯＭの代用
として十分なものであることが知られるようになり、特
殊なパッケージを使用せず、プラスチックバックージ等
ＲＯＭと同様なパッケージとして、ただしメモリ内容の
消去は無くし、めで安くなり、フィールドでの利便性も
あり、ユーザが製品を入手するにも短期間となり、又ス
トックとして持ち得るＥＰＲＯＭ（以下、ワンライトＥ
ＦＲＯＭという。）が考えられた。By the way, it has come to be known that the stability of EFROM memory, that is, the retention characteristics after information is written, is extremely good, and that it is a sufficient substitute for ROM. EPROMs (hereinafter referred to as One light E
It's called FROM. ) was considered.
しかし、このワンライトＥＦＲＯＭは製品としての機能
試験は組立前のウエノ・一段階だけとなり、組立後は、
全くデータがメモリされていない状態混入比率が高いこ
とになる。またデータの読出し時間、いわゆるアクセス
タイム等についても十分チェック出来ないことになって
しまう。However, for this one-light EFROM, the functional test as a product is only performed at one stage before assembly, and after assembly,
This means that the ratio of states in which no data is stored at all is high. Furthermore, data read time, so-called access time, etc. cannot be sufficiently checked.
第１図はかかる従来のＥＰＲＯＭの一例の要部を示すブ
ロック図であり、入出力８ビツト構成のＥＦＲＯＭ の
−例である。アドレス入力ＡｏからＡｎｌにより列デコ
ーダ２２行デコーダ３の選択によってメモリセルマトリ
クス部６への入出力データ０゜〜０７の入出力が、入出
力バッファ４２列セレクタ５を介して入出力コントロー
ル部ｌによってなされる。すなわち、この従来例におい
ては、なんら試験機能が含まれていないので、組立後に
おいては任意の機能試験を行なうことは出来ない。FIG. 1 is a block diagram showing the essential parts of an example of such a conventional EPROM, and is an example of an EFROM having an input/output 8-bit configuration. Input/output data 0° to 07 to the memory cell matrix section 6 is input/outputted to the memory cell matrix section 6 by the selection of the column decoder 22 and the row decoder 3 by the address inputs Ao to Anl, and is controlled by the input/output control section l via the input/output buffer 42 and the column selector 5. It will be done. That is, since this conventional example does not include any test function, it is not possible to perform any functional test after assembly.
そこで、メモリマトリクス部６以外に試験用のセルを設
けて組立後の機能試験を行なう方法が考えられたが、す
べての周辺回路、又、アクセスタイム等のＡＣ特性まで
試験出来ない欠点があった。Therefore, a method was considered in which a test cell was provided in addition to the memory matrix section 6 to perform a functional test after assembly, but this method had the drawback that it was not possible to test all peripheral circuits and AC characteristics such as access time. .
（発明の目的）
本発明の目的は、上記欠点を除去することにより、従来
のＥＦＲＯＭとしての機能はそのまま有すると共に、゛
十分な機能試験ができ、かつ低コストで高信頼性の不揮
発性半導体メモリを提供することにめる。(Objective of the Invention) The object of the present invention is to provide a non-volatile semiconductor memory which retains the functions of a conventional EFROM and which can perform sufficient functional tests and is low-cost and highly reliable by eliminating the above-mentioned drawbacks. We are committed to providing the following.
（発明の構成）
本発明の不揮発性半導体メモリは、複数の試験用行線に
よって駆動される複数の第１試験用セルと、前記試験用
行線を選択、する複数の試験用行デコーダと、複数の試
験用列線によって駆動されるセルは各列線の列セレクタ
側に最も近い位置と最も遠い位置に交互に１個は配置さ
れるよ？各列線に少くとも１個配置され、前記第２試験
用セルは各行線の行デコーダに最も近い位置と最も遠い
位置に交互に１個は配置されるよう各行線に少くとも１
個配置されることから構成される。(Structure of the Invention) A nonvolatile semiconductor memory of the present invention includes a plurality of first test cells driven by a plurality of test row lines, a plurality of test row decoders that select the test row lines, and a plurality of test row decoders that select the test row lines. Cells driven by multiple test column lines are placed alternately at the closest position and the farthest position from the column selector side of each column line. At least one second test cell is arranged on each column line, and at least one second test cell is arranged on each row line, with one second test cell being arranged alternately at the closest position and the farthest position from the row decoder of each row line.
It consists of arranging individual pieces.
（実施例）
以下、本発明の実施例について図面を８照して説明する
。(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.
第２図は本発明の一実施例の要部を示すブロック図で、
第１図と同じく入出力８ビツト構成のＥＰＲ，ＯＭを表
わしている。FIG. 2 is a block diagram showing the main parts of an embodiment of the present invention.
As in FIG. 1, EPR and OM are shown with an 8-bit input/output configuration.
本実施例は、複数の試験用行線ＸＴｏ〜ＸＴｋによって
駆動される複数の第１試験用セル（’ｒｃ）１１と、試
験用行線ｘ ’ｒｏ −Ｘ Ｔｋを選択する複数の試験
用行デコーダ１２と、複数の試験用列・線ＹＴ。This embodiment includes a plurality of first test cells ('rc) 11 driven by a plurality of test row lines XTo to XTk, and a plurality of test rows that select the test row line x'ro - A decoder 12 and a plurality of test columns/lines YT.
〜ＹＴＪによって駆動される複数の第２試験用セ用セル
ｌｌは各列線のり１ｊセレクタ側に最も近い位置と最も
遠い位置に♀互に１個は配置されるよう各列線に１個配
置され、第２試験用セル１３は各行線の行デコーダに最
も近い位置と最も遠い位置に交互に１個は配置されるよ
う各行線に１個配置されることから構成される。~ A plurality of second test cells ll driven by YTJ are arranged on each column line so that one cell is placed at the position closest to the selector side of each column line 1j and one cell is placed at the farthest position from the selector side. One second test cell 13 is arranged on each row line such that one cell is alternately arranged at the position closest to the row decoder and one at the farthest position from the row decoder of each row line.
すなわち、本実施例は第１図に示した従来例に対して、
第１．第２試験用セル１１．１３とそれの選択制御用と
して試験用行デコーダ１２．試験用列Ｃレフタ１４を設
けたことから構成される。In other words, this embodiment differs from the conventional example shown in FIG.
1st. A second test cell 11.13 and a test row decoder 12.13 for selection control thereof. It is constructed by providing a test row C lefter 14.
次に本実施例の動作について説明する。Next, the operation of this embodiment will be explained.
試験用行デコーダ１２．試験用
は、通常に使用される場合には非選択状態にあり、従来
のＥＦＲＯＭと何ら変るものでない。一方、試験状態に
入った場合には、試験性デコータ“１２が選択された場
合は、メインの行デコーダ３はＪ卜選択となり、列セレ
クタ５によって各列線に接続される第１試験用セル１１
への書込み、読出しの試験が行なわれる。Test row decoder 12. The test memory is in a non-selected state during normal use, and is no different from a conventional EFROM. On the other hand, when entering the test state, if the test decoder "12" is selected, the main row decoder 3 is set to "J", and the column selector 5 selects the first test cell connected to each column line. 11
Write and read tests are performed.
又、試験用列セレクタ１４が選択された場合はメインの
列セレクタ５は非選択となり、行デコーダ３によって各
行線に接続される第２試験用セル１３への書込み、読出
しの試験が行われる。ここで、試験用行デコーダ１２に
よって選択される各列線へ接続されている第１試験用セ
ル１１は、各列線１列交互に、メインの列セレクタ５か
らみて最も近い位置と、最も遠い位置に配置しであるの
で、列線の浮遊容量，抵抗等に基因するスピード −の
遅延の試験をも行なうことができる。又、試験用列セレ
クタ１４によって選択される各行線へ接続されている第
２試験用セル１３は、各行＃１行交互に、メインの行デ
コーダ３から最も近い位置 。Further, when the test column selector 14 is selected, the main column selector 5 is not selected, and the row decoder 3 performs writing and reading tests on the second test cells 13 connected to each row line. Here, the first test cells 11 connected to each column line selected by the test row decoder 12 are alternately connected to each column line at the closest position and the farthest position when viewed from the main column selector 5. Since it is arranged at a fixed position, it is also possible to test speed delays caused by stray capacitance, resistance, etc. of column lines. Further, the second test cells 13 connected to each row line selected by the test column selector 14 are alternately connected to each row #1 at the position closest to the main row decoder 3.
と、最も遠い位置に配置しであるので、行線の浮遊容量
、抵抗等に基因するスピードの遅延の試験を行なうこと
ができる。すなわち、メインのメモリセルの機能試験は
もちろん、アクセスタイム等ＡＣ特性をも試験可能であ
る。Since it is placed at the farthest position, it is possible to test for speed delays caused by stray capacitance, resistance, etc. of the row lines. That is, it is possible to test not only the function of the main memory cell but also AC characteristics such as access time.
なお、上記説明は紫外線消去型のＥＦＲＯＭの場合につ
いて述べたが、電気的消去可能ＦＲＯＭ等他のＦＲＯＭ
においても同様である。又、第２図は入出力全ビット共
通にみた場合であるが、各入出力ビット単位で適用する
ことも可能である。Note that although the above explanation deals with the case of ultraviolet erasable EFROM, other FROMs such as electrically erasable FROM can also be used.
The same applies to Further, although FIG. 2 shows a case in which all input and output bits are viewed in common, it is also possible to apply the method to each input and output bit unit.
更に、Ｎ−チャネル型，Ｐ−チャネル型，０ＭＯ８型等
いずれにおいても適用可能であることは明白である。Furthermore, it is obvious that the present invention can be applied to any of the N-channel type, P-channel type, 0MO8 type, etc.
（発明の効果）
以上、詳細に説明したとおり、本発明の不揮発性半導体
メモリは、試験用セルとその選択手段を有しているので
、従来のように組立前のウェーッ・段階のみでなく組立
後においても自由に機能試験ができるという効果を有し
ている。従って本発明によれば、低コストで高信頼性の
消去可能な不揮発性半導体メモリが得られる。(Effects of the Invention) As explained in detail above, the nonvolatile semiconductor memory of the present invention has a test cell and its selection means, so it can be used not only in the wafer stage before assembly but also in the assembly process as in the conventional method. This has the advantage that functional tests can be carried out freely even afterwards. Therefore, according to the present invention, a low-cost, highly reliable erasable non-volatile semiconductor memory can be obtained.
第１図は従来の不揮発性半導体メモリの一例の要部を示
すブロック図、第２図は本発明の一実施例の要部を示す
ブロック図である。
１・・・・・・入出力コントロール部、２・・・・・・
列デコーダ、３・・・・・・行デコーダ、４・・・・・
・入出力バッファ、５・・・・・・列セレクタ、６・・
・・・・メモリセルマトリクス部，１１・・・・・・第
１試験用セル（ＴＯ）、１２・・・・・・試験用行デコ
ーダ、１３・・・・・・第２試験用セル（ＴＣ）、１
４ ・＝−・・試験用列セレクタ、Ａｏ−Ａｌｌ，Ａｌ
ｌ＋１〜Ａｆｆｉ・・・・・・アドレス人力、０ｏ〜０
７・・・・・・入出力、データ、ＸＴｏ−ＸＴｋ・・・
・・、・試験用行線、Ｙｏ−Ｙｊ・・・・・・試験用列
線。FIG. 1 is a block diagram showing a main part of an example of a conventional nonvolatile semiconductor memory, and FIG. 2 is a block diagram showing a main part of an embodiment of the present invention. 1... Input/output control section, 2...
Column decoder, 3... Row decoder, 4...
・I/O buffer, 5...Column selector, 6...
...Memory cell matrix section, 11...First test cell (TO), 12...Test row decoder, 13...Second test cell ( TC), 1
4 ・=-・Test column selector, Ao-All, Al
l+1~Affi...Address manual, 0o~0
7...Input/output, data, XTo-XTk...
..., Test row line, Yo-Yj... Test column line.
Claims (1)
セルと、前記試験用行線を選択する複数の試験用行デコ
ーダと、複数の献−用列線によつて駆動される複数の第
２試験用セルと、前記試験用列線を選択する複数の試験
用列セレクタとを含み、前記薬１試験用セルは各列線の
列セレクタ側に最も近い位置と最も遠い位置に交互に１
個は配置されるよう各列線に少くとも１個配置され、前
記第２試験用セルは各行線の行デコーダに最も近い位置
と最も遠い位置に交互に１個は°装置されるよう各行線
に少くとも１個配置されるととを特徴とする不揮発性半
導体メモリ。A plurality of first test cells driven by a plurality of test row lines, a plurality of test row decoders that select the test row lines, and a plurality of test row decoders driven by a plurality of dedicated column lines. a second test cell and a plurality of test column selectors for selecting the test column lines, and the drug 1 test cells are arranged alternately at positions closest to and farthest from the column selector side of each column line. 1
At least one second test cell is arranged in each column line so that the second test cell is arranged in each row line so that one cell is arranged alternately at a position closest to the row decoder of each row line and one at a position farthest from the row decoder of each row line. A non-volatile semiconductor memory characterized in that at least one non-volatile semiconductor memory is arranged in.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58240316A JPS60131700A (en) | 1983-12-20 | 1983-12-20 | Non-volatile semiconductor memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58240316A JPS60131700A (en) | 1983-12-20 | 1983-12-20 | Non-volatile semiconductor memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60131700A true JPS60131700A (en) | 1985-07-13 |
| JPH0232720B2 JPH0232720B2 (en) | 1990-07-23 |
Family
ID=17057649
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58240316A Granted JPS60131700A (en) | 1983-12-20 | 1983-12-20 | Non-volatile semiconductor memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60131700A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62128099A (en) * | 1985-11-28 | 1987-06-10 | Fujitsu Ltd | Test circuit for one-time rom |
| JPH04106795A (en) * | 1990-08-28 | 1992-04-08 | Nec Corp | Semiconductor memory |
| JP2001210098A (en) * | 2000-01-26 | 2001-08-03 | Fujitsu Ltd | Semiconductor memory and method for detecting defect of word line of semiconductor memory |
| CN1096571C (en) * | 1997-09-30 | 2002-12-18 | 株式会社荏原制作所 | Turbo type fluid machinery |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5466042A (en) * | 1977-11-04 | 1979-05-28 | Nec Corp | Programable read-only memory |
-
1983
- 1983-12-20 JP JP58240316A patent/JPS60131700A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5466042A (en) * | 1977-11-04 | 1979-05-28 | Nec Corp | Programable read-only memory |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62128099A (en) * | 1985-11-28 | 1987-06-10 | Fujitsu Ltd | Test circuit for one-time rom |
| JPH04106795A (en) * | 1990-08-28 | 1992-04-08 | Nec Corp | Semiconductor memory |
| CN1096571C (en) * | 1997-09-30 | 2002-12-18 | 株式会社荏原制作所 | Turbo type fluid machinery |
| JP2001210098A (en) * | 2000-01-26 | 2001-08-03 | Fujitsu Ltd | Semiconductor memory and method for detecting defect of word line of semiconductor memory |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0232720B2 (en) | 1990-07-23 |
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