JPS60131051U - Watchdog circuit - Google Patents

Watchdog circuit

Info

Publication number
JPS60131051U
JPS60131051U JP1941984U JP1941984U JPS60131051U JP S60131051 U JPS60131051 U JP S60131051U JP 1941984 U JP1941984 U JP 1941984U JP 1941984 U JP1941984 U JP 1941984U JP S60131051 U JPS60131051 U JP S60131051U
Authority
JP
Japan
Prior art keywords
count
signal
watchdog circuit
cpu
counting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1941984U
Other languages
Japanese (ja)
Inventor
日江井　政一
Original Assignee
富士電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士電機株式会社 filed Critical 富士電機株式会社
Priority to JP1941984U priority Critical patent/JPS60131051U/en
Publication of JPS60131051U publication Critical patent/JPS60131051U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の一実施例を示す回路図、第２図は第１
図の動作を説明するタイムチャート、第３図は本考案の
他の実施例を示す回路図である。 １・・・マイクロコンピュータ（マイコン）、２・・・
メモリ、３・・・入出力回路（ｉ　／　ｏ回路）、４・
・・発振器、５・・・カウンタ（Ａカウンタ）、５１・
・・Ｂカウンタ、６・・・ＲＳフリップフロップ（Ｆ／
Ｆ）、７．８，１０・・・ＯＲゲート、９，１３・・・
ワンショット回路。Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
FIG. 3 is a time chart explaining the operation shown in FIG. 3, and FIG. 3 is a circuit diagram showing another embodiment of the present invention. 1...Microcomputer (microcomputer), 2...
Memory, 3... Input/output circuit (I/O circuit), 4.
...Oscillator, 5...Counter (A counter), 51.
...B counter, 6...RS flip-flop (F/
F), 7.8, 10...OR gate, 9, 13...
One shot circuit.

Claims (2)

【実用新案登録請求の範囲】[Scope of utility model registration request] （１）クロックパルスの出力手段と、ＣＰＵの起動信号
によって前記クロックパルスの計数を開始し、ＣＰＵか
ら所定の時間毎に出力されるクリヤ信号によって計数値
をクリヤされて再度前記の計数を開始するとともに、前
記の計数値が所定の値を越えるときは、カウントアツプ
信号を出力する計数手段と、を備え、前記カウントアツ
プ信号によりＣＰＵのリセット、再起動を行うようにし
たウォッチドッグ回路において、前記カウントアツプ信
号によって動作し、前記ＣＰＵのリセットを保持するリ
セット保持手段、を備えたことを特徴とするウォッチド
ッグ回路。(1) Counting of the clock pulses is started by a clock pulse output means and a start signal of the CPU, and the count value is cleared by a clear signal outputted from the CPU at predetermined intervals and the counting is started again. The watchdog circuit also includes a counting means for outputting a count-up signal when the counted value exceeds a predetermined value, and the watchdog circuit resets and restarts the CPU using the count-up signal. A watchdog circuit comprising: reset holding means operated by a count-up signal and holding the CPU reset. （２）実用新案登録請求の範囲第１項に記載の回路にお
いて、前記リセット保持手段は、前記カウントアツプ信
号を計数し、この計数値が所定の値となったとき前記リ
セットを保持する手段であることを特徴とするウォッチ
ドッグ回路。(2) Utility Model Registration In the circuit according to claim 1, the reset holding means is means for counting the count-up signal and holding the reset when the counted value reaches a predetermined value. A watchdog circuit characterized by:
JP1941984U 1984-02-14 1984-02-14 Watchdog circuit Pending JPS60131051U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1941984U JPS60131051U (en) 1984-02-14 1984-02-14 Watchdog circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1941984U JPS60131051U (en) 1984-02-14 1984-02-14 Watchdog circuit

Publications (1)

Publication Number Publication Date
JPS60131051U true JPS60131051U (en) 1985-09-02

Family

ID=30508984

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1941984U Pending JPS60131051U (en) 1984-02-14 1984-02-14 Watchdog circuit

Country Status (1)

Country Link
JP (1) JPS60131051U (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01284914A (en) * 1988-05-12 1989-11-16 Fujitsu Ltd Power-on resetting system
JPH02136939A (en) * 1988-11-17 1990-05-25 Rohm Co Ltd Data processor
JPH03192410A (en) * 1989-12-21 1991-08-22 Matsushita Electric Ind Co Ltd Communication equipment

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01284914A (en) * 1988-05-12 1989-11-16 Fujitsu Ltd Power-on resetting system
JPH02136939A (en) * 1988-11-17 1990-05-25 Rohm Co Ltd Data processor
JPH03192410A (en) * 1989-12-21 1991-08-22 Matsushita Electric Ind Co Ltd Communication equipment

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