JPS60130218A - Frequency synthesizer - Google Patents
Frequency synthesizerInfo
- Publication number
- JPS60130218A JPS60130218A JP58238598A JP23859883A JPS60130218A JP S60130218 A JPS60130218 A JP S60130218A JP 58238598 A JP58238598 A JP 58238598A JP 23859883 A JP23859883 A JP 23859883A JP S60130218 A JPS60130218 A JP S60130218A
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- output
- divider
- signal
- synthesizer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000010355 oscillation Effects 0.000 claims abstract description 6
- 238000000605 extraction Methods 0.000 claims 1
- 238000009434 installation Methods 0.000 claims 1
- 230000010354 integration Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010295 mobile communication Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000762 glandular Effects 0.000 description 1
- 230000035935 pregnancy Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
- H03L7/185—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using a mixer in the loop
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は位相同期ループ(PLL)を用いた周波数シ
ンセサイザに関するものであり、特にIC化に適した直
接分周方式の周波数シンセサイザにおいて、周波数切替
時やt、 諒投入時における応答時間を従来に比して著
しく短かくすることか可能なものを得ようとするもので
ある。[Detailed Description of the Invention] The present invention relates to a frequency synthesizer using a phase-locked loop (PLL), and in particular, in a frequency synthesizer using a direct frequency division method that is suitable for IC implementation, the present invention relates to a frequency synthesizer that uses a phase-locked loop (PLL). The purpose of this invention is to significantly shorten the response time compared to the conventional method.
〈従来技術〉
無線通信、とりわけ移動通信の分1!1・で(弓、11
に4.りある周波数を有効に利用するため、多ky、の
無線機が相数の無線周波数を共有し、各無線4幾がこれ
らの無線周波数の内の一波を必要時に選択してコ11信
を行なうマルチチャネル・アクセス法が5辿ニ広がりつ
つある。この方法では各無線像に数十チャネル−数千チ
ャネルという多数の無線周波数を切なrる機能を持たせ
るために周波数シンセサイザが・I/、・要と々る13
周周波数シンセサイザは様々な型式かあるが、移tj?
li 、’t4信用としてVHF”帯〜]、GH2程度
という高い1^1波数で動作し、周波数安定度か良好で
、しかも小形化・IC化・無ル61整化が容易であると
いう条件を考慮して、従来は直接分周方式の周波数シン
セサイザが用いられてきた。面接分周方式の一種である
パルススワロ方式の周波数シンセサイザの構成を第1図
に示す。<Prior art> Wireless communication, especially mobile communication (bow, 11
4. In order to make effective use of certain frequencies, multiple radios share a number of radio frequencies, and each radio selects one of these radio frequencies when necessary to send a radio signal. Multi-channel access methods are becoming more widespread. In this method, in order to provide each radio image with the function of cutting a large number of radio frequencies, from tens to thousands of channels, a frequency synthesizer is required to
There are various types of frequency synthesizers, but what is the difference between them?
The conditions are that it operates at a high 1^1 wave number of about GH2, has good frequency stability, and is easy to miniaturize, integrate into ICs, and simplify. In consideration of this, a direct frequency division type frequency synthesizer has been used in the past.The configuration of a pulse swallow type frequency synthesizer, which is a type of surface frequency division type, is shown in FIG.
第1図において電圧制御発振器(VCO)11からの出
力は7ノセサイザ出力として出力端子12へ出力される
と同時に、可変分周部13へ入力され、可変分周部13
において設定端子14から設定された151波数に応じ
た整数比でシンセサイザ出力をN分周した信号が得られ
る。このN分周出力信号は位相比較器15のηう:゛1
の入力端子へ加えられる。一方、位相比較器15の第2
の入力※11.1子にd基準発損益16の出力を固定分
周器17でに分周して得た基飴信−弓か加えられる。こ
の基糸信号の周波数(位相比較周波数)は前記無線チャ
ネルの熱線周波数間隔fchと一致するように選ばれて
いる。位相比iI5!器15は入力された2つの信号を
位相比較して誤差信号として出力する。この誤差信号は
必要に尾、じてループフィルタ18を介してVCOII
に制御信号として与えられる。この結果、V C011
−t1]変分周部13−位相比較器15−ループフィル
ター18−VCOIIなる位相同期ループ°(PLLル
ープ)が構成され、出力端子12に無11児周波数間隔
fchのN倍の周波数の信号が得られる。n」変分周部
13の総合分周数Nは、周波数設定端子14から入力さ
れたコード帯号によって設定され、この絶1図に示した
構成は周波数シンセサイザとして動作する。In FIG. 1, the output from the voltage controlled oscillator (VCO) 11 is output to the output terminal 12 as a 7-noiseizer output, and at the same time is input to the variable frequency divider 13.
A signal is obtained by dividing the frequency of the synthesizer output by N using an integer ratio according to the 151 wave number set from the setting terminal 14. This N-divided output signal is the output signal of the phase comparator 15.
is applied to the input terminal of On the other hand, the second
The input of *11.1 is the base value obtained by dividing the output of the d standard profit and loss 16 by the fixed frequency divider 17. The frequency of this basic thread signal (phase comparison frequency) is selected to match the hot wire frequency interval fch of the wireless channel. Phase ratio iI5! The device 15 compares the phases of the two input signals and outputs the result as an error signal. This error signal is passed through the loop filter 18 to the VCOII as necessary.
is given as a control signal. As a result, V C011
-t1] A phase-locked loop (PLL loop) consisting of variational frequency divider 13 - phase comparator 15 - loop filter 18 - VCOII is constructed, and a signal with a frequency N times the frequency interval fch is output to the output terminal 12. can get. The total frequency division number N of the variable frequency division section 13 is set by the code band symbol inputted from the frequency setting terminal 14, and the configuration shown in FIG. 1 operates as a frequency synthesizer.
とXで可変分局部13について説明する。vIIF帯〜
IG+(2のシンセサイザ出力を25 K t(z f
i8度のイずl相比較周波敏捷で分周するためには、可
変分周部1513の分周数Nil″1:数万程度となる
。このような大きな分周数を得るために、可変分局部1
3を、。The variable branching section 13 will be explained using and X. vIIF band~
The synthesizer output of IG+(2 is 25 K t(z f
In order to divide the frequency with i8 degrees of phase comparison frequency agility, the frequency division number Nil''1 of the variable frequency dividing section 1513 is approximately tens of thousands.In order to obtain such a large frequency division number, the variable Branch part 1
3.
予め入力信号計数M 1−17.程度址で分周する高速
の1111随分周器]、 3 aと、前置分周器1.3
aの出力をさらに位相比較周波敏捷で分周する低消費
電力の主分周器13bと、前置分周器部j御用カθンタ
13cとに分けて(構成している。こXで前置分周器1
3aは2つの分局モードを持ち、制御用カウンタ13c
の出力が1のとき÷Pモード、l1lr+lI用カウン
タ13Cの出力が0のとき+(P+1)モードになるも
のとする。また、主分周器]、 3 bにはその分周数
iVIを任意に設定できるプログラマブルカウンタが用
いられる。制御用カウンタ13cの出力は、前16分周
器]、 3 aめ出力をAザイクルだけ開数すると1に
セットされ、かつ主分周器131〕から分局パルスが出
力される毎にOにリセットされるものとする。3たソし
ARMとする。このとき可変分周部]3の総合分周数N
は、
N=A(P+1)+(M−A)・P=M −P十A (
1,1となる。こ\でAが0から°(P−1)tでの全
ての値をηyれるように制御用カウンタ13cもプログ
ラマブルカウンタで構成すれば、Nは任意の自然数の値
を取ることができる。しだかつて第1図に示したパルス
スワロ方式の構成を用いることによって単一のp]変分
周器と等価な分周動作を’IWることかできる。Preliminary input signal count M 1-17. A high-speed 1111 frequency divider that divides the frequency by degrees], 3a, and a prescaler 1.3
The output of a is further divided into a low power consumption main frequency divider 13b which divides the frequency by phase comparison frequency agility, and a counter 13c for use in the pre-frequency divider section j. Positional frequency divider 1
3a has two branch modes, and a control counter 13c.
When the output of the counter 13C for l1lr+lI is 0, the mode is ÷P mode, and when the output of the l1lr+lI counter 13C is 0, the mode is +(P+1). Furthermore, a programmable counter is used for the main frequency divider] and 3b, the frequency division number iVI of which can be arbitrarily set. The output of the control counter 13c is set to 1 when the output of the first 16th frequency divider is divided by A cycles, and is reset to O every time a division pulse is output from the main frequency divider 131. shall be carried out. 3. Make it ARM. At this time, the total frequency division number N of variable frequency division section] 3
is, N=A(P+1)+(M-A)・P=M-P0A (
It becomes 1,1. If the control counter 13c is also configured as a programmable counter so that A can take all values from 0 to °(P-1)t, then N can take the value of any natural number. However, by using the configuration of the pulse swirl system shown in FIG. 1, it is possible to perform a frequency division operation equivalent to a single p] variable frequency divider.
以上のように第1図の十輛成に、VCO及びループフィ
ルタ以外の回路か全てティジタル回路で(・Nr 成で
きるのでIC化に適しており、調整置所も少いのでシン
セサイザの小形化・商伯幀度化f’(−J+している。As mentioned above, all circuits other than the VCO and loop filter can be constructed using digital circuits (Nr) in the ten configurations shown in Fig. 1, making it suitable for IC implementation. Commercialization f' (-J+).
ととろが、この構成ではb1亥分周1Xii ] 3に
おけるKb合分周数Nか数万程1徒と大きい/ζめ 1
)LLループのループゲインか低くなる1、一方、1〕
L Lループのフーc、l谷時間はルーズケインに反比
例するので、とのi構成では周波数切替時や電源投入1
1Hj。However, in this configuration, the Kb combined frequency division number N in 3 is as large as 1/ζ 1
) The loop gain of the LL loop is 1, on the other hand, 1]
Since the loop c and l trough times of the L loop are inversely proportional to the loose-cain, in the i configuration, when switching the frequency or turning on the power
1Hj.
のシンセサイザの応答時間かとうしてもIk<なって1
.廿うという問Y4すかあった9゜この問題を角子決す
る方法として、i1]置分周器13aを用いる替りにミ
ギザを用い、/ンセヅイザ出力を数へ/i H7,程度
に周θ支故変換することによって総合分周比Nを小さく
する方法(ミックスタウン方式P L T、、 IJ波
>タンンセザイザ)か考えられる1、即ち第2図Jlr
C第1図と対1芯するi′、ls分に同一71号をイχ
1けて示すように、シンセサイザ出力はミキサ19で局
発信号逓倍部21の出力で低い周波数に変換されて主分
周器(プログラマブルカウンタ)13bへ供給される。The response time of the synthesizer is Ik<1.
.. The question Y4 is 9゜As a way to solve this problem, instead of using the i1] frequency divider 13a, use a migrater and convert the output of the frequency divider to a number /i H7, by converting the frequency θ to the degree One possible method is to reduce the overall frequency division ratio N by
Insert the same No. 71 for i′, ls, which is one core as in Fig. 1.
As shown in Figure 1, the synthesizer output is converted to a lower frequency by the mixer 19 using the output of the local oscillator signal multiplier 21, and is supplied to the main frequency divider (programmable counter) 13b.
この方法によれば前置分周器を省]烙できるので、シン
セサイザ出力から位相比較器15の入力捷での分周数は
主分周器13bの分局数Mに一致し、第1図に示したも
のと比べて分局数を大幅に小さくしてループゲインを上
けることができる。According to this method, the pre-frequency divider can be omitted, so that the frequency division number at the input of the phase comparator 15 from the synthesizer output matches the division number M of the main frequency divider 13b, and as shown in FIG. The loop gain can be increased by significantly reducing the number of branched stations compared to what is shown.
一方、このミックスダウン方式ではミキサ19V(刀n
える局発信号として、極めて高安定かつ高純磨の信号が
必要になる。このだめ、この構成では基準発振器16の
出力を局発信号逓倍部21により逓倍してミキサ用の局
発信号、を得でいる。ところが、基”A 発、+11=
*器16の発振周波数は通常数TVI )Iz〜10
MH7,程度に選1ばれるから、ミキサ19の局発周波
数としてシンセザイザ出力とはソ同じVHF帯〜i G
117.4”−=度を得るためには局発信号逓倍部2
1における逓倍数が数十〜百程度必要となる。On the other hand, in this mixdown method, the mixer 19V
As a local oscillator signal, an extremely stable and highly polished signal is required. However, in this configuration, the output of the reference oscillator 16 is multiplied by the local oscillator signal multiplier 21 to obtain the local oscillator signal for the mixer. However, from base “A, +11=
*The oscillation frequency of the device 16 is usually a number TVI) Iz~10
Since the local oscillation frequency of the mixer 19 is selected to be approximately MH7, the VHF band ~ i G is the same as the synthesizer output.
In order to obtain 117.4”-=degree, the local signal multiplier 2
A multiplication number of about 1 to about 100 is required.
したがって局発信号逓倍部21では図示するように逓倍
回路21a、21b、21cを多段縦属接続し、しかも
各段の出力側にスプリアス除去のだめの帯域通過フィル
タ21d 、21 e 、21fをそれぞれ挿入する心
安がある。こ9ため局発信号逓倍部21の回路規模が極
めて犬さくなる。さらに局発信号逓倍部21に含捷れる
回路はコイル等を多数使用するので潤幣が必要であり、
IC化か困e’aである。したがってシンセサイザの小
形化・肩信頼度化の妨り”になるという問題が生ずる。Therefore, in the local oscillator signal multiplier 21, multiplier circuits 21a, 21b, and 21c are connected in series in multiple stages as shown in the figure, and band-pass filters 21d, 21e, and 21f for spurious removal are inserted on the output side of each stage, respectively. I feel safe. Therefore, the circuit scale of the local oscillator signal multiplier 21 becomes extremely small. Furthermore, the circuit included in the local oscillator signal multiplier 21 uses many coils, etc., so it requires a lot of money.
It is difficult to convert to IC. Therefore, a problem arises in that it becomes a hindrance to making the synthesizer more compact and more reliable.
〈発明の概要〉
この発明はこれらの欠点を除去するため、■CO出力を
前置分周器で分周した後でミキサにより低い周波数に周
波数変換を行って総合分周数を小さくシ、周波数応答時
間を知かくすると共に、基準発振器からの出力をその件
寸ミギザの局発信号として用いることによって回路B1
1漠の増大を抑え、IC化に適した格造としたものであ
る。<Summary of the Invention> In order to eliminate these drawbacks, the present invention: ■ divides the CO output using a prescaler and then converts the frequency to a lower frequency using a mixer to reduce the total frequency division number and reduce the frequency. By increasing the response time and using the output from the reference oscillator as a local oscillator signal, the circuit B1
This structure suppresses the increase in noise and makes it suitable for use with ICs.
〈実施例〉
第3図(dこの発明の実施例を示し、第1図と対応する
部分には同一符号を示しである1、この発明では可変分
周部22は前置分周器22aと、その出力を周波数変換
するミキサ22bと、ミキサ22bの出力を周波数分周
する主分周器2.2.cと、前置分周器22aを制御す
る前置分周器制往1用カウンタ22dとから構成する。<Embodiment> FIG. 3 (d) shows an embodiment of this invention, and parts corresponding to those in FIG. , a mixer 22b that frequency converts the output thereof, a main frequency divider 2.2.c that frequency divides the output of the mixer 22b, and a prescaler limit 1 counter that controls the prescaler 22a. 22d.
主分周器22Cにはプログラマブル分周器(分周数M’
)が用いられ、さらに前置分周器22a1前置分周器制
御用カウノタ22dの動作(はそれぞれ第1 [2+に
おける前16゛分周器13a1前置分周器制御用カウン
タ13Cの動作と全く同じものとする。捷だ基準発振器
1Gの発振周波数は無線周波数間隔fchのに倍とし、
数M H7,程度に1ソリぷものとする。The main frequency divider 22C is a programmable frequency divider (dividing number M'
) is used, and the operation of the prescaler control counter 22d of the prescaler 22a1 (is the operation of the prescaler control counter 13C of the prescaler 16' divider 13a1 at the first [2+), respectively. The oscillation frequency of the standard oscillator 1G is twice the radio frequency interval fch,
It is assumed that there is one solip every several MH7.
この構成におい一’CVCOIIの出力はシンセザイザ
出力として出力端1子12へ出力されると同nypに、
可変分周部22内において、捷ず前置分周器22aによ
ってaM H2程度に寸で分周され、その分周山力樗:
次に基準発振器16の出力を局クラ信号とするミキサ2
21)により周波数変換されて数百K +−1Z程度の
低い周波数の信号とされる。この信号d、さらに主分周
器22Cにより+VL’分周された後、位相比較器15
の第1の入力伶子へ加えられる7、位相比較器15の第
20入力端子には乱準発振器16の出力を分周器17で
に分周して得た基準信号(周波数=fch)が加えられ
ており、位相比較器15は2つの入力信号を位相比較し
て誤差伯弓として出力する。この誤差信号を8四に尼し
てループフィルタ18を介してVCO]、1にフィード
バックする。この結果、出力端子12に無線局θに数間
隔fchのL倍の周波数を持った(i号がイ4fられる
。こSで、周波数設定端子14から入力されたコード番
号に」:って十分b1器22c及び副側1用ツノウンタ
22dの各分周数M1及びAが変化するとこれに従って
分周数りも変わるので、このA・伶h′vにtつて周波
数シンセサイザを41,1成することかできる4、この
構成により第1図に示した場合よりも流台分周数を以下
に述べる」:うに著しく小はくすることができる。In this configuration, when the output of 1'CVCOII is output to the output terminal 12 as a synthesizer output,
In the variable frequency dividing section 22, the frequency is divided into approximately aM H2 by the pre-frequency divider 22a, and the frequency of the frequency division is as follows:
Next, a mixer 2 which uses the output of the reference oscillator 16 as a local signal
21), the signal is frequency-converted into a signal with a low frequency of about several hundred K+-1Z. After this signal d is further divided by +VL' by the main frequency divider 22C, the phase comparator 15
A reference signal (frequency = fch) obtained by dividing the output of the random oscillator 16 by a frequency divider 17 is applied to the 20th input terminal of the phase comparator 15. The phase comparator 15 compares the phases of the two input signals and outputs the result as an error signal. This error signal is fed back to the VCO 1 through the loop filter 18. As a result, at the output terminal 12, the wireless station θ has a frequency L times the frequency fch at several intervals (i is added to the code number inputted from the frequency setting terminal 14). When the frequency division numbers M1 and A of the b1 unit 22c and the secondary side 1 counter 22d change, the frequency division numbers also change accordingly, so a frequency synthesizer is constructed by adding t to this A and h'v. With this configuration, the sink frequency division number can be made significantly smaller than in the case shown in FIG.
捷ずシンセサイザ出力周波数f3yNと無線周波数fc
hとの比りは第1図の場合七同イか(て考えて式(2)
の」二うに表せる。Synthesizer output frequency f3yN and radio frequency fc
Is the comparison with h equal to 7 in the case of Figure 1?
It can be expressed in two ways.
L=A・(P+1 )+(M’+f(−A)・P=(M
’+K)P十A(2)
第1図の場合と同一の出力周波数fsYNを得るだめに
はT、 = Nとすれはよい。このとき式(1)と式(
2)とから、
M’+に=M (3)
の[p1係があることがわかる。一方、第3図中の可変
分周部22における総合分周数N1は、はソ分周器22
a、22Cの分周数の積で表わせ、N’菅M1・P=(
M−K)・P(4)となる。式(4)を式(1)と比べ
ると、好キサ22 ’I)を用いて周波数変換した分だ
け分周数が小さくて済むことがわかる。−例として、f
c h=25 K t(z 。L=A・(P+1)+(M'+f(-A)・P=(M
'+K)P0A(2) In order to obtain the same output frequency fsYN as in the case of FIG. 1, it is better to set T, = N. At this time, equation (1) and equation (
From 2), it can be seen that M'+ has a [p1 coefficient of =M (3). On the other hand, the total frequency division number N1 in the variable frequency divider 22 in FIG.
It is expressed as the product of the frequency division number of a and 22C, and N'M1・P=(
M-K)・P(4). Comparing Equation (4) with Equation (1), it can be seen that the frequency division number can be reduced by the amount of frequency conversion performed using the good frequency converter 22'I). - As an example, f
c h=25 K t(z .
f SYN” 800 MHz、 Pニ128とすると
第1図の構成ではM−250、l’J=32000とな
るが、第3図の構成でに=240(発揚器1Gの発振周
波数=6MH7,)とするとM’=10、N’=128
Ofあり、N1はNの1./200以下にできる。P
L Lループのループゲインは分周数N及びN′の逆数
に比[タリするから、この実施例ではループケインを2
00倍以上大きくすることができる。したがって周波数
応答が改善され、周波数切替時間等を著しく短かくする
ことが可能である。f SYN" 800 MHz, P2128, in the configuration shown in Figure 1, M-250, l'J = 32000, but in the configuration shown in Figure 3, it becomes 240 (oscillation frequency of oscillator 1G = 6MH7,) Then M'=10, N'=128
Of, N1 is N's 1. /200 or less. P
The loop gain of the L L loop is proportional to the reciprocal of the dividing number N and N', so in this example, the loop gain is set to 2.
It can be made larger by 00 times or more. Therefore, frequency response is improved, and frequency switching time etc. can be significantly shortened.
このように第3図の実施例は第1図に示した従来のもの
にミキサ22bを追加するだけで実mでき、第2図に示
したもののように抜朶(な逓倍回路や帯域通過フィルタ
を必要とせずに周波数切替時間等を大幅に短縮すること
ができる。さらに追加するミキサ22bは数M j(z
8度の低周波で動作すればよいので実現は極めて容易
である。ミキサ22bの構成例を第4図に示す。ミキサ
入力端子23.24に前置分周器22aの出力に基準発
振器1Gの出力をそれぞれ入力し、これら内入力を排他
的論理和回路25へ供給し、その出力を低域通過フィル
タに;ijiせばI門波数変換出力がミキサ出力端子2
7に得られ、この出力を主分周器22cへ供給する。ミ
キサ22bはこのように簡単に構成できるため実施に伴
う部品点数の増加は少なく、調整箇所も皆諷である。捷
た、第4図に示したミキサ22F)は主分周器22c及
び前置分周器副側1用カウンタ22dと共に容易にLS
I化でき、シンセサイザの小形化・高信頼度化に対して
も非常に有利である。In this way, the embodiment of FIG. 3 can be realized by simply adding the mixer 22b to the conventional one shown in FIG. It is possible to significantly shorten the frequency switching time etc. without requiring the additional mixer 22b.
It is extremely easy to realize this because it only needs to operate at a low frequency of 8 degrees. An example of the configuration of the mixer 22b is shown in FIG. The output of the reference oscillator 1G is input to the mixer input terminals 23 and 24 as the output of the pre-frequency divider 22a, and these inputs are supplied to the exclusive OR circuit 25, and the output is passed to the low-pass filter; If so, the I gate wave number conversion output is mixer output terminal 2.
7 and supplies this output to the main frequency divider 22c. Since the mixer 22b can be constructed easily in this way, the number of parts increases little due to implementation, and the adjustment points are all the same. The mixer 22F) shown in FIG.
It can be integrated into an integrated circuit, which is very advantageous for making synthesizers more compact and highly reliable.
前置分周器22aの分周数はP 、P+1に1浪らず、
一般にPとQ(Pと異なる数)七にすることができれば
よ<、P、Qは共に2以上の整数であり、この場合式(
2)tj: (P + 1 )の代りにQを用いる。i
4i::併用カウンタ22aのAi:LJ、Qの何れよ
りも小さい0又は正整数であり、主分周器22Cの分周
pW(’は2以上の整数である。The frequency division number of the prescaler 22a is P, not less than 1 in P+1,
In general, if P and Q (numbers different from P) can be made to be seven, P and Q are both integers greater than or equal to 2, and in this case, the formula (
2) tj: Use Q instead of (P + 1). i
4i:: Ai of the combination counter 22a: 0 or a positive integer smaller than either LJ or Q, and the frequency division pW of the main frequency divider 22C (' is an integer of 2 or more.
〈効 果〉
以上説明したようにこの発明によれば小形化・IC化・
無調整化が容易な構成をとりながら、周波数i刃替時や
電源投入時の応答時間が極めて短かい周波数シンセサイ
ザを実現することができる。。<Effects> As explained above, according to this invention, miniaturization, ICization,
It is possible to realize a frequency synthesizer that has an extremely short response time when changing the frequency i blade or when turning on the power, while having a configuration that allows easy adjustment. .
したがって今後益々発展が期待される各純移動通伯方式
(自11ij車′市話、コードレス電話、パーソナル無
線等)に適用すると、
■、空チーヤネル探策に費する時間が知縮されるので、
より頻累に空チャネル探策を行なうことが可能となる、
しだがって無線チャイルをより有効に使用することかで
き、システムの加入者容量の噌犬に寄与することかでき
る。Therefore, if it is applied to various pure mobile communication methods (mobile 11IJ car, city phone, cordless telephone, personal radio, etc.) which are expected to develop more and more in the future, the time spent searching for air channels will be reduced.
It becomes possible to conduct sky channel exploration more frequently,
Therefore, the wireless cell can be used more efficiently and can contribute to the subscriber capacity of the system.
■、間欠愛惜を行々う無腺板において、%に投入時のノ
ンセサイザ立上り時間が早くなるので、より短い時間で
受信信号の検出ができるようになる、したがって単位時
間あ/こりの間欠受化回数孕同しとすれば、電4ネをオ
ンしている時間を小さくすることができ、無線様の消費
電力の低減に大きく寄与することができる。■In a non-glandular board that performs intermittent reception, since the rise time of the non-synthesizer becomes faster when it is turned on, it becomes possible to detect the received signal in a shorter time, and therefore the intermittent reception of unit time. If the number of pregnancies is reduced, the time during which the lights are turned on can be reduced, which can greatly contribute to reducing the power consumption of wireless devices.
等の効果があり、各方式の高性能化の」二で犬さな効果
がある。This has the effect of increasing the performance of each method.
第1図1は従来のパルススワロ方式周波数シンセサイザ
の構成を示すブロック図、第2図&J従来のミックスダ
ウン方式周波数ン/セザイザの構成を示すブロック図、
第3図シIニとの発明の実施例を7丁<すブロック図、
第4図は第3図中のミキサ2.2 bの構成例を示すN
略図である。
11:電圧制御発振器、12:出力111^i子、14
:周波数設定端子、15:位相比軸器、16:基準発振
器、17:固定分周器、18:ループフィルタ、22:
司変分周部、22a:前辺分周器、22b:ミキサ、2
2C:十分筒器、22d:前置分周器制御用カウンタ。
特許出願人 日本電信電話公社
代理人 草野 卓
オ 1 図
オ 2図
第3 図
文′4 図FIG. 1 is a block diagram showing the configuration of a conventional pulse swirl frequency synthesizer, and FIG. 2 is a block diagram showing the configuration of a conventional mixdown frequency synthesizer.
FIG. 3 is a block diagram showing seven embodiments of the invention;
Figure 4 shows an example of the configuration of mixer 2.2b in Figure 3.
This is a schematic diagram. 11: Voltage controlled oscillator, 12: Output 111^i child, 14
: Frequency setting terminal, 15: Phase ratio axis unit, 16: Reference oscillator, 17: Fixed frequency divider, 18: Loop filter, 22:
22a: front side frequency divider, 22b: mixer, 2
2C: Sufficient cylinder, 22d: Prescaler control counter. Patent applicant Takuo Kusano, agent for Nippon Telegraph and Telephone Public Corporation 1 Figure 2 Figure 3 Figure '4 Figure
Claims (1)
御発振器と、その電圧制御発振器の出力信号をその設定
された周波数に応じた整数比で分周して出力する可変分
周部と、その可変分局部からの分周出力信号とノロ・準
となる信号とを位相比較する位相比較器と、その位相比
較器の出力により上記′…;圧抽御発据器を制御する手
段とを廟する周波数シンセサイザにおいて、上記可変分
周部d2つの分周ap(2以上の整数)及びQ(Pと界
斤る2以」−の整数)が選1Rできる前置分周器とその
前1+#分周器の出力をこれよりも低い周波数に1M波
数性換するミキサと1そのミキサからの出力を設定され
た周波数に応じたM(2以上の整数)分周する主分周器
と、上記前置分周器の出力を設定された周波数に応じだ
A(P、Qよりも小さいO又は正整数)サイクルだけ計
数するとその前置分周器の分周数を上記Pに設定し、か
つ上記主分周器から分周パルスが出力される毎に上記前
置分周器の分周数をl He Qに設定する前置分周器
制御用カウンタとで構成されることを特徴とする周波数
シンセサイザ。(1) A voltage controlled oscillator whose oscillation frequency can be controlled from outside ↑-11, a variable frequency divider which divides and outputs the output signal of the voltage controlled oscillator by an integer ratio according to the set frequency, and its A phase comparator that compares the phase of the frequency-divided output signal from the variable dividing section and the normal/quasi signal, and a means for controlling the pressure extraction generator and installation device based on the output of the phase comparator. In the frequency synthesizer, the variable frequency dividing section d has a pre-frequency divider in which two frequency division ap (an integer of 2 or more) and Q (an integer of 2 or more that is equal to or greater than P) can be selected 1R, and a pre-divider in front of it 1+#. 1. A mixer that converts the output of the frequency divider into a 1M wave number lower frequency; 1. A main frequency divider that divides the output from the mixer by M (an integer of 2 or more) according to a set frequency; When the output of the prescaler is counted according to the set frequency A (O or a positive integer smaller than P and Q) cycles, the division number of the prescaler is set to the above P, and and a prescaler control counter that sets the frequency division number of the prescaler to l He Q every time a frequency division pulse is output from the main frequency divider. frequency synthesizer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58238598A JPS60130218A (en) | 1983-12-16 | 1983-12-16 | Frequency synthesizer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58238598A JPS60130218A (en) | 1983-12-16 | 1983-12-16 | Frequency synthesizer |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS60130218A true JPS60130218A (en) | 1985-07-11 |
JPH0559614B2 JPH0559614B2 (en) | 1993-08-31 |
Family
ID=17032569
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58238598A Granted JPS60130218A (en) | 1983-12-16 | 1983-12-16 | Frequency synthesizer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60130218A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63114421A (en) * | 1986-10-31 | 1988-05-19 | Yaesu Musen Co Ltd | Pll circuit |
JP2005057754A (en) * | 2003-07-31 | 2005-03-03 | Agilent Technol Inc | Direct frequency synthesizer for offset loop synthesizer |
-
1983
- 1983-12-16 JP JP58238598A patent/JPS60130218A/en active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63114421A (en) * | 1986-10-31 | 1988-05-19 | Yaesu Musen Co Ltd | Pll circuit |
JP2005057754A (en) * | 2003-07-31 | 2005-03-03 | Agilent Technol Inc | Direct frequency synthesizer for offset loop synthesizer |
Also Published As
Publication number | Publication date |
---|---|
JPH0559614B2 (en) | 1993-08-31 |
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