JPS60111433A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60111433A JPS60111433A JP58219808A JP21980883A JPS60111433A JP S60111433 A JPS60111433 A JP S60111433A JP 58219808 A JP58219808 A JP 58219808A JP 21980883 A JP21980883 A JP 21980883A JP S60111433 A JPS60111433 A JP S60111433A
- Authority
- JP
- Japan
- Prior art keywords
- film
- lead
- metal protrusion
- region
- film lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/79—Apparatus for Tape Automated Bonding [TAB]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
２ページ
産業上の利用分野
本発明は半導体素子等の高密度、薄型、小型の実装にお
ける転写バンプ方式による半導体装置の製造方法に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION Page 2 Field of Industrial Application The present invention relates to a method of manufacturing a semiconductor device using a transfer bump method for packaging semiconductor elements and the like in high density, thin and compact packaging.
従来例の構成とその問題点
近年、ＩＣ，ＬＳＩ等の半導体素子は各種の家庭電化製
品、産業用機器の分野へ導入されている。2. Description of the Related Art Structures of Conventional Examples and Their Problems In recent years, semiconductor elements such as ICs and LSIs have been introduced into the fields of various home appliances and industrial equipment.
これら家庭電化製品、産業用機器は、省資源化、省電力
化のためにあるいは利用範囲を拡大させるために、多機
能化、小型化、薄型化のいわゆるポータプル化が保進さ
れてきている。In order to conserve resources and power, or to expand the scope of use, these household electrical appliances and industrial devices are becoming more multifunctional, smaller, and thinner, so-called portable devices.
半導体素子においてもポータプル化に対応するために、
パッケージングの小型化が要求されてきている。拡散工
程、電極配線工程の終了したシリコンスライスは半導体
素子単位のチップに切断され、チップの周辺に設けらｎ
たアルミ電極端子から外部端子へ電極リードを取出して
取扱いやすくしまた機械的保護のためにパッケージング
される。In order to respond to the portupling of semiconductor devices,
There is a growing demand for smaller packaging. After the diffusion process and electrode wiring process have been completed, the silicon slice is cut into chips each containing a semiconductor element.
Electrode leads are taken out from the aluminum electrode terminals to external terminals for easy handling and are packaged for mechanical protection.
通常、これら半導体素子のパッケージングには、ＯＩＬ
、チップキャリヤ、フリップチップ、フィ３べ、。Usually, OIL is used for packaging these semiconductor devices.
, chip carrier, flip chip, fi 3be,.
ルムキャリャ方式等が用いられているが、前記した目的
のためには、フィルムキャリヤ方式が有望である。Lum carrier systems and the like have been used, but film carrier systems are promising for the purpose described above.
半導体素子の電極端子にフィルムキャリヤのり−ド端素
を接合する手段のひとつとして転写バンプ方式（特開昭
５６−１５２１４７号）が提案さｎている。この転写バ
ンプ方式は、絶縁性基板上の半導体素子の電極と対応し
た位置にＡｕの金属突起（バンプ）を形成しておき、捷
ず、前記金属突起とフィルムキャリヤのＳｎメッキした
リード端子とを位置合せし、ツールで加圧、加熱し、前
記リード端子に前記絶縁性基板上の金属突起ｉＡｕ・Ｓ
ｎ合金で接合し、絶縁性基板上から前記金属突起を剥離
せしめ、リード端子に転写させる。次いで、半導体素子
（アルミ）と前記リード端子の金属突起と全位置合せし
、ツールで加圧、加熱せしめ、Ａｕ−ＡＪ４合金で前記
金属突起と半導体素子の電極端子とを接合するものであ
る。A transfer bump method (Japanese Unexamined Patent Publication No. 152147/1983) has been proposed as one means for bonding film carrier glue end elements to electrode terminals of semiconductor elements. In this transfer bump method, Au metal protrusions (bumps) are formed on an insulating substrate at positions corresponding to the electrodes of the semiconductor element, and the metal protrusions and the Sn-plated lead terminals of the film carrier are connected without being separated. Align, pressurize and heat with a tool, and attach the metal protrusion iAu・S on the insulating substrate to the lead terminal.
After bonding with n alloy, the metal protrusions are peeled off from the insulating substrate and transferred to lead terminals. Next, the semiconductor element (aluminum) and the metal protrusions of the lead terminals are fully aligned, and the metal protrusions and the electrode terminals of the semiconductor element are bonded using an Au-AJ4 alloy by applying pressure and heat using a tool.
従来、前記転写バング方式のフィルムキャリヤのリード
に第１図に示す構成であった。すなわち・長尺の樹脂フ
ィルム１には半導体素子２と樹脂フィルム１から延在し
たリード端子３とを接合するために開孔部４が形成さ扛
ている。樹脂フィルム１から延在したリード端子３は、
開孔部４の領域において、同一のｒｌ］’を有するもの
であった（第１図ａ）。この場合、リード端子３に基板
上に形成した金属突起を位置合せし転写する際に、前記
リード端子３に金属突起との位置合せ時の所定位置を示
すキーがないために、延在したリード端子３のどの領域
に金属突起を転写、接合すべきかが不明確となる。Conventionally, the lead of the transfer bang type film carrier has the structure shown in FIG. That is, openings 4 are formed in the long resin film 1 for joining the semiconductor element 2 and the lead terminals 3 extending from the resin film 1. The lead terminal 3 extending from the resin film 1 is
In the area of the aperture 4, they had the same rl]' (FIG. 1a). In this case, when aligning and transferring the metal protrusion formed on the substrate to the lead terminal 3, the extended lead is It becomes unclear to which region of the terminal 3 the metal protrusion should be transferred and bonded.
また、リード端子３の巾が金属突起５の巾よりも太きい
と、半導体素子２の電極６とリード端子３に転写した金
属突起５とを位置合せする際に、第１図Φ）の如く、金
属突起５がリード端子３にかくｎてし捷うために、位置
合せが著じるしく困難どなり位置合せずれによる接合強
度の低下ｉｔねくものである。また、仮に第１図（Ｃ）
のごとく、リード端子３の巾が金属突起５の巾よりも小
さいと、リード端子３の延在方向と直角方向の位置合せ
は、５べ一＝ン
前記金属突起５がリード端子３からはみだすので割合容
易ではあるが、延在方向の位置合せは困難となり、樹脂
フィルム１と半導体素子２との別離が上下、左右方向で
たとえばａとａ２で異なってし捷う。したがって、樹脂
フィルム１に機械的応力・熱的応力が作用した場合にリ
ード端子３の長さが異なるために、リード端子３が受け
る応力も、上下、左右方向で不均等になり、リード端子
の破断をまねくことがあった。また、距離への相異は、
金属突起半導体素子の電極との接合時にリード端子から
の熱の逃げが不均等であるからのボンディングツールの
温度分布に不均性をもたらし、こｎも捷た接合強度の低
下をもたらすものであった。Furthermore, if the width of the lead terminal 3 is wider than the width of the metal protrusion 5, when aligning the electrode 6 of the semiconductor element 2 and the metal protrusion 5 transferred to the lead terminal 3, it will be difficult to align the electrode 6 of the semiconductor element 2 and the metal protrusion 5 transferred to the lead terminal 3, as shown in Fig. 1 Φ). Since the metal protrusion 5 bends over the lead terminal 3, alignment is extremely difficult and the bonding strength is inevitably reduced due to misalignment. Also, suppose that Figure 1 (C)
As shown in the figure, if the width of the lead terminal 3 is smaller than the width of the metal protrusion 5, the alignment in the direction perpendicular to the extending direction of the lead terminal 3 will be 5 points, since the metal protrusion 5 protrudes from the lead terminal 3. Although relatively easy, alignment in the extending direction becomes difficult, and the resin film 1 and the semiconductor element 2 are separated differently in the vertical and horizontal directions, for example, a and a2. Therefore, when mechanical stress/thermal stress is applied to the resin film 1, since the length of the lead terminal 3 is different, the stress applied to the lead terminal 3 is also uneven in the vertical and horizontal directions, and the stress on the lead terminal 3 is uneven. This could lead to breakage. Also, the difference in distance is
When a metal protrusion semiconductor element is bonded to an electrode, heat escapes unevenly from the lead terminal, resulting in uneven temperature distribution of the bonding tool, which also causes a decrease in bonding strength. Ta.
こｎは第１図（ｂ）の構成でも同様に生じる。This problem similarly occurs in the configuration shown in FIG. 1(b).
発明の目的
本発明はこのような従来の問題に鑑み、位置合せが著じ
るしく容易で、接合強度の高い転写バンプ方式を行うこ
とのできる方法を提供することを目的とする。OBJECTS OF THE INVENTION In view of the above-mentioned conventional problems, it is an object of the present invention to provide a method that can perform a transfer bump method in which positioning is extremely easy and bonding strength is high.
発明の構成
６ページ
本発明は、金属突起を転写・接合するフィルムリードの
巾が、前記金属突起を転写する領域でかつ半導体素子の
電極に相対応した領域の巾を、他の領域よりも巾広い構
造を有し、これにより転写バンプ方式により半導体素子
を実装する際、位置合せが容易でかつ、接合強度および
信頼度の高い実装を可能とするものである。Structure of the Invention Page 6 The present invention provides that the width of the film lead for transferring and bonding the metal protrusions is such that the width of the area where the metal protrusions are transferred and the area corresponding to the electrode of the semiconductor element is wider than other areas. It has a wide structure, which allows easy alignment and high bonding strength and reliability when mounting semiconductor elements using the transfer bump method.
実施例の説明
第２図は本発明の第１の実施例におけるフィルムリード
の構造を示したものである。樹脂フィルム１から延在し
たフィルムリード２０は、その先端領域２１においてそ
の他の部分よりも巾広い寸法を有している。すなわち前
記フィルムリード２０の先端領域２１は、転写用の金属
突起が転写・接合さ肛かつ半導体素子の電極と相対応し
た位置の領域であって、樹脂フィルム１から延在したフ
ィルムリード２０の１ＪＢよりも、先端領域２１の巾Ｃ
が大きい構造である。また、フィルムリード２０の巾Ｃ
およびＤは、半導体素子の電極の寸法と同一かもしくは
小さく構成さｎている。DESCRIPTION OF EMBODIMENTS FIG. 2 shows the structure of a film lead in a first embodiment of the present invention. The film lead 20 extending from the resin film 1 has a tip region 21 wider than the other portion. That is, the tip region 21 of the film lead 20 is a region where the metal protrusion for transfer is transferred and bonded and is located in a position corresponding to the electrode of the semiconductor element, and is a region corresponding to the 1JB of the film lead 20 extending from the resin film 1. , the width C of the tip region 21
It is a large structure. Also, the width C of the film lead 20
and D are configured to be the same or smaller than the dimensions of the electrodes of the semiconductor element.
７ 、・
次に第３図をもちいて、本発明にががる方法を詳細に説
明する。絶縁性上基板２２を主体とする表面にメッキ法
等で形成された金属突起２３とフィルムリード２０とを
位置合せする場合、通常、フィルムリード２０の矢印４
０方向から顕微鏡等で観察しながら位置合せする。この
時、フィルムＩＪ−ト”２０の先端領域２１は第２図で
説明した如く［１］広くなっているから、金属突起２３
が、フィルムリード２０のＣ，Ｄで囲まれた領域２１内
に入る様に、すなわち、Ｃ，Ｄで四重れた領域２１内に
金属突起２３がかくれる様に位置合せす几ば良い。この
様に位置合せの領域が各フィルムリード毎に指定さ几て
いるので著しるしく位置合せが容易となるものである。7. Next, the method according to the present invention will be explained in detail using FIG. When aligning the film lead 20 with the metal protrusion 23 formed by plating or the like on the surface mainly composed of the insulating substrate 22, the arrow 4 of the film lead 20 is usually aligned.
Align while observing with a microscope etc. from the 0 direction. At this time, since the tip region 21 of the film IJ-t" 20 is wide [1] as explained in FIG. 2, the metal protrusion 23
However, the metal protrusion 23 should be positioned so that it is within the area 21 surrounded by C and D of the film lead 20, that is, so that the metal protrusion 23 is hidden within the area 21 overlapped by C and D. Since the alignment area is designated for each film lead in this way, alignment becomes considerably easier.
この様にしてフィルムリード２０のＣ，Ｄで囲まｎた領
域２１に金属突起２３を転写・接合（第３図ａ）し、次
いで半導体素子２の電極６に位置合せして接合する。半
導体素子２のアルミ電極６と、フィルムリード２０の金
属突起２３とを位置合せするわけであるが、この場合、
アルミ電極６と金属突起２３とを位置合せするのではな
く、前記フィルムリード２ｏの先端のＣ，Ｄで囲まれた
領域２１と、アルミ電極６とを位置合せすればよい（第
３図ｂ）。In this way, the metal protrusion 23 is transferred and bonded to the area 21 surrounded by C and D of the film lead 20 (FIG. 3a), and then aligned and bonded to the electrode 6 of the semiconductor element 2. The aluminum electrode 6 of the semiconductor element 2 and the metal protrusion 23 of the film lead 20 are aligned, but in this case,
Instead of aligning the aluminum electrode 6 and the metal protrusion 23, it is sufficient to align the area 21 surrounded by C and D at the tip of the film lead 2o with the aluminum electrode 6 (FIG. 3b). .
本発明では、フィルムリード２０の先端部のＣＤで囲ま
ｎた金属突起を転写・接合する領域は、半導体素子２の
アルミ電極らよりも小さめの寸法であるから一第３図す
の矢印４１方向から位置合せした場合、アルミ電極６の
方がＣ，Ｄの領域２１よりも太きいから、容易に位置合
せができる。In the present invention, the area surrounded by the CD at the tip of the film lead 20 where the metal protrusions are transferred and bonded has a smaller size than the aluminum electrodes of the semiconductor element 2. When the aluminum electrode 6 is thicker than the C and D regions 21, the alignment can be easily performed.
また、位置合せも単に半導体素子２のアルミ電極６にフ
ィルムリード２０の先端Ｃ，Ｄの領域２１の指定された
領域を重ね合せるだけで良い。この状態で金属套起２３
は、確実にアルミ電極６領域内に存在し、確実な位置合
せが実施され、接合される（第３図Ｃ）。Furthermore, positioning can be accomplished simply by overlapping specified regions 21 of the tips C and D of the film lead 20 on the aluminum electrode 6 of the semiconductor element 2. In this state, the metal mantle 23
is reliably present within the area of the aluminum electrode 6, and reliable alignment is performed and bonding is performed (FIG. 3C).
第４図は、フィルムリードの第２の実施例である。第４
図ａは樹脂フィルムから延在したフィルムリード２０の
巾広の領域２１に突起２σを形成したものであ□って、
位置合せの際のフィルムリードの先端領域２１の中心位
置を判別しやすい様に９ 、−
形成したものである。捷だ、第４図すは、フィルムリー
ド２ｏの先端領域を円形３１に形成したもので、半導体
素子の電極の四角の領域と位置合せする際、著しるしく
容易になるものである。このように、本発明においては
、この種にフィルムリードの先端部の形状にこだわるも
のではなく、延在した領域の巾よりも、巾広く構成さｎ
ることが特徴である。FIG. 4 shows a second embodiment of the film lead. Fourth
Figure a shows a film lead 20 extending from a resin film in which a protrusion 2σ is formed in a wide region 21.
9.- is formed so that the center position of the tip region 21 of the film lead can be easily determined during alignment. As shown in FIG. 4, the tip region of the film lead 2o is formed into a circular shape 31, which greatly facilitates alignment with the square region of the electrode of the semiconductor element. As described above, in the present invention, the shape of the tip of the film lead is not particularly concerned, and the width is wider than the width of the extended region.
It is characterized by
次に第５図をもちいて、本発旧の全体の工程の実施例を
説明する。Next, an embodiment of the entire process of the present invention will be described using FIG.
樹脂フィルム１から延在したフィルムリード２０はＣｕ
箔をエツチング処理し、ビーム状に形成され、かつＳｎ
メッキを０．４μｍの浮さに有するものである。一方、
金属突起２３を形成するための基板２２は、ガラス、セ
ラミック等の絶縁性基板上ＫＰｔ、Ｐｄ、ｉＴｏ等の金
属膜または導電性の金楓酸化膜が形成され、この上にさ
らに、半導体素子の電極に相対応する領域のみを開孔し
たメッキ用マスクパターンを有するＳｔ、２．５ｔ３Ｎ
４．ポリイミド膜等の絶縁膜が形成されており、開孔部
に１０、、−ラ・
金属突起２３が電解メッキ法で形成される〔第５図ａ〕
。The film lead 20 extending from the resin film 1 is made of Cu.
The foil is etched and formed into a beam shape, and Sn
The plating has a height of 0.4 μm. on the other hand,
The substrate 22 for forming the metal protrusions 23 is formed by forming a metal film such as KPt, Pd, iTo, etc. or a conductive gold maple oxide film on an insulating substrate such as glass or ceramic, and further forming a semiconductor element thereon. St, 2.5t3N having a plating mask pattern with holes only in areas corresponding to the electrodes.
4. An insulating film such as a polyimide film is formed, and metal projections 23 are formed in the openings by electrolytic plating (Figure 5a).
.
次に、フィルムリード２ｏの巾広の領域と金属突起２３
とを位置合せし、ボンディングツール３２で加熱加圧せ
しめ、フィルムリードの先端部の巾広の領域に、金属突
起２３ｉＡ＊・Ｓｎの合金で転写・接合し、基板２２よ
り、金属突起２３を剥離するものである（第５図ｂ）。Next, the wide area of the film lead 2o and the metal protrusion 23
The metal protrusions 23iA* and Sn alloy are transferred and bonded to the wide area of the tip of the film lead by heating and pressing with the bonding tool 32, and the metal protrusions 23 are peeled off from the substrate 22. (Figure 5b).
次にフィルムリード２ｏに転写・接合さｎて金属突起２
３を半導体素子２の電極６に位置合せするわけであるが
、この場合、フィルムリード２゜の巾広の領域と電極と
を位置合せするのみで良い（第６図Ｃ）。位置合せが終
了した段階で、金属突起２３は、確実に前記半導体素子
２の電極θ上の領域内に位置合せされ存在するものであ
る。この状態でボンディングツール３３で加圧・加熱す
ｎば、金属突起はＡｕ−ＡＲの合金で接合され、第５図
ｄの状態を得るものである。Next, the metal protrusion 2 is transferred and bonded to the film lead 2o.
3 to the electrode 6 of the semiconductor element 2. In this case, it is only necessary to align the wide area of the film lead 2° and the electrode (FIG. 6C). When the alignment is completed, the metal protrusion 23 is reliably aligned and present within the region above the electrode θ of the semiconductor element 2. In this state, by applying pressure and heating with the bonding tool 33, the metal protrusions are joined with the Au-AR alloy, resulting in the state shown in FIG. 5d.
発明の効果
■ 本発明によれば、延在したフィルムリ〜ドの巾広く
形成されている先端領域内に前記転写用の）金属突起が
かくｎでし甘う様に位置合せを行えば良＜１＊前記フイ
ルムリードに転写した金属突起を半導体素子の電極に接
合する際も、フィルムリードの巾広の先端領域を半導体
素子の電極領域に位置合せすれば良いから、著しるしく
位置合せが容易と々す、この工程での所要時間を短縮で
きるものである。Effects of the Invention ■ According to the present invention, it is only necessary to align the metal protrusion (for transfer) within the widely formed tip region of the extended film lead. <1*When bonding the metal protrusions transferred to the film lead to the electrodes of the semiconductor element, it is only necessary to align the wide tip region of the film lead with the electrode area of the semiconductor element, so alignment is extremely difficult. This is easy and can shorten the time required for this process.
■ また、金属突起も半導体素子の電極も巾広くなって
いるフィルムリードの先端領域を基準に位置合せを行な
うことができるので従来例で説明した第１図ｂ−またけ
Ｃ′の寸法Ａが上下、左右方向で変化し、フィルムリー
ドの強度を低下さすことがないので信頼性の高い半導体
装置を得ることができる。■ In addition, since the metal protrusions and the electrodes of the semiconductor element can be aligned based on the wide tip area of the film lead, the dimension A in Fig. 1 b-straddle C' explained in the conventional example can be adjusted. Since it changes in the vertical and horizontal directions and does not reduce the strength of the film lead, a highly reliable semiconductor device can be obtained.
■ さらに壕だ、位置合せが容易でかつ確実に実施でき
るので、金属突起とフィルムリードの位置合せづれや、
半導体素子の電極に対する位置合せづれが発生しない。■ In addition, positioning is easy and reliable, so it is possible to eliminate misalignment between metal protrusions and film leads,
Misalignment of the semiconductor element with respect to the electrode does not occur.
このため著しるしく接合強度が安定した信頼性の高い半
導体装置を得ることができる。Therefore, a highly reliable semiconductor device with significantly stable bonding strength can be obtained.
第１図（−）〜（Ｃ） Ｕ従来−のフィル・ムリーデと
金属突起および半導体素子の電極との接合方法を示す平
面図、第２図は本発明の第１の実施例のフィルムリード
の構造を示す平面図、第３図（ａ） 、 （ｂ）は本発
明のフィルムリードと金属突起および半導体素子の電極
との接合状態の断面図、同（Ｃ）は同接合状態の平面図
、第４図（ａ） 、 （ｂ）は本発明の他の実施例のフ
ィルムリードの構造を示す平面図、第６図（ａ）〜（ｄ
） ｆ１本発明を用いた転写パップ方式の工程断面図で
ある
１・・・・樹脂フィルム、２・・・・・半導体素子、６
・・・・・電極、２０・・・・・フィル リード、２１
，３１°°。
・・・巾広の先端領域、２３・・・・・金属突起。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名馳
派
図
第４図
（ａ、）
Ｃ４）
（ａ、）
（Ｃ）Figures 1 (-) to (C) are plan views showing a conventional method of bonding a film lead to a metal protrusion and an electrode of a semiconductor element; Figure 2 is a diagram showing a film lead according to a first embodiment of the invention; A plan view showing the structure, FIGS. 3(a) and 3(b) are cross-sectional views of a bonded state between the film lead of the present invention, a metal protrusion, and an electrode of a semiconductor element, and FIG. 3(C) is a plan view of the bonded state. FIGS. 4(a) and 4(b) are plan views showing the structure of a film lead according to another embodiment of the present invention, and FIGS. 6(a) to (d)
) f1 Process cross-sectional diagram of the transfer pad method using the present invention 1...Resin film, 2...Semiconductor element, 6
... Electrode, 20 ... Fill lead, 21
, 31°°. ...Wide tip region, 23...Metal protrusion. Name of agent: Patent attorney Toshio Nakao and one other person
Drawing 4 (a,) C4) (a,) (C)
Claims (1)
相対応する領域の巾が、樹脂フィルムから延在した他の
領域の巾よりも大きいフィルムリードを用い、前記リー
ドの相対応する領域に、基板上の前記金属突起を転写・
接合する工程、前記金属突起前記半導体素子の電極に接
合する工程とを有することを特徴とする半導体装置の製
造方法。 （２） フィルムリードの相対応する領域の巾が、金属
突起の外寸と同一もしくは大きいことを特徴とする特許
請求の範囲第１項記載の半導体装置の製造方法。 （３）フィルムリードの相対応する領域の巾が１．半導
体素子の電極寸法と同一もしくは小さいことを特徴とす
る特許請求の範囲第１項記載の半導体装置の製造方法。[Scope of Claims] 0) Using a film lead in which the width of the region where the metal protrusion is to be transferred and which corresponds to the electrode of the semiconductor element is larger than the width of the other region extending from the resin film, the lead The metal protrusions on the substrate are transferred to the corresponding areas of the
A method for manufacturing a semiconductor device, comprising the steps of bonding, and bonding the metal protrusion to an electrode of the semiconductor element. (2) The method for manufacturing a semiconductor device according to claim 1, wherein the width of the corresponding region of the film lead is the same as or larger than the outer dimension of the metal protrusion. (3) The width of the corresponding area of the film lead is 1. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the dimensions of the electrodes of the semiconductor element are the same or smaller.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58219808A JPS60111433A (en) | 1983-11-22 | 1983-11-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58219808A JPS60111433A (en) | 1983-11-22 | 1983-11-22 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60111433A true JPS60111433A (en) | 1985-06-17 |
| JPH0158865B2 JPH0158865B2 (en) | 1989-12-13 |
Family
ID=16741355
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58219808A Granted JPS60111433A (en) | 1983-11-22 | 1983-11-22 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60111433A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009078275A1 (en) * | 2007-12-14 | 2009-06-25 | Sharp Kabushiki Kaisha | Semiconductor device |
-
1983
- 1983-11-22 JP JP58219808A patent/JPS60111433A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009078275A1 (en) * | 2007-12-14 | 2009-06-25 | Sharp Kabushiki Kaisha | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0158865B2 (en) | 1989-12-13 |
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