JP2000260933A - Manufacture for semiconductor device - Google Patents
Manufacture for semiconductor deviceInfo
- Publication number
- JP2000260933A JP2000260933A JP11058819A JP5881999A JP2000260933A JP 2000260933 A JP2000260933 A JP 2000260933A JP 11058819 A JP11058819 A JP 11058819A JP 5881999 A JP5881999 A JP 5881999A JP 2000260933 A JP2000260933 A JP 2000260933A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- semiconductor
- holes
- solder
- pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、複数個の半導体チ
ップを積層した、より高い機能を有する半導体装置の製
造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having a higher function by stacking a plurality of semiconductor chips.
【０００２】[0002]
【従来の技術】昨今の急速な半導体技術の進歩により、
半導体チップの高性能化とチップサイズの小型化が図ら
れてきた。しかしながら、チップ自体の小型化によりそ
れをパッケージ化し実装するのが困難となってきてお
り、また実装コストの大幅な増加の原因にもなってい
る。2. Description of the Related Art Due to recent rapid advances in semiconductor technology,
2. Description of the Related Art Higher performance semiconductor chips and smaller chip sizes have been attempted. However, the miniaturization of the chip itself has made it difficult to package and mount it, and has also caused a significant increase in mounting cost.
【０００３】さらに、半導体装置に複合的な高い機能が
要求されるようになり、複数の半導体装置を組み込んだ
システムが要求され、結果的に基板上に半導体の占める
面積が大きくなってきている。この課題を解決すべく３
次元構造を持った半導体チップ・パッケージのアイデア
がすでに多数検討されている。例えば、特開平５−６３
１３７号や特開平６−２９１２５０号（特許番号第２６
０５９６８号）や特開平８−２６４７１２号や特開平１
０−１６３４１１号などである。これらに共通する基本
構造を図３に示す。半導体チップ１−１、１−２、１−
３を重ねあわせ、スルーホール４に形成された導電体物
質を介して電気的接続を得るものである。[0003] Furthermore, a complex high function is required for a semiconductor device, and a system incorporating a plurality of semiconductor devices is required. As a result, the area occupied by a semiconductor on a substrate is increasing. 3 to solve this problem
Many ideas for semiconductor chip packages having a two-dimensional structure have already been considered. For example, JP-A-5-63
137 and JP-A-6-291250 (Patent No. 26
05968), JP-A-8-264712 and JP-A-1
No. 0-163411. FIG. 3 shows a basic structure common to these. Semiconductor chips 1-1, 1-2, 1-
3 are overlapped with each other to obtain an electrical connection via a conductive substance formed in the through hole 4.
【０００４】[0004]
【発明が解決しようとする課題】本発明は、図４に示し
たような３次元構造を容易に実現させるべく創作された
ものであり、小型で実装面積が少なくかつ多機能である
３次元構造の半導体チップを得ることを目的とする。SUMMARY OF THE INVENTION The present invention has been created in order to easily realize a three-dimensional structure as shown in FIG. 4, and has a small size, a small mounting area, and a multifunctional structure. The purpose of the present invention is to obtain a semiconductor chip.
【０００５】[0005]
【課題を解決するための手段】請求項１の半導体装置の
製造方法は、電気信号取り出し用の配線および電極パッ
ドを形成した第１の半導体チップと、第１の半導体チッ
プと同じ位置に電気信号取り出し用の配線および電極パ
ッドを形成した第２の半導体チップを積層し、少なくと
も二つの半導体チップを備えた半導体装置を製造する半
導体装置の製造方法において、第１の半導体チップと第
２の半導体チップの電気信号取り出し用の電極パッドに
形成したスルーホールに、半田めっきを施した金属細線
ワイヤーを通したのち、加熱により半田を溶融させて、
第１と第２の半導体チップ間の電気的接合部を形成する
ことを特徴とする。According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a first semiconductor chip on which a wiring and an electrode pad for extracting an electric signal are formed; In a semiconductor device manufacturing method for stacking a second semiconductor chip on which an extraction wiring and an electrode pad are formed and manufacturing a semiconductor device having at least two semiconductor chips, a first semiconductor chip and a second semiconductor chip are provided. After passing a thin metal wire with solder plating through the through hole formed in the electrode pad for taking out the electric signal, the solder is melted by heating,
An electrical junction between the first and second semiconductor chips is formed.
【０００６】請求項１の半導体装置の製造方法において
は、チップに切断する前のウェハーの状態でホールを形
成し、複数のウェハーを積層したのち半田めっきを施し
たワイヤーをホールに通し、一括してリフローにより電
気的接合部を形成した後、チップサイズにダイシングし
てもよい（請求項２）。In the method of manufacturing a semiconductor device according to the first aspect of the present invention, a hole is formed in a state of a wafer before being cut into chips, a plurality of wafers are stacked, and a wire plated with solder is passed through the hole to collectively form a hole. After forming the electrical junction by reflow, dicing may be performed to a chip size (claim 2).
【０００７】[0007]
【発明の実施の形態】以下、本発明を実施の形態に基づ
き、詳細に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on embodiments.
【０００８】＜実施の形態１＞図２は、実施の形態１に
より作成された半導体装置の構造を示した断面図であ
る。半導体チップ１−１、１−２、１−３がパッド３−
１、３−２、３−３に開けられたスルーホール内に挿入
された金属ワイヤー４−１により、互いに電気的に接続
されている。<First Embodiment> FIG. 2 is a cross-sectional view showing a structure of a semiconductor device manufactured according to a first embodiment. The semiconductor chips 1-1, 1-2, and 1-3 are pads 3-
They are electrically connected to each other by metal wires 4-1 inserted into through holes formed in 1, 3, 2 and 3-3.
【０００９】次に、本発明の製造方法を、図１に基づい
て詳細に述べる。Next, the manufacturing method of the present invention will be described in detail with reference to FIG.
【００１０】図１−ａに示したように、半導体チップ１
−１上に、電気的接続をとるためのパッド３−１が形成
してある。パッド部のサイズは１００ミクロン角であ
る。このパッドの中央に直径８０ミクロンの大きさのス
ルーホール２−１を作成する。スルーホールの開口方法
は、レーザーで開ける方法やシリコンを異方性エッチン
グで開けておく方法などがある。なお、パッドの材質は
通常Ａｌが一般的だが、ここではＡｌ上にバリヤ層とし
てＴｉ／ＴｉＮ層を形成した上に、Ｃｕが形成してある
パッドを使用した。As shown in FIG. 1A, the semiconductor chip 1
A pad 3-1 for making an electrical connection is formed on -1. The size of the pad portion is 100 microns square. A through hole 2-1 having a diameter of 80 microns is formed at the center of the pad. As a method of opening the through hole, there is a method of opening with a laser or a method of opening silicon by anisotropic etching. The material of the pad is generally Al, but here, a pad in which a Ti / TiN layer is formed as a barrier layer on Al and Cu is formed is used.
【００１１】次に、図１−ｂに示したように、スルーホ
ールを形成した半導体チップ１−１、１−２、１−３を
位置合わせしながら重ねあわせ、次に、図１−ｃに示し
たように、表面に１０μｍの半田めっきを施した直径７
０μｍのＡｕ細線ワイヤー４−１を用意しておき、これ
をスルーホールに貫通させた。Next, as shown in FIG. 1B, the semiconductor chips 1-1, 1-2, and 1-3 having the through-holes are overlapped while being aligned. As shown, a diameter of 7 μm with a 10 μm solder plated surface
A 0 μm Au fine wire 4-1 was prepared and passed through a through hole.
【００１２】この状態でリフロー炉で半田を溶解せしめ
ることにより、半導体チップ１−１、１−２、１−３を
スルーホールを介して電気的に接続することができた。In this state, by melting the solder in a reflow furnace, the semiconductor chips 1-1, 1-2, and 1-3 could be electrically connected via through holes.
【００１３】＜実施の形態２＞図３は、実施の形態２に
より作成された半導体装置の構成を示した図である。第
１の半導体チップ１−１の上に第２の半導体チップ１−
２が積層されている。それぞれのチップ上にはパッド３
が複数個形成されており、半導体チップ１−１に形成さ
れたパッド群５はワイヤーボンディングするためのパッ
ドである。またチップ１−２上に形成されたパッド群７
もワイヤーボンディングするためのパッドである。ここ
で、パッド３に中央に半田めっきを施した金属ワイヤー
４を形成してあるパッド群６により、上下のチップの電
気的接続を取っている。<Second Embodiment> FIG. 3 is a diagram showing a configuration of a semiconductor device manufactured according to a second embodiment. On the first semiconductor chip 1-1, the second semiconductor chip 1-
2 are stacked. Pad 3 on each chip
Are formed, and a pad group 5 formed on the semiconductor chip 1-1 is a pad for wire bonding. The pad group 7 formed on the chip 1-2
Are also pads for wire bonding. Here, the upper and lower chips are electrically connected by a pad group 6 in which a metal wire 4 plated with solder is formed in the center of the pad 3.
【００１４】次に、実施の形態２の製造方法を、図３に
基づいて詳細に述べる。Next, the manufacturing method of the second embodiment will be described in detail with reference to FIG.
【００１５】図３に示したように、半導体チップ１−１
上に、電気的接続をとるためのパッド３がすでに形成し
てある。このパッド３が複数個形成され、パッド群５と
パッド群６が形成されている。このパッド部のサイズは
１００ミクロン角である。このうちのパッド群６につい
てのみ、中央に直径８０ミクロンの大きさのスルーホー
ルを作成する。スルーホールの開口方法は、レーザーで
開ける方法をもちいた。なお、パッドの材質は通常Ａｌ
が一般的だが、ここではＡｌ上にＡｕが形成してあるパ
ッドを使用した。As shown in FIG. 3, the semiconductor chip 1-1
Above, pads 3 for making electrical connections have already been formed. A plurality of the pads 3 are formed, and a pad group 5 and a pad group 6 are formed. The size of this pad is 100 microns square. For only the pad group 6, a through hole having a diameter of 80 microns is formed at the center. The method of opening the through-hole used a method of opening with a laser. The pad material is usually Al
However, here, a pad having Au formed on Al was used.
【００１６】次に、同様に、半導体チップ１−２上に
も、電気的接続をとるためのパッド３が形成してある。
このパッド３が複数個形成され、パッド群６とパッド群
７が形成されている。このパッド部のサイズは１００ミ
クロン角である。このうちのパッド群６についてのみ、
中央に直径８０ミクロンの大きさのスルーホールを作成
する。形成方法は先ほどと同じである。またパッド群６
については、チップ１−１と１−２を積層した際に、ス
ルーホールが貫通するように正確にアライメントできる
ように形成されている。スルーホールを形成した半導体
チップ１−１、１−２を位置合わせしながら重ねあわ
せ、次に、表面に１０μｍの半田めっきを施した直径７
０μｍのＡｕ細線ワイヤー４を用意しておき、これをス
ルーホールに貫通させた。Next, similarly, pads 3 for electrical connection are formed on the semiconductor chip 1-2.
A plurality of the pads 3 are formed, and a pad group 6 and a pad group 7 are formed. The size of this pad is 100 microns square. Only for pad group 6 of these,
A through hole having a diameter of 80 microns is formed at the center. The forming method is the same as above. Pad group 6
Is formed so that when the chips 1-1 and 1-2 are stacked, the alignment can be performed accurately so that the through holes penetrate. The semiconductor chips 1-1 and 1-2 having the through holes formed thereon were aligned with each other while being aligned, and then the surface was plated with a solder having a diameter of 10 μm.
A 0 μm Au fine wire 4 was prepared and passed through a through hole.
【００１７】この状態でリフロー炉で半田を溶解せしめ
ることにより、半導体チップ１−１、１−２をスルーホ
ールを介して電気的に接続できた。In this state, by melting the solder in a reflow furnace, the semiconductor chips 1-1 and 1-2 could be electrically connected via the through holes.
【００１８】[0018]
【発明の効果】本発明により、図４に記したような３次
元構造を容易に実現することができ、小型で実装面積の
少なく、かつ多機能である３次元構造の半導体チップ、
例えば第１のチップとしてマイコンチップと第２のチッ
プとしてメモリーを組み合わせることにより、従来より
小型で多機能な半導体チップのような半導体装置を得る
ことができた。According to the present invention, a three-dimensional semiconductor chip having a small size, a small mounting area, and a multi-function can be easily realized as shown in FIG.
For example, by combining a microcomputer chip as the first chip and a memory as the second chip, it is possible to obtain a semiconductor device such as a multifunctional semiconductor chip which is smaller than the conventional one.
【図１】本発明の製造方法を示した図。FIG. 1 is a view showing a manufacturing method of the present invention.
【図２】実施の形態１により形成した半導体チップの断
面図。FIG. 2 is a cross-sectional view of a semiconductor chip formed according to the first embodiment.
【図３】実施の形態２により作成した半導体チップの平
面図。FIG. 3 is a plan view of a semiconductor chip manufactured according to Embodiment 2;
【図４】一般的な半導体チップを積層した３次元構造の
断面図。FIG. 4 is a cross-sectional view of a three-dimensional structure in which general semiconductor chips are stacked.
１−１．第１の半導体チップ １−２．第２の半導体チップ １−３．第３の半導体チップ ２．スルーホール ３−１．第１の半導体チップの電極パッド ３−２．第２の半導体チップの電極パッド ３−３．第３の半導体チップの電極パッド ４−１．表面に半田めっきを施した金属細線ワイヤー ４−２．導電性材料 ５．第１の半導体チップのパッド群 ６．第１の半導体チップと第２の半導体チップを接続す
るためのパッド群 ７．第２の半導体チップのパッド群1-1. First semiconductor chip 1-2. Second semiconductor chip 1-3. 1. Third semiconductor chip Through hole 3-1. Electrode pad of first semiconductor chip 3-2. Electrode pad of second semiconductor chip 3-3. Electrode pad of third semiconductor chip 4-1. Fine metal wire with solder plating on the surface 4-2. Conductive material 5. 5. Pad group of first semiconductor chip 6. Pad group for connecting the first semiconductor chip and the second semiconductor chip Pad group of second semiconductor chip
Claims (2)
ドを形成した第１の半導体チップと、第１の半導体チッ
プと同じ位置に電気信号取り出し用の配線および電極パ
ッドを形成した第２の半導体チップを積層し、少なくと
も二つの半導体チップを備えた半導体装置を製造する半
導体装置の製造方法において、第１の半導体チップと第
２の半導体チップの電気信号取り出し用の電極パッドに
形成したスルーホールに、半田めっきを施した金属細線
ワイヤーを通したのち、加熱により半田を溶融させて、
第１の半導体チップと第２の半導体チップとの間の電気
的接合部を形成することを特徴とする半導体装置の製造
方法。1. A first semiconductor chip on which wiring and electrode pads for extracting electric signals are formed, and a second semiconductor chip on which wiring and electrode pads for extracting electric signals are formed at the same position as the first semiconductor chip In a method of manufacturing a semiconductor device having at least two semiconductor chips, wherein a through hole formed in an electrode pad for extracting an electric signal of the first semiconductor chip and the second semiconductor chip includes: After passing the solder-plated thin metal wire, the solder is melted by heating,
A method for manufacturing a semiconductor device, comprising: forming an electrical junction between a first semiconductor chip and a second semiconductor chip.
おいて、チップに切断する前のウェハーの状態でスルー
ホールを形成し、複数のウェハーを積層したのち半田め
っきを施したワイヤーをスルーホールに通し、一括して
リフローにより電気的接合部を形成した後、チップサイ
ズにダイシングすることを特徴とする半導体装置の製造
方法。2. A method of manufacturing a semiconductor device according to claim 1, wherein a through-hole is formed in a state of the wafer before being cut into chips, a plurality of wafers are stacked, and a wire plated with solder is formed in the through-hole. Forming an electrical joint by reflow at a time, and then dicing to a chip size.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP05881999A JP3697926B2 (en) | 1999-03-05 | 1999-03-05 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP05881999A JP3697926B2 (en) | 1999-03-05 | 1999-03-05 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000260933A true JP2000260933A (en) | 2000-09-22 |
| JP3697926B2 JP3697926B2 (en) | 2005-09-21 |
Family
ID=13095245
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP05881999A Expired - Fee Related JP3697926B2 (en) | 1999-03-05 | 1999-03-05 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3697926B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100435813B1 (en) * | 2001-12-06 | 2004-06-12 | 삼성전자주식회사 | Multi chip package using metal bar and manufacturing method thereof |
| KR100817718B1 (en) | 2006-12-27 | 2008-03-27 | 동부일렉트로닉스 주식회사 | Semiconductor device fabricating method |
| KR101078737B1 (en) | 2009-08-10 | 2011-11-02 | 주식회사 하이닉스반도체 | Stacked semiconductor package |
| US8159066B2 (en) | 2009-08-10 | 2012-04-17 | Hynix Semiconductor Inc. | Semiconductor package having a heat dissipation member |
| US8368195B2 (en) | 2009-01-05 | 2013-02-05 | Hitachi Metals, Ltd. | Semiconductor device including arrangement to control connection height and alignment between a plurity of stacked semiconductor chips |
| JP5733486B1 (en) * | 2014-09-09 | 2015-06-10 | 千住金属工業株式会社 | Cu column, Cu core column, solder joint and through silicon via |
| JP2015519751A (en) * | 2012-05-17 | 2015-07-09 | ヘプタゴン・マイクロ・オプティクス・プライベート・リミテッドＨｅｐｔａｇｏｎ Ｍｉｃｒｏ Ｏｐｔｉｃｓ Ｐｔｅ． Ｌｔｄ． | Wafer stack assembly |
-
1999
- 1999-03-05 JP JP05881999A patent/JP3697926B2/en not_active Expired - Fee Related
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6908785B2 (en) | 2001-12-06 | 2005-06-21 | Samsung Electronics Co., Ltd. | Multi-chip package (MCP) with a conductive bar and method for manufacturing the same |
| US7531890B2 (en) | 2001-12-06 | 2009-05-12 | Samsung Electronics Co., Ltd. | Multi-chip package (MCP) with a conductive bar and method for manufacturing the same |
| KR100435813B1 (en) * | 2001-12-06 | 2004-06-12 | 삼성전자주식회사 | Multi chip package using metal bar and manufacturing method thereof |
| KR100817718B1 (en) | 2006-12-27 | 2008-03-27 | 동부일렉트로닉스 주식회사 | Semiconductor device fabricating method |
| US8368195B2 (en) | 2009-01-05 | 2013-02-05 | Hitachi Metals, Ltd. | Semiconductor device including arrangement to control connection height and alignment between a plurity of stacked semiconductor chips |
| KR101078737B1 (en) | 2009-08-10 | 2011-11-02 | 주식회사 하이닉스반도체 | Stacked semiconductor package |
| US8159066B2 (en) | 2009-08-10 | 2012-04-17 | Hynix Semiconductor Inc. | Semiconductor package having a heat dissipation member |
| US8253256B2 (en) | 2009-08-10 | 2012-08-28 | Hynix Semiconductor Inc. | Stacked semiconductor package |
| US9716081B2 (en) | 2012-05-17 | 2017-07-25 | Heptagon Micro Optics Pte. Ltd. | Assembly of wafer stacks |
| JP2015519751A (en) * | 2012-05-17 | 2015-07-09 | ヘプタゴン・マイクロ・オプティクス・プライベート・リミテッドＨｅｐｔａｇｏｎ Ｍｉｃｒｏ Ｏｐｔｉｃｓ Ｐｔｅ． Ｌｔｄ． | Wafer stack assembly |
| US10903197B2 (en) | 2012-05-17 | 2021-01-26 | Ams Sensors Singapore Pte. Ltd. | Assembly of wafer stacks |
| US9997506B2 (en) | 2012-05-17 | 2018-06-12 | Heptagon Micro Optics Pte. Ltd. | Assembly of wafer stacks |
| JP5733486B1 (en) * | 2014-09-09 | 2015-06-10 | 千住金属工業株式会社 | Cu column, Cu core column, solder joint and through silicon via |
| CN106688085A (en) * | 2014-09-09 | 2017-05-17 | 千住金属工业株式会社 | Cu column, Cu nuclear column, solder joint, and through-silicon via |
| KR20180021222A (en) * | 2014-09-09 | 2018-02-28 | 센주긴조쿠고교 가부시키가이샤 | Cu COLUMN, Cu NUCLEAR COLUMN, SOLDER JOINT, AND THROUGH-SILICON VIA |
| TWI566650B (en) * | 2014-09-09 | 2017-01-11 | Senju Metal Industry Co | Copper pillars, copper core posts, welded joints and silicon through electrodes |
| US10811376B2 (en) | 2014-09-09 | 2020-10-20 | Senju Metal Industry Co., Ltd. | Cu column, Cu core column, solder joint, and through-silicon via |
| WO2016038686A1 (en) * | 2014-09-09 | 2016-03-17 | 千住金属工業株式会社 | Cu COLUMN, Cu NUCLEAR COLUMN, SOLDER JOINT, AND THROUGH-SILICON VIA |
| KR102315758B1 (en) | 2014-09-09 | 2021-10-20 | 센주긴조쿠고교 가부시키가이샤 | Cu COLUMN, Cu NUCLEAR COLUMN, SOLDER JOINT, AND THROUGH-SILICON VIA |
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