JPS5994829A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5994829A
JPS5994829A JP57204761A JP20476182A JPS5994829A JP S5994829 A JPS5994829 A JP S5994829A JP 57204761 A JP57204761 A JP 57204761A JP 20476182 A JP20476182 A JP 20476182A JP S5994829 A JPS5994829 A JP S5994829A
Authority
JP
Japan
Prior art keywords
film
annealing
flash lamp
substrate
deposition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57204761A
Other languages
Japanese (ja)
Inventor
Yoichiro Numazawa
陽一郎 沼澤
Koji Yamazaki
孝二 山崎
Kuniyuki Hamano
浜野　邦幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57204761A priority Critical patent/JPS5994829A/en
Publication of JPS5994829A publication Critical patent/JPS5994829A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/48—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating by irradiation, e.g. photolysis, radiolysis, particle radiation
    • C23C16/482—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating by irradiation, e.g. photolysis, radiolysis, particle radiation using incoherent light, UV to IR, e.g. lamps
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/56—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02277—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition the reactions being activated by other means than plasma or thermal, e.g. photo-CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
    • H01L21/02348—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light treatment by exposure to UV light

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • General Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)

Abstract

PURPOSE:To form the excellent deposition film having no pinhole by a method wherein, in the process where a film is formed utilizing a photochemical vaporphase reaction, a flash lamp annealing is repeatedly performed at a fixed rate of time interval in the process of film deposition by irradiating ultraviolet rays. CONSTITUTION:After a substrate 104 has been provided on a pedestal 105, the interior of a reaction cell is sufficiently evacuated in the state wherein a valve 106 is closed. Subsequently, the valve 106 is opened, gas containing N2O, SiH4 and mercury is introduced, and when it is stabilized into a steady flow, a light is radiated using a low voltage mercury lamp. Through the above light irradiation, a silicon oxide film is deposited. At this point, a pulse annealing is performed at the interval of 100sec using a xenon flash lamp 102. Using said pulse light, an annealing is performed on the surface only of the deposition film giving no effect on the substrate. Using a photochemical vapor-phase growing method, including a repeated flash lamp annealing process, the excellent pinholeless deposition film having high density can be obtained at the low substrate temperature of 20 deg.C.

Description

【発明の詳細な説明】 本発明は、化学気相反応を用いて、膜を形成する方法に
関し、特に、光照射下で膜を形成する方法に関している
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of forming a film using a chemical vapor phase reaction, and particularly to a method of forming a film under light irradiation.

近年におけるＶＬＳＩのより高集積化に伴ない、深さ方
向および横方向の不純物分布全正確に制御する事、又プ
ロセス誘起欠陥全極力少なくする必要がある事等の理由
から、プロセスの低温化が重要な課題である。In recent years, as VLSIs have become more highly integrated, it has become necessary to accurately control the impurity distribution in the depth and lateral directions, and to reduce process-induced defects as much as possible. This is an important issue.

低温で膜全形成する方法とに、光エネルギーを用いた光
化学気相成長法が、特に注目されてきてイル。光化学気
相反応による堆積膜は、プラズマ気相成長における様な
荷電粒子等による胛射損傷はなく、良質の膜といえる。Photochemical vapor deposition, which uses light energy, is attracting particular attention as a method for forming entire films at low temperatures. The film deposited by photochemical vapor phase reaction is not damaged by radiation due to charged particles as in plasma vapor phase growth, and can be said to be a good quality film.

しかしながら、基板温度５００°Ｃ以下で膜形成した場
合、該堆積膜の稠密性において難点があり、それ故、希
釈弗酸液等に対するエツチング速度が太きい。父、従来
の光化学気相成長膜全パッシイベイション膜として旋用
した際、配線アルミニウムのヒロック抑制効果が少なく
、それ故、信頼性に難点があった。さらにこれからのＶ
ＬＳＩのパッシイベイション膜、あるいは多層配線の層
間絶縁膜として使用するためには、ピンホールは皆無に
する必要がある。However, when a film is formed at a substrate temperature of 500° C. or lower, there is a problem in the density of the deposited film, and therefore the etching rate with diluted hydrofluoric acid solution is high. When a conventional photochemical vapor deposition film was used as a total passivation film, it had little effect on suppressing hillocks on aluminum wiring, and therefore had problems with reliability. Further future V
In order to use it as a passivation film for LSI or an interlayer insulating film for multilayer wiring, it is necessary to have no pinholes.

本発明の目的は、上記問題を解決し、ピンホールの無い
良質の堆積膜を形成する方法全提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a method for forming a high-quality deposited film without pinholes.

本発明の特徴は、光化学気相反応により膜全形成する工
程において、紫外光照射し膜堆積する過程テ、一定時間
間隔での７う、シーランプアニールを繰り返丁ことにあ
る。The feature of the present invention is that in the step of forming the entire film by photochemical vapor phase reaction, during the step of irradiating the film with ultraviolet light and depositing the film, sea lamp annealing is repeated at regular time intervals.

この様に、繰、り返しのフラッシュランプアニール工程
全含む光化学気相成長法を用いることによフ、基板温度
を室温に保ちかつ稠密性に優れ１ピンホールの無い堆積
膜を得ることが可能となる。In this way, by using the photochemical vapor deposition method that includes all the repeated flash lamp annealing steps, it is possible to maintain the substrate temperature at room temperature and obtain a deposited film with excellent density and no pinholes. becomes.

次に実施例に基づく膜堆積法を図を用いて説明する。Next, a film deposition method based on an example will be explained using figures.

第１図は、本実施例に用いた膜堆積装置の概要全示すも
のである。第１図において、１０１は光化学気相反応を
生じさせるための低圧水銀ランプで、１０２が本特許に
基づくところのクセノンフラッシュランプである。本実
施例においては、低圧水銀ランプの波長２５７ｎｍ光會
、光化学反応に使用せしめる様、光透過窓１０３は石英
で形成されている。次に、本実施例による膜堆積手順に
ついて述べる。基板１０４全合座１０５に設置後、パル
プ１０６全閉じたまま、十分に反応セル内を排気する。FIG. 1 shows the entire outline of the film deposition apparatus used in this example. In FIG. 1, 101 is a low-pressure mercury lamp for producing a photochemical vapor phase reaction, and 102 is a xenon flash lamp based on this patent. In this embodiment, the light transmitting window 103 is made of quartz so that it can be used for photochemical reactions using a low-pressure mercury lamp with a wavelength of 257 nm. Next, the film deposition procedure according to this example will be described. After all the substrates 104 are placed on the joint seat 105, the inside of the reaction cell is sufficiently evacuated while the pulp 106 is completely closed.

その後パルプ１０６を開口し、Ｎ２０と５ｉｌ−１４に
約１０　　Ｔｏｒｒ分圧の水銀を含んだ混合ガスを導入
し、約ＩＴｏｒｒの定常流で安定したところで、５００
Ｗの低圧水銀ランプにより光照射する。この光照射によ
りシリコン酸化膜が堆積することは公知の事実である。Thereafter, the pulp 106 was opened and a mixed gas containing N20 and 5il-14 containing mercury at a partial pressure of about 10 Torr was introduced.
Light is irradiated using a W low-pressure mercury lamp. It is a known fact that a silicon oxide film is deposited by this light irradiation.

ここで、本実施例においては、クセノンフラッシュラン
プにより、１００秒間隔でパルスアニーリングを行なっ
た。In this example, pulse annealing was performed at 100 second intervals using a xenon flash lamp.

このパルス光により、基板４には影＃を与えることなく
、堆積膜の表面のみをアニールすることになる。ここで
、このパルスアニールの時間間隔は、膜成長速度と関係
しており、本実施例においては、１００秒間隔が最適で
あった。This pulsed light anneals only the surface of the deposited film without casting a shadow on the substrate 4. Here, the time interval of this pulse annealing is related to the film growth rate, and in this example, an interval of 100 seconds was optimal.

以上の様に、繰り返しのフラッシュランプアニール工程
を含む、光化学気相成長法を用いることにより、基板温
度が２０℃という低温にて、稠密性に優れ、ピンホール
の無い、良質の堆積膜を得ることが可能となる。囲えば
、本発明による方法で堆積したシリコン酸化膜を用いて
Ｍ、０８型構造を作り、その特性を、従来の光化学気相
成長法によるシリコン酸化膜音用いたものと比較したと
ころ、界面準位密度が小さく、特性の再現性も良く、又
ヒステリシスも少ない良好の結果を得ることができた。As described above, by using the photochemical vapor deposition method that includes repeated flash lamp annealing steps, a high-quality deposited film with excellent density and no pinholes can be obtained at a low substrate temperature of 20°C. becomes possible. Specifically, an M,08 type structure was fabricated using a silicon oxide film deposited by the method of the present invention, and its characteristics were compared with those of a silicon oxide film deposited using the conventional photochemical vapor deposition method. Good results were obtained with low phase density, good reproducibility of characteristics, and little hysteresis.

これはクセノンフラッシュによるアニール効果とともに
、パルス的ではあるが、膜堆積時における表面反応をも
律速しでいる効果によると考えられる。This is thought to be due to the annealing effect of the xenon flash as well as the effect of controlling the rate of the surface reaction during film deposition, albeit in a pulsed manner.

次に、上述した本発明による方法で堆積した膜１Ｍ０８
）ランジスタのパッシイベイションに使用した例につい
て述べる。第２図において、２０１はＰ型シリコン基板
であり、ソース領域２０３及びドレイン領域２０１．砒
素拡散により形成し、シリコン酸化膜２０２に選択的に
開口１４１ｓ　ｋ設け、ソース電極２０５．ドレイン電
極２０６及びゲート電極２０７をアルミ蒸着によシ形成
後、本発明に基づく光化学気相成長シリコン酸化膜ヲノ
＜ツシイベイション膜２０８として使用したＭＯ８型ト
ランジスタ全示す。この様なＭ（ＪＳ型トランジスタの
信頼性評価において、本発明による光化学気相成長シリ
コンば化膜によるパッシイペイションは、その膜の稠祈
性が優れている点、又アルミヒロック抑制効果が優れて
いる点で有効である。実除に、本発明による堆積シリコ
ン酸化膜の代わりに、従来の光化学気相成長シリコンｉ
亥化膜ヲノ＜ツシイベイション膜２０８に用いた１ＶＩ
Ｕｓ型トランジスタを作製し、その信頼性を比較評価し
たところ、本発明によるシリコン［伎化膜による）（ツ
シイペイションが、信頼性を非辞に増加させることが、
見い出された。Next, the film 1M08 deposited by the method according to the invention described above
) An example of use in transistor passivation will be described. In FIG. 2, 201 is a P-type silicon substrate, including a source region 203 and a drain region 201 . Formed by arsenic diffusion, openings 141sk are selectively provided in the silicon oxide film 202, and source electrodes 205. After forming a drain electrode 206 and a gate electrode 207 by aluminum evaporation, a MO8 type transistor is shown in which a photochemical vapor deposition silicon oxide film according to the present invention is used as an oxidation film 208. In evaluating the reliability of such M(JS type transistors), the passivation using the photochemical vapor deposition silicon oxide film according to the present invention has been shown to have excellent film consistency and an excellent aluminum hillock suppressing effect. In fact, in place of the deposited silicon oxide film according to the present invention, conventional photochemical vapor deposition silicon i
1VI used for the oxidation film 208
When we fabricated Us-type transistors and compared and evaluated their reliability, we found that the silicon pation of the present invention significantly increases reliability.
Found out.

さら［、本発明による光化学気相成長シリコン酸化膜を
、バイポーラメモリの多層配線の層間肥祿膜として１更
用したところ、層配線間のショートが無く、歩留ま！ｌ
ｌ全改善することができた。Furthermore, when the photochemical vapor deposition silicon oxide film according to the present invention was used once again as an interlayer thickening film for multilayer wiring in a bipolar memory, there was no short circuit between layer wirings, and the yield was improved! l
I was able to improve everything.

以上の様に、本発明による堆積膜の形成法は、ＶＬ］の
製造に非常に役に立つものである。As described above, the method for forming a deposited film according to the present invention is very useful for manufacturing VL.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、本発明の実施例に用いた膜堆積装置を示す概
要図である。側１図において、１０１・・・・・・低圧
水銀ランプ、１０２・・・・・クセノンフラッシュラン
プ、１０３・・・・・石英光透過窓、１０４・・・・・
・基板、１０５・・・・・・基板台座、１０６・・・・
・・パルプ、である。 第２図は、本発明に基づく堆積膜のＨ住を評価するのに
用いたＭＯＳ）ランジスタの断面図である。第２図にお
いて、 ２０１・・・・・・Ｐ型シリコン基板、２０２・・・・
・シリコン戚化膜、２０３・・・・・・ソース領域、２
０４・・・・・ドレイン領域、２０５・・・・・・ソー
ス電極、２０６・・・・・・ドレイン電極、２０７・・
・・・・ゲート電極、２０８・・・・・・本発明に基づ
く光化学気相成長シリコン酸化膜（パッシイペイション
膜）である。 第１　図 − ０７ 鉾２図FIG. 1 is a schematic diagram showing a film deposition apparatus used in an example of the present invention. In side 1 diagram, 101...low pressure mercury lamp, 102...xenon flash lamp, 103...quartz light transmission window, 104...
・Substrate, 105...Substrate pedestal, 106...
...Pulp. FIG. 2 is a cross-sectional view of a MOS transistor used to evaluate the H concentration of the deposited film according to the present invention. In FIG. 2, 201...P-type silicon substrate, 202...
・Silicon film, 203... Source region, 2
04...Drain region, 205...Source electrode, 206...Drain electrode, 207...
. . . Gate electrode, 208 . . . Photochemical vapor deposition silicon oxide film (passive separation film) based on the present invention. Figure 1 - 07 Hoko 2

Claims (1)

【特許請求の範囲】[Claims] 基板上に、光化学気相反応により、硅素酸化膜、硅素窒
化膜等の絶縁膜全形成する工程において、紫外光を照射
し膜堆積する過程で、一定時間間隔でのフラッシュラン
プによるアニーリングを繰り返すことを特徴とする半導
体装置の製造方法。In the process of completely forming an insulating film such as a silicon oxide film or silicon nitride film on a substrate by photochemical vapor phase reaction, annealing with a flash lamp is repeated at regular intervals during the process of irradiating ultraviolet light and depositing the film. A method for manufacturing a semiconductor device, characterized by:
JP57204761A 1982-11-22 1982-11-22 Manufacture of semiconductor device Pending JPS5994829A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57204761A JPS5994829A (en) 1982-11-22 1982-11-22 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57204761A JPS5994829A (en) 1982-11-22 1982-11-22 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5994829A true JPS5994829A (en) 1984-05-31

Family

ID=16495904

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57204761A Pending JPS5994829A (en) 1982-11-22 1982-11-22 Manufacture of semiconductor device

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59163831A (en) * 1983-03-09 1984-09-14 Fujitsu Ltd Manufacture of semiconductor device and manufacturing apparatus therefor
US4735821A (en) * 1985-09-21 1988-04-05 Semiconductor Energy Laboratory Co., Ltd. Method for depositing material on depressions
JPH04291916A (en) * 1991-03-20 1992-10-16 Kokusai Electric Co Ltd Method and apparatus for vapor growth
US5308651A (en) * 1986-12-25 1994-05-03 Kawasaki Steel Corp. Photochemical vapor deposition process
US5462767A (en) * 1985-09-21 1995-10-31 Semiconductor Energy Laboratory Co., Ltd. CVD of conformal coatings over a depression using alkylmetal precursors
US6067931A (en) * 1996-11-04 2000-05-30 General Electric Company Thermal processor for semiconductor wafers

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59163831A (en) * 1983-03-09 1984-09-14 Fujitsu Ltd Manufacture of semiconductor device and manufacturing apparatus therefor
US4735821A (en) * 1985-09-21 1988-04-05 Semiconductor Energy Laboratory Co., Ltd. Method for depositing material on depressions
US5462767A (en) * 1985-09-21 1995-10-31 Semiconductor Energy Laboratory Co., Ltd. CVD of conformal coatings over a depression using alkylmetal precursors
US5308651A (en) * 1986-12-25 1994-05-03 Kawasaki Steel Corp. Photochemical vapor deposition process
JPH04291916A (en) * 1991-03-20 1992-10-16 Kokusai Electric Co Ltd Method and apparatus for vapor growth
US6067931A (en) * 1996-11-04 2000-05-30 General Electric Company Thermal processor for semiconductor wafers

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