JP2502789B2 - Method for manufacturing thin film transistor - Google Patents
Method for manufacturing thin film transistorInfo
- Publication number
- JP2502789B2 JP2502789B2 JP12847690A JP12847690A JP2502789B2 JP 2502789 B2 JP2502789 B2 JP 2502789B2 JP 12847690 A JP12847690 A JP 12847690A JP 12847690 A JP12847690 A JP 12847690A JP 2502789 B2 JP2502789 B2 JP 2502789B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- insulating film
- film
- silicon
- silicon oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Description
【発明の詳細な説明】 産業上の利用分野 本発明は、例えば薄膜トランジスタや半導体メモリー
等に用いる事が可能である絶縁膜の製造方法及び薄膜ト
ランジスタの製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an insulating film and a method of manufacturing a thin film transistor, which can be used in, for example, a thin film transistor, a semiconductor memory or the like.
従来の技術 シリコン半導体において最も使用される絶縁膜は酸化
シリコン膜及び窒化シリコン膜であるが以下に酸化シリ
コン膜の形成方法を例にとって説明する。2. Description of the Related Art The most used insulating film in a silicon semiconductor is a silicon oxide film and a silicon nitride film, but a method for forming a silicon oxide film will be described below as an example.
従来シリコン半導体に用いられる絶縁膜の形成方法と
しては、熱酸化法、気相成長法（CVD法）及びスパッタ
法（PVD法）等がある。Conventional methods for forming an insulating film used for a silicon semiconductor include a thermal oxidation method, a vapor phase growth method (CVD method), and a sputtering method (PVD method).
結晶シリコン半導体においては、シリコンと酸化シリ
コン膜との界面においてデバイス特性に影響を与えるト
ラップ等の欠陥準位が少ない良質な酸化シリコン膜が形
成できるため熱酸化法が最も一般的に用いられている。In the crystalline silicon semiconductor, the thermal oxidation method is most commonly used because a high-quality silicon oxide film with few defect states such as traps that affects device characteristics can be formed at the interface between silicon and the silicon oxide film. .
熱酸化法は、高温（一般的には1000℃以上）に加熱さ
れた反応炉中に基板を維持し反応炉中に酸素あるいは水
蒸気を導入することにより、酸素がガス中から基板表面
へ移動しシリコン膜中に取り込まれることにより酸化シ
リコン膜が形成される。熱酸化膜の形成速度はガス量
（酸素濃度）と酸化物中への酸素の固溶度により決定さ
れるため、充分な酸化速度を得るためには基板温度を充
分高温に保つ必要がある。The thermal oxidation method moves oxygen from the gas to the substrate surface by maintaining the substrate in a reaction furnace heated to a high temperature (generally 1000 ° C or higher) and introducing oxygen or water vapor into the reaction furnace. A silicon oxide film is formed by being taken into the silicon film. Since the formation rate of the thermal oxide film is determined by the amount of gas (oxygen concentration) and the solid solubility of oxygen in the oxide, it is necessary to keep the substrate temperature sufficiently high to obtain a sufficient oxidation rate.
熱酸化法に比べて低温で絶縁膜を形成する手法として
は気相成長法（CVD法）やスパッタ法（PDV法）がある。As a method of forming an insulating film at a lower temperature than the thermal oxidation method, there are a vapor phase growth method (CVD method) and a sputtering method (PDV method).
一般的なCVD法による酸化シリコン膜の形成方法とし
てはシリコンを構成元素として含むガスと酸素を構成元
素として含むガスを混合した雰囲気を熱分解する事によ
り酸化シリコンを形成する方法が用いられる。CVD法は
熱酸化法に比べて低温で形成可能であるが、充分な形成
速度あるいは電気特性（誘電率や耐圧等）を得るために
は600℃以上の基板温度が必要である。As a method of forming a silicon oxide film by a general CVD method, a method of forming silicon oxide by thermally decomposing an atmosphere in which a gas containing silicon as a constituent element and a gas containing oxygen as a constituent element are mixed is used. The CVD method can be formed at a lower temperature than the thermal oxidation method, but a substrate temperature of 600 ° C. or higher is required to obtain a sufficient formation rate or electric characteristics (dielectric constant, breakdown voltage, etc.).
またPVD法による代表的な絶縁膜の形成方法としては
スパッタ法が挙げられる。スパッタ法は真空中での荷電
粒子によるターゲットへの物理的な衝突を利用するた
め、熱酸化法やCVD法に比べてさらに低温での成膜が可
能であるがピンホールが形成され易いために膜厚を厚く
したり多層構成にする必要がある。また段差部での被覆
性（ステップカバレージ）が良くないという問題点があ
る。Further, as a typical method of forming an insulating film by the PVD method, there is a sputtering method. Since the sputtering method utilizes physical collision of charged particles with a target in a vacuum, it is possible to form a film at a lower temperature than the thermal oxidation method or the CVD method, but pinholes are easily formed. It is necessary to increase the film thickness or make a multilayer structure. There is also a problem that the coverage (step coverage) at the step portion is not good.
発明が解決しようとする課題 酸化シリコン膜の製造方法として一般的に用いられて
いる熱酸化法は、前述のように充分な酸化速度を得るた
めには酸素あるいは水蒸気を含む雰囲気中で基板を高温
に加熱する必要がある。基板の高温処理は酸化の工程以
前に形成したデバイスに対して、導入済みの不純物の濃
度や分布を変化させたり最悪の場合には形成済みのデバ
イスの破壊を引き起こす等の問題がある。また、基板材
料としてもSiや石英等の1000℃以上の高温に耐える基板
以外は使用できない問題ある。近年、デバイスの微細化
が進むにつれプロセス温度の低温化が不可欠になってき
ているが、熱酸化法においては基板温度は酸化速度に対
して指数関数的に影響するために低温で熱酸化を行う場
合においては酸化時間が非常に長くなり実用的でない。Problems to be Solved by the Invention The thermal oxidation method, which is generally used as a method for manufacturing a silicon oxide film, requires a high temperature of the substrate in an atmosphere containing oxygen or water vapor in order to obtain a sufficient oxidation rate as described above. Need to be heated. The high temperature treatment of the substrate has a problem that the concentration and distribution of the introduced impurities are changed with respect to the device formed before the oxidation step, and in the worst case, the formed device is destroyed. In addition, as a substrate material, there is a problem that only substrates such as Si and quartz that can withstand a high temperature of 1000 ° C. or higher cannot be used. In recent years, as device miniaturization progresses, it has become essential to lower the process temperature. In the thermal oxidation method, the substrate temperature exponentially affects the oxidation rate, so thermal oxidation is performed at a low temperature. In some cases, the oxidation time becomes very long, which is not practical.
熱酸化法に比べて低温で絶縁膜が形成可能な気相成長
法（CVD法）やスパッタ法に代表されるPVD法は低温形成
時には良質な絶縁膜が得難く、ピンホールの発生による
絶縁不良等の問題が発生する。従来、薄膜トランジスタ
等の絶縁膜としてCVD法あるいはPVD法により形成した絶
縁膜を用いる場合には、ピンホールの影響を避けるため
に絶縁膜の膜厚を厚くしたり、絶縁膜の形成を２度に分
ける、あるいは２種類の絶縁膜を積層することにより絶
縁不良の問題に対処している。PVD method typified by vapor phase growth method (CVD method) and sputtering method that can form an insulating film at a lower temperature than thermal oxidation method makes it difficult to obtain a good quality insulating film at low temperature formation, resulting in poor insulation due to pinholes. Problems such as occur. Conventionally, when an insulating film formed by a CVD method or a PVD method is used as an insulating film for a thin film transistor or the like, the insulating film should be thickened or the insulating film should be formed twice in order to avoid the effect of pinholes. The problem of insulation failure is dealt with by dividing or laminating two kinds of insulating films.
CVD法やPVD法により形成した絶縁膜は熱酸化法に対し
て低温で形成可能であるが、シリコンと絶縁膜界面にお
けるトラップ準位が熱酸化法に比べて多いためにデバイ
スの電気特性や信頼性への影響が避けられない。The insulating film formed by the CVD method or PVD method can be formed at a lower temperature than the thermal oxidation method, but since the trap level at the interface between silicon and the insulating film is higher than that of the thermal oxidation method, the electrical characteristics and reliability of the device The effect on sex is unavoidable.
また、近年盛んに研究されている薄膜トランジスタ等
の能動素子をマトリックス状に形成したアクティブマト
リックスアレイを用いた液晶表示装置や、イメージセン
サ等の入出力デバイスにおいては安価で大面積化が容易
なガラス基板が用いられることが多い。ガラス基板は耐
熱性が低いために低温（600℃以下）で良質な絶縁膜を
形成する必要がある。特に薄膜トランジスタの活性層と
して高移動度な多結晶シリコンを用いた場合、良好なト
ランジスタを得るためには多結晶シリコン上に界面トラ
ップ等の欠陥の少ない良質な絶縁膜を低温（ガラスの耐
熱温度以下）で作成することが必要不可欠となってく
る。実際には良好な絶縁膜とシリコン界面を形成するた
めに熱酸化法が用いられる事が多いが、前述のように石
英等の高融点材料を用いざるを得ずコストの点で問題が
生じる。Further, in a liquid crystal display device using an active matrix array in which active elements such as thin film transistors and the like, which have been actively researched in recent years, and an input / output device such as an image sensor, a glass substrate which is inexpensive and can easily have a large area Is often used. Since the glass substrate has low heat resistance, it is necessary to form a good insulating film at low temperature (600 ° C or lower). In particular, when high mobility polycrystalline silicon is used as the active layer of a thin film transistor, a good quality insulating film with few defects such as interface traps is formed on the polycrystalline silicon at a low temperature (below the heat resistant temperature of glass) in order to obtain a good transistor. ) Will be indispensable. In practice, a thermal oxidation method is often used to form a good insulating film-silicon interface, but as described above, a high melting point material such as quartz is inevitably used, which causes a problem in cost.
課題を解決するための手段 基板上に半導体薄膜を形成し、前記半導体薄膜を酸
素、酸素化合物、水蒸気あるいは窒素を構成元素として
含むガスのうち少なくとも１種類以上の気体を含む雰囲
気中で、エネルギービーム（例えばレーザー光や電子ビ
ーム、赤外線等）の照射を行うことにより半導体薄膜表
面にピンホールの少ない絶縁物薄膜を低温で形成する。Means for Solving the Problems A semiconductor thin film is formed on a substrate, and the semiconductor thin film is subjected to energy beam irradiation in an atmosphere containing at least one kind of gas containing oxygen, oxygen compound, water vapor or nitrogen as a constituent element. By irradiating (for example, laser light, electron beam, infrared rays, etc.), an insulating thin film with few pinholes is formed at a low temperature on the surface of the semiconductor thin film.
また、前記絶縁膜を薄膜トランジスタ等の能動素子に
応用する場合には、前記絶縁膜層上にさらに第２の絶縁
膜を形成することにより活性層と絶縁膜との外面におい
てトラップ等の少ない良質な絶縁膜を形成しつつ、かつ
所望の電気的特性を持つ絶縁膜を得ることが可能であ
る。Further, when the insulating film is applied to an active element such as a thin film transistor, a second insulating film is further formed on the insulating film layer so that the outer surface between the active layer and the insulating film has a small number of traps and the like. It is possible to obtain an insulating film having desired electrical characteristics while forming the insulating film.
作用 シリコン半導体に対しては、酸素、酸素化合物、水蒸
気あるいは窒素を構成元素として含むガスとして含む雰
囲気のうち少なくとも１種類以上の気体を含む雰囲気中
でレーザー光や電子ビーム等のエネルギービームを照射
することによりシリコン半導体を部分的に溶融あるいは
半溶融状態としシリコン半導体表面に雰囲気ガス中の酸
素あるいは窒素との表面反応を起こし酸化シリコン薄膜
あるいは窒化シリコン薄膜を形成する。本発明により形
成される絶縁膜はシリコン半導体の溶融時間が熱酸化法
等に比べ短いために極表面部のみに形成されるが、絶縁
膜の膜質としては界面準位やピンホールの少ない良質な
絶縁膜が形成可能である。Action A silicon semiconductor is irradiated with an energy beam such as a laser beam or an electron beam in an atmosphere containing at least one type of gas containing oxygen, an oxygen compound, water vapor or nitrogen as a constituent element. As a result, the silicon semiconductor is partially melted or semi-molten to cause a surface reaction with oxygen or nitrogen in the atmosphere gas to form a silicon oxide thin film or a silicon nitride thin film on the surface of the silicon semiconductor. The insulating film formed by the present invention is formed only on the extreme surface portion because the melting time of the silicon semiconductor is shorter than that of the thermal oxidation method or the like, but the film quality of the insulating film is high quality with few interface states and pinholes. An insulating film can be formed.
一般的にエネルギービームの照射によりシリコン半導
体が溶融する時間は非常に短時間に設定されるために、
基板へ熱が拡散され基板温度が上昇する前に冷却される
ため基板の温度上昇は少なく抑えられる。前記の特徴に
より基板の耐熱性の問題で従来の熱酸化法を用いること
ができなかった基板材料、例えば低融点ガラス基板等へ
の応用が可能となる。Generally, the time for melting a silicon semiconductor by irradiation with an energy beam is set to a very short time,
Since the heat is diffused to the substrate and cooled before the substrate temperature rises, the temperature rise of the substrate can be suppressed to a small level. Due to the above characteristics, it is possible to apply to a substrate material for which a conventional thermal oxidation method could not be used due to the heat resistance of the substrate, such as a low melting point glass substrate.
また、本発明の製造方法により形成した絶縁膜は、ピ
ンホールが少ないために薄膜トランジスタのゲート絶縁
膜として用いた場合絶縁不良を起こす確率が少なく、か
つ極薄膜のため静電容量が大きく薄膜トランジスタのON
電流を大きくする事が可能である。しかも活性層とゲー
ト絶縁膜の界面での準位密度が少ないために信頼性の向
上が図られる。In addition, the insulating film formed by the manufacturing method of the present invention has few pinholes, and thus has a low probability of causing insulation failure when used as a gate insulating film of a thin film transistor, and has a large electrostatic capacitance because it is an ultrathin film.
It is possible to increase the current. Moreover, since the level density at the interface between the active layer and the gate insulating film is small, the reliability can be improved.
さらに、本発明の製造方法を用いたゲート絶縁膜上に
さらに同種あるいは異種の第２の絶縁膜を形成する事に
より、第１層の絶縁膜の絶縁不良の確率が小さいため第
２層目の絶縁膜の膜厚を薄くする事が可能となり、ゲー
ト絶縁膜の耐圧を制御しつつゲート絶縁膜の容量を増大
させON電流の増大を図る事が可能である。Further, by forming a second insulating film of the same kind or different kind on the gate insulating film using the manufacturing method of the present invention, the probability of insulation failure of the insulating film of the first layer is small, so that the second insulating film of the second layer is formed. It is possible to reduce the thickness of the insulating film, and it is possible to increase the ON current by increasing the capacitance of the gate insulating film while controlling the breakdown voltage of the gate insulating film.
上記のように本発明の製造方法を用いることにより、
電気的特性に優れた絶縁膜を低温で形成することが可能
である。By using the production method of the present invention as described above,
It is possible to form an insulating film having excellent electrical characteristics at low temperature.
実施例 以下に本発明の実施例を図面を基に説明する。Embodiments Embodiments of the present invention will be described below with reference to the drawings.
第１図は本発明の絶縁膜の製造方法を用いた薄膜トラ
ンジスタの実施例の一例である。第１図（ａ）に示した
ようにガラス基板１上に非晶質半導体薄膜２が形成され
ており、前記基板に対してN2Oガスを含む雰囲気中にお
いてエネルギービーム（ここではレーザー光）の照射を
行う。第１図（ａ）の状態でのエネルギービーム照射に
よって非晶質半導体薄膜２は部分的に溶融あるいは半溶
融状態となり、雰囲気ガス中の酸素との表面反応を起こ
し非晶質半導体薄膜表面に酸化シリコン膜３を形成す
る。また、同時に非晶質半導体薄膜はエネルギービーム
の照射により結晶化し多結晶半導体薄膜となる。次いで
第１図（ｂ）に示すように多結晶半導体薄膜を減圧CVD
法等により形成しゲート電極４を形成する。第１図
（ｃ）に示すようにゲート電極４をマスクとして自己整
合（セルフアライン）によりソース、ドレイン電極形成
のための不純物（第１図（ｄ）ではＰ）をイオン注入に
より導入する。第１図（ｄ）に示すように注入イオンの
活性化を行った後、トランジスタ部以外の半導体層をエ
ッチング除去しバッシベーションSio2膜５を形成する。
最後に第１図（ｅ）に示すようにソース、ドレイン領域
のｎ形低抵抗領域７上の絶縁膜をエッチング除去しソー
ス、ドレイン電極８を形成する。FIG. 1 is an example of an embodiment of a thin film transistor using the method for manufacturing an insulating film of the present invention. As shown in FIG. 1A, an amorphous semiconductor thin film 2 is formed on a glass substrate 1, and an energy beam (here, a laser beam) is applied to the substrate in an atmosphere containing N 2 O gas. Irradiation. The amorphous semiconductor thin film 2 is partially melted or semi-molten by the energy beam irradiation in the state of FIG. A silicon film 3 is formed. At the same time, the amorphous semiconductor thin film is crystallized by irradiation with an energy beam to become a polycrystalline semiconductor thin film. Then, as shown in FIG. 1 (b), the polycrystalline semiconductor thin film is subjected to low pressure CVD.
The gate electrode 4 is formed by the method or the like. As shown in FIG. 1C, impurities (P in FIG. 1D) for forming source and drain electrodes are introduced by ion implantation by self-alignment using the gate electrode 4 as a mask. After activating the implanted ions as shown in FIG. 1D, the semiconductor layer other than the transistor portion is removed by etching to form a passivation Sio 2 film 5.
Finally, as shown in FIG. 1E, the insulating film on the n-type low resistance region 7 in the source and drain regions is removed by etching to form the source and drain electrodes 8.
本発明の絶縁膜の製造方法を用いて薄膜トランジスタ
を作成したところ、酸化シリコン薄膜がガラス基板上に
低温で形成でき、かつゲート絶縁膜とシリコン半導体界
面でのトラップ準位が減少し信頼性が向上した。また、
ゲート絶縁膜の静電容量が増大したことによりトランジ
スタのON電流が向上した。When a thin film transistor was produced using the method for producing an insulating film of the present invention, a silicon oxide thin film could be formed on a glass substrate at a low temperature, and the trap level at the interface between the gate insulating film and the silicon semiconductor was reduced to improve reliability. did. Also,
The increase in the capacitance of the gate insulating film improved the ON current of the transistor.
第２図に本発明の薄膜トランジスタの製造方法の一例
を示す。FIG. 2 shows an example of a method of manufacturing the thin film transistor of the present invention.
基本的なトランジスタの構成は第１図に記載の物と同
一であり図中の番号も第１図と対応している。第１図と
異なる点は第２図（ｂ）においてエネルギービームの照
射により形成した酸化シリコン膜３上に窒化シリコン膜
３′をプラズマCVD法により形成し２層ゲート絶縁膜を
形成した後に多結晶シリコンを堆積しゲート電極を形成
する点にある。エネルギービームの照射により形成され
る酸化シリコン膜の膜厚は非晶質シリコンの薄膜の溶融
時間により制御されるが、一般的にガラス基板が使用可
能な条件では下地ガラス基板への熱伝導を防止するた
め、溶融時間は短時間に限定され酸化シリコン膜厚も限
定される。従って、本実施例中に示した２層絶縁膜構成
を用いることにより、多結晶シリコンと酸化シリコンと
の界面は熱酸化時に得られるものと同等の良好な界面を
維持しつつ、第二の絶縁膜により十分な絶縁耐圧を得る
ことが可能となった。The basic structure of the transistor is the same as that shown in FIG. 1, and the numbers in the figure correspond to those in FIG. The difference from FIG. 1 is that in FIG. 2 (b), a silicon nitride film 3'is formed by plasma CVD on the silicon oxide film 3 formed by irradiation of an energy beam to form a two-layer gate insulating film, and then a polycrystalline film is formed. The point is to deposit silicon to form a gate electrode. The film thickness of the silicon oxide film formed by the irradiation of the energy beam is controlled by the melting time of the amorphous silicon thin film, but generally heat transfer to the underlying glass substrate is prevented under the condition that the glass substrate can be used. Therefore, the melting time is limited to a short time and the silicon oxide film thickness is also limited. Therefore, by using the two-layer insulation film structure shown in the present embodiment, the interface between the polycrystalline silicon and the silicon oxide maintains a good interface equivalent to that obtained at the time of thermal oxidation, while maintaining the second insulation. The film made it possible to obtain a sufficient withstand voltage.
本発明の製造方法を用いた薄膜トランジスタを作成し
たところ従来の酸化シリコンあるいは窒化シリコン単層
で形成したゲート絶縁膜に比べ、第１層の酸化シリコン
膜のピンホール密度が小さいために第２層目の絶縁膜の
膜厚を薄くしても絶縁不良の確率が少なくなる。従っ
て、ゲート絶縁膜の絶縁耐圧を向上させつつ従来の単層
ゲート絶縁膜に比べゲート絶縁膜の静電容量を向上させ
ることができ、トランジスタのON電流を向上させること
が可能となった。When a thin film transistor is manufactured using the manufacturing method of the present invention, the pinhole density of the silicon oxide film of the first layer is smaller than that of the conventional gate insulating film formed of a silicon oxide or silicon nitride single layer. Even if the thickness of the insulating film is reduced, the probability of defective insulation is reduced. Therefore, it is possible to improve the withstand voltage of the gate insulating film and improve the capacitance of the gate insulating film as compared with the conventional single-layer gate insulating film, and it is possible to improve the ON current of the transistor.
発明の効果 上記のように本発明によれば、半導体薄膜の表面に低
温で良質な絶縁膜を形成することが可能である。また、
絶縁膜の形成と同時に半導体薄膜の改質を同時に行うこ
とが出来る。前記特徴を用いて薄膜トランジスタを作成
することにより半導体層とゲート絶縁膜界面におけるト
ラップ等の欠陥の少ない良好な界面が形成できトランジ
スタ特性が向上し、かつ信頼性の向上が図られた。Effects of the Invention As described above, according to the present invention, it is possible to form a good-quality insulating film on the surface of a semiconductor thin film at low temperature. Also,
The semiconductor thin film can be simultaneously modified with the formation of the insulating film. By forming a thin film transistor using the above characteristics, a favorable interface with few defects such as traps at the interface between the semiconductor layer and the gate insulating film can be formed, and the transistor characteristics are improved and the reliability is improved.
本発明を薄膜トランジスタ等に応用することにより機
能素子の高性能化及び高集積化が可能である。By applying the present invention to a thin film transistor or the like, high performance and high integration of functional elements can be achieved.
なお、本発明の実施例には記載していないが、窒素を
構成元素として含む反応性雰囲気中においてエネルギー
ビームの照射を行うことにより窒化シリコン膜を形成す
ることもでき同様の効果が期待できる。また、シリコン
以外の半導体に関しても応用可能である。Although not described in the examples of the present invention, a silicon nitride film can be formed by irradiating an energy beam in a reactive atmosphere containing nitrogen as a constituent element, and the same effect can be expected. Further, it can be applied to semiconductors other than silicon.
第１図は本発明の一実施例である絶縁膜の製造方法を用
いた薄膜トランジスタの製造方法の工程図、第２図は他
の実施例の工程図である。 １……透光性基板（ガラス基板）、２……非晶質半導体
薄膜（非晶質シリコン）、３……ゲート絶縁膜（Si
o2）、３′……第２のゲート絶縁膜（SiNx）、４……ゲ
ート電極、５……パッシベーション膜、６……ソース及
びドレイン電極、７……ｎ形低抵抗領域（Ｐドープ領
域）。FIG. 1 is a process drawing of a method of manufacturing a thin film transistor using an insulating film manufacturing method which is an embodiment of the present invention, and FIG. 2 is a process drawing of another embodiment. 1 ... Translucent substrate (glass substrate), 2 ... Amorphous semiconductor thin film (amorphous silicon), 3 ... Gate insulating film (Si
o 2 ), 3 '... second gate insulating film (SiNx), 4 ... gate electrode, 5 ... passivation film, 6 ... source and drain electrode, 7 ... n-type low resistance region (P-doped region) ).
Claims (5)
晶半導体薄膜を形成する工程と、前記半導体薄膜に対し
酸素、酸素化合物、水蒸気のうち少なくとも一種類以上
のガスを含む雰囲気中に於てエネルギービームの照射を
行い酸化珪素膜を形成する工程と、前記酸化珪素膜上に
ゲート電極を形成する工程と、前記酸化珪素膜を選択的
に除去して一対のソース、ドレイン電極を形成する工程
から少なくとも成る薄膜トランジスタの製造方法。1. A step of forming a non-single-crystal semiconductor thin film containing at least silicon on a substrate, and an atmosphere containing at least one gas selected from oxygen, oxygen compounds and water vapor with respect to the semiconductor thin film. A step of forming a silicon oxide film by irradiation with an energy beam, a step of forming a gate electrode on the silicon oxide film, and a step of selectively removing the silicon oxide film to form a pair of source and drain electrodes. And a method of manufacturing a thin film transistor.
晶半導体薄膜を形成する工程と、前記半導体薄膜に対し
酸素、酸素化合物、水蒸気のうち少なくとも一種類以上
のガスを含む雰囲気中に於てエネルギービームの照射を
行い酸化珪素膜を形成する工程と、前記絶縁膜上に第２
酸化珪素膜を形成する工程を有することを特徴とする薄
膜トランジスタの製造方法。2. A step of forming a non-single crystal semiconductor thin film containing at least silicon on a substrate, and an atmosphere containing at least one gas selected from oxygen, oxygen compounds and water vapor with respect to the semiconductor thin film. A step of forming a silicon oxide film by irradiating an energy beam, and a second step on the insulating film.
A method of manufacturing a thin film transistor, comprising the step of forming a silicon oxide film.
膜を用いることを特徴とする請求項２記載の薄膜トラン
ジスタの製造方法。3. The method of manufacturing a thin film transistor according to claim 2, wherein a silicon oxide film or a silicon nitride film is used as the insulating film.
の非晶質珪素薄膜を用い、エネルギービームの照射によ
り形成する酸化シリコン薄膜の膜厚を100nm以下とする
ことを特徴とする請求項１、２または３記載の薄膜トラ
ンジスタの製造方法。4. An amorphous silicon thin film having a thickness of 150 nm or less is used as the non-single-crystal semiconductor thin film, and a silicon oxide thin film formed by irradiation with an energy beam has a thickness of 100 nm or less. 2. The method for manufacturing a thin film transistor according to 2 or 3.
てN2Oガスを用いることを特徴とする請求項１、２、３
または４記載の薄膜トランジスタの製造方法。5. An N 2 O gas is used as an atmospheric gas during the energy beam irradiation.
Alternatively, the method for manufacturing a thin film transistor according to the item 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12847690A JP2502789B2 (en) | 1990-05-17 | 1990-05-17 | Method for manufacturing thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12847690A JP2502789B2 (en) | 1990-05-17 | 1990-05-17 | Method for manufacturing thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0422127A JPH0422127A (en) | 1992-01-27 |
| JP2502789B2 true JP2502789B2 (en) | 1996-05-29 |
Family
ID=14985681
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12847690A Expired - Fee Related JP2502789B2 (en) | 1990-05-17 | 1990-05-17 | Method for manufacturing thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2502789B2 (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7097712B1 (en) | 1992-12-04 | 2006-08-29 | Semiconductor Energy Laboratory Co., Ltd. | Apparatus for processing a semiconductor |
| US5663077A (en) | 1993-07-27 | 1997-09-02 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a thin film transistor in which the gate insulator comprises two oxide films |
| JPH0766426A (en) * | 1993-08-27 | 1995-03-10 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its forming method |
| JPH0794756A (en) * | 1993-07-27 | 1995-04-07 | Semiconductor Energy Lab Co Ltd | Method of fabricating semiconductor device |
| JP3417072B2 (en) * | 1994-08-15 | 2003-06-16 | ソニー株式会社 | Semiconductor device manufacturing method |
| US5587330A (en) * | 1994-10-20 | 1996-12-24 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
| WO2004017396A1 (en) * | 2002-08-14 | 2004-02-26 | Tokyo Electron Limited | Method of forming insulation film on semiconductor substrate |
| JP2004140329A (en) | 2002-08-19 | 2004-05-13 | Seiko Epson Corp | Substrate device, its manufacturing method, electrooptical device, and electronic apparatus |
| JP3791517B2 (en) | 2002-10-31 | 2006-06-28 | セイコーエプソン株式会社 | Electro-optical device and electronic apparatus |
| JP2007025611A (en) * | 2005-06-17 | 2007-02-01 | Seiko Epson Corp | Electro-optical device, method of manufacturing the same, and electronic apparatus |
| KR101610260B1 (en) * | 2008-12-15 | 2016-04-08 | 삼성전자주식회사 | Electron beam anneling apparatus and annealing method using the same |
-
1990
- 1990-05-17 JP JP12847690A patent/JP2502789B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0422127A (en) | 1992-01-27 |
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