JPS5984922U - Chip-shaped piezoelectric oscillator - Google Patents

Chip-shaped piezoelectric oscillator

Info

Publication number
JPS5984922U
JPS5984922U JP18131882U JP18131882U JPS5984922U JP S5984922 U JPS5984922 U JP S5984922U JP 18131882 U JP18131882 U JP 18131882U JP 18131882 U JP18131882 U JP 18131882U JP S5984922 U JPS5984922 U JP S5984922U
Authority
JP
Japan
Prior art keywords
electrodes
piezoelectric
chip
piezoelectric oscillator
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18131882U
Other languages
Japanese (ja)
Other versions
JPH0115229Y2 (en
Inventor
隆 山本
Original Assignee
株式会社村田製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社村田製作所 filed Critical 株式会社村田製作所
Priority to JP18131882U priority Critical patent/JPS5984922U/en
Publication of JPS5984922U publication Critical patent/JPS5984922U/en
Application granted granted Critical
Publication of JPH0115229Y2 publication Critical patent/JPH0115229Y2/ja
Granted legal-status Critical Current

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  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第2図は夫々従来の圧電発振子の圧電基板
の平面図および縦断面図、第3図は本考案に係る圧電発
振子の横断面図、第4図は第3図、の圧電発振子の圧電
基板の平面図、第5図はサポート基板の入力電極、出力
電極およびアース電極の形成面の平面図、第6図は第3
図の圧電発振子の斜視図、第7図は発振回路の回路図、
第8図、第9図および第10図は夫々第3図の圧電発振
子によるデュアルインライン形の圧電発振子の製造工程
の説明図である。 11−・・圧電基板(11a、  1 lb−・・主面
)、12゜13−1ポート基板(12a、  12b、
  13a−・・主面)、14・・・接着剤、15.1
6・・・外部電極、17.18・・・電極、19.20
・・・引出し電極、21.22・・・空間、31・・・
入力電極、32・・・出力電極、33・・・アース電極
1 and 2 are a plan view and a vertical cross-sectional view of a piezoelectric substrate of a conventional piezoelectric oscillator, respectively, FIG. 3 is a cross-sectional view of a piezoelectric oscillator according to the present invention, and FIG. FIG. 5 is a plan view of the piezoelectric substrate of the piezoelectric oscillator, FIG.
Figure 7 is a perspective view of the piezoelectric oscillator, Figure 7 is a circuit diagram of the oscillation circuit,
FIGS. 8, 9, and 10 are explanatory diagrams of the manufacturing process of a dual in-line type piezoelectric oscillator using the piezoelectric oscillator of FIG. 3, respectively. 11-...Piezoelectric board (11a, 1 lb-...main surface), 12゜13-1 Port board (12a, 12b,
13a--principal surface), 14--adhesive, 15.1
6... External electrode, 17.18... Electrode, 19.20
...Extraction electrode, 21.22...Space, 31...
Input electrode, 32... Output electrode, 33... Earth electrode.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 上下両主面に電極を形成してなる圧電基板のエネルギー
閉じ込め型厚み振動を用いた圧電発振子であって、上記
圧電基板に振動を許容する空間を残して少くとも一方が
誘電体からなる2枚のサポート基板をその一つの主面を
圧電基板の上記両生面に対向させて絶縁性の接着剤で夫
々接着し゛、誘電体からなる上記サポート基板のいま一
つの主面に入力電極と出力電極とを形成するとともに、
これら入力電極と出力電極との間にアース電極を形成し
、上記入力電極および出力電極を夫々上記圧、 型基板
およびサポート基板の端面に形成した外部電極で圧電基
板の上記電極から引き出した引出し電極に夫々導通され
るようにしたことを特徴とするチップ状圧電発振子。
A piezoelectric oscillator using energy-trapped thickness vibration of a piezoelectric substrate having electrodes formed on both upper and lower main surfaces, the piezoelectric substrate having at least one side made of a dielectric material, leaving a space for allowing vibration. Two support substrates are bonded with an insulating adhesive with one main surface facing the above-mentioned bidirectional surface of the piezoelectric substrate, and an input electrode and an output electrode are attached to the other main surface of the support substrate made of a dielectric material. In addition to forming the
A ground electrode is formed between these input electrodes and output electrodes, and external electrodes are formed on the end faces of the piezoelectric substrate and the support substrate to connect the input and output electrodes, respectively. A chip-shaped piezoelectric oscillator characterized in that each of the chip-shaped piezoelectric oscillators is electrically conductive.
JP18131882U 1982-11-29 1982-11-29 Chip-shaped piezoelectric oscillator Granted JPS5984922U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18131882U JPS5984922U (en) 1982-11-29 1982-11-29 Chip-shaped piezoelectric oscillator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18131882U JPS5984922U (en) 1982-11-29 1982-11-29 Chip-shaped piezoelectric oscillator

Publications (2)

Publication Number Publication Date
JPS5984922U true JPS5984922U (en) 1984-06-08
JPH0115229Y2 JPH0115229Y2 (en) 1989-05-08

Family

ID=30392931

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18131882U Granted JPS5984922U (en) 1982-11-29 1982-11-29 Chip-shaped piezoelectric oscillator

Country Status (1)

Country Link
JP (1) JPS5984922U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6461111A (en) * 1987-08-31 1989-03-08 Sumitomo Metal Ind Composite parts comprising piezoelectric resonator and capacitor
JPH0390123U (en) * 1989-12-27 1991-09-13

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6461111A (en) * 1987-08-31 1989-03-08 Sumitomo Metal Ind Composite parts comprising piezoelectric resonator and capacitor
JPH0390123U (en) * 1989-12-27 1991-09-13

Also Published As

Publication number Publication date
JPH0115229Y2 (en) 1989-05-08

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