JPS5984551A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5984551A
JPS5984551A JP57195476A JP19547682A JPS5984551A JP S5984551 A JPS5984551 A JP S5984551A JP 57195476 A JP57195476 A JP 57195476A JP 19547682 A JP19547682 A JP 19547682A JP S5984551 A JPS5984551 A JP S5984551A
Authority
JP
Japan
Prior art keywords
wiring
layer
semiconductor device
insulating film
stepped
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57195476A
Other languages
Japanese (ja)
Other versions
JPS6362105B2 (en
Inventor
Tsutomu Matsuura
松浦　勉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57195476A priority Critical patent/JPS5984551A/en
Publication of JPS5984551A publication Critical patent/JPS5984551A/en
Publication of JPS6362105B2 publication Critical patent/JPS6362105B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To obtain the semiconductor device, the degree of freedom of a wiring therein is large, which fits to a miniaturization and a simplification, reliability thereof is excellent and which has three layers or moe of the wiring, by forming the inter-layer connecting wiring and/or the outgoing wiring to an insulating film section formed to a stepped shape. CONSTITUTION:The end sections of inter-layer insulating films 1-4 are formed to the stepped shape, and the end section of the first layer metallic wiring 11 and the end section of the third layer metallic wiring 13 are exposed, and formed to the stepped shape together with other insulating films 2, 4, and the first layer metallic wiring 11 and the third metallic wiring 13 are connected directly by the metallic wiring 20. The first layer metallic wiring 11 and the fourth layer metallic wiring 14 are connected directly by the side surface wiring 31, and the second layer metallic wiring 12 and the fourth layer metallic wiring 14 are connected directly by the side surface wiring 32. Stepped differences are reduced because the insulating films are formed to the stepped shape, the reliability of the wirings can be improved, the degree of freedom of a design is large because the wirings of separate layers can be connected directly, and the semiconductor device can be miniaturized.

Description

【発明の詳細な説明】 本発明は半導体装置にかかり、特に３層以上の多層配線
を有する半導体装置において、配線構造を改良し配線の
多様化と信頼性の向上をばかった半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device having multilayer wiring of three or more layers, in which the wiring structure is improved to allow for diversification of wiring and improvement in reliability.

従来、半導体装置の多層配線は通常スルホール式を設は
一層二層と１１次電気的接絞をとって行く方法がとられ
ている。＃、１図は従来の多層配線構造を有する半導体
装置の要部断面図である。図において第１層の絶縁膜１
の上に第１層の金属配線１１が形成され、次いで第２層
の絶縁膜２により金属配線１１を覆（・絶縁する。しか
るのち金、に配線に達するスルホールをあけ、第２層目
の金属配線１２を形成する。以下同様の方法で第３１※
の絶縁膜３、第３層の金属配線１３が形成される。Conventionally, the multilayer wiring of semiconductor devices has generally been formed using a through-hole type, or one layer and two layers, and an 11th-order electrical junction. #, Figure 1 is a sectional view of a main part of a semiconductor device having a conventional multilayer wiring structure. In the figure, the first layer of insulating film 1
A first layer of metal wiring 11 is formed thereon, and then a second layer of insulating film 2 covers (and insulates) the metal wiring 11. Then, a through hole is made in the gold layer to reach the wiring, and a second layer of insulation film 2 is formed to cover (and insulate) the metal wiring 11. Form the metal wiring 12.The 31st* metal wiring is formed in the same manner.
An insulating film 3 and a third layer of metal wiring 13 are formed.

以上のように従来の構造はスルホールを介して順次絶縁
膜と金属配線を重ねて行くため、第１に製造工程が複雑
で、第２に配線長が長くなり配線が捨雑で小型化に適さ
な（・。第３としてスルホール形成はこの部分における
信頼性の面からも多くの問題を含んでいる。As mentioned above, in the conventional structure, the insulating film and metal wiring are sequentially stacked via through-holes, which firstly complicates the manufacturing process, and secondly, the wiring length becomes long and the wiring is untidy, making it unsuitable for miniaturization. Thirdly, throughhole formation involves many problems from the aspect of reliability in this part.

また、１１１次接続して行くことから第１層と第３層を
接続する場合においても必らず２層を経由するという不
都合があった。Further, since the 111th connection is made, there is an inconvenience that even when connecting the first layer and the third layer, the connection must go through the second layer.

それに加え多層化と共に絶縁膜が厚くなることから配線
における段差問題が発生し信頼性を著しく低下させてい
た。In addition, as the insulating film becomes thicker with multilayering, the problem of level differences in wiring occurs, significantly reducing reliability.

本発明は以上の問題点に対処してなされたもので、配線
の自由度が大きく、・小型化、簡易化に適し、信頼性の
優れた改良された３層以上の配線を有する半導体装置を
提供するにある。The present invention has been made to address the above problems, and provides a semiconductor device having improved wiring of three or more layers, which has a large degree of freedom in wiring, is suitable for miniaturization and simplification, and has excellent reliability. It is on offer.

本発明の要旨は、３層以上の配線構造を有する半導体装
置において、絶縁膜を階段状に形成した階段状絶縁膜部
と、該階段状絶縁膜部に形成された層間接続配線及び又
は引き出し配線とを含むことを特徴とする半導体装置に
ある。The gist of the present invention is to provide a semiconductor device having a wiring structure of three or more layers, including a step-like insulating film portion in which an insulating film is formed in a step-like manner, and an interlayer connection wiring and/or lead-out wiring formed in the step-like insulating film portion. A semiconductor device comprising:

以下実施例を参照し本発明を説明する。The present invention will be explained below with reference to Examples.

第２図は本発明の一実施例による半導体装置の断面図で
ある。図において１〜４は絶縁膜、１１〜１４は金属配
線で第１図に準じ隣接する金属配線は図面には表示され
ていた（・が必要によりスルホールで接続されて（・る
。第２図では層間絶縁膜の端部が階段状に形成されてお
り、また第１層の金属配線１１の端部及び第３層の金属
配線１３の端部が露出し、他の絶縁膜と共に階段状に形
成されて（・る。図にお（・て２０は金属配線で、この
金属配線２０により第１層金属配線１１と第３の金属配
線１３は直接接続されている。すなわち従来のようにス
ルホールを通じ一層一層接続するのでなく直接接続され
るので構成は簡素化され設計の自由度の増大と小型化に
有効である。しかも側面は階段状に形成されているので
一段の段差は小さく。FIG. 2 is a sectional view of a semiconductor device according to an embodiment of the present invention. In the figure, 1 to 4 are insulating films, and 11 to 14 are metal wires.Adjacent metal wires are shown in the drawing as in FIG. In this case, the end of the interlayer insulating film is formed in a step-like shape, and the end of the first-layer metal wiring 11 and the end of the third-layer metal wiring 13 are exposed, forming a step-like shape together with other insulating films. In the figure, 20 is a metal wiring, and the first layer metal wiring 11 and the third metal wiring 13 are directly connected by this metal wiring 20. In other words, unlike the conventional through-hole Since they are directly connected instead of being connected layer by layer, the configuration is simplified and is effective for increasing the degree of design freedom and downsizing.Furthermore, since the sides are formed in a step-like shape, the difference in step is small.

なり、従来最も問題であった段差部における配線の断線
問題は大幅に改良することができる。Therefore, the problem of disconnection of wiring at the stepped portion, which has been the most problematic problem in the past, can be significantly improved.

第３図は本発明をより詳細に説明するための一実施例の
概略斜視図である。図において１〜５に′！。FIG. 3 is a schematic perspective view of an embodiment for explaining the present invention in more detail. In the figure, 1 to 5'! .

それぞれ第１〜第５層の絶縁膜、１１は第１層金属配線
、１２は第２層、１３は第３層、１４は第４層の金属配
線をそれぞれ示ず。側面配線３１は第１層金属配線１１
と第４層金属配線１４を直接接続して（・る。また側面
配線３２は第２層金属配線１２と第４層の金属配線１４
を接続している。The insulating films of the first to fifth layers, 11 the first layer metal wiring, 12 the second layer, 13 the third layer, and 14 the fourth layer metal wiring are not shown. The side wiring 31 is the first layer metal wiring 11
The side wiring 32 is connected directly to the fourth layer metal wiring 14 and to the second layer metal wiring 12.
are connected.

また側面配線３３は第２Ｍと同様に第１１１膚金属配線
１１と第３層金属配線１３が階段状の絶縁膜を経由して
接続されている。また側面配線３４は第４＠の金属配線
１４と第３層の金属配線１３を接続しているが、他の配
線３５が中間に存在することと、上下方向が合って（・
な（・ので、段差部に横方向配線を設けることにより迂
回して接続して（・る。また側面配線３５も横方向配線
を施すことにより金属配線１２と１４の間を接続してい
る。Further, in the side wiring 33, the 111th metal wiring 11 and the third layer metal wiring 13 are connected via a stepped insulating film, similar to the second M wiring. Also, the side wiring 34 connects the fourth @ metal wiring 14 and the third layer metal wiring 13, but the other wiring 35 is present in the middle and the vertical direction is aligned (・
Therefore, horizontal wiring is provided at the stepped portion to connect in a detour (.) Also, the side wiring 35 is also provided with horizontal wiring to connect the metal wirings 12 and 14.

以上説明したように本実施例によれば周辺部の絶縁膜を
階段状に形成し、この部分にて多層配線における配線を
行えば例えば１層と３層のように離れた層の配線が直接
接続でき、また側面は階段状に１工っ゛〔（・るので、
従来の配線をより簡易化でき、設計の自由度が増大し、
小型化と信頼性の向上が達成できる。As explained above, according to this embodiment, the insulating film in the peripheral area is formed in a step-like manner, and if wiring in multilayer wiring is performed in this area, wiring in distant layers, such as the first and third layers, can be directly connected. It can be connected, and the sides are shaped like steps.
Conventional wiring can be simplified, increasing the degree of freedom in design,
Miniaturization and improved reliability can be achieved.

第４図は本発明の他の実施例による半導体装置の概略斜
視図である。図において１〜４は絶縁膜、１１及び１３
はそれぞれ第１層金属配線、第３層金属配線で、これが
側面配線４０により接続されて（・る。本実施例の特徴
は配線を施す階段部がベレットの周辺部でなく、ペレッ
トの内部に設けられていることであり、本実施例におい
ても周辺部に設けた場合と同様な効果が得られる。FIG. 4 is a schematic perspective view of a semiconductor device according to another embodiment of the present invention. In the figure, 1 to 4 are insulating films, 11 and 13
are the first layer metal wiring and the third layer metal wiring, respectively, which are connected by the side wiring 40.The feature of this embodiment is that the staircase part where the wiring is applied is not on the periphery of the pellet, but inside the pellet. In this embodiment, the same effect as when provided in the peripheral area can be obtained.

第５図は本発明の他の実施例による半導体装置の断面図
である。図において３０は電極配線、３０′は電極配線
を外部に引き出すための側面配線であり、３０”は第１
層の絶縁膜上に形成されたポンディングパッドである。FIG. 5 is a sectional view of a semiconductor device according to another embodiment of the present invention. In the figure, 30 is the electrode wiring, 30' is the side wiring for drawing the electrode wiring to the outside, and 30'' is the first
A bonding pad formed on an insulating film of a layer.

従来、多層配線を有する半導体装置の配線は最上層に引
き出され、そこに電極並びに外部リードへ接続のための
ポンディングパッドが設けられている。しかし多層配線
の場合、通常配線にはアルミニウムが用いられるので２
層以上の層間絶縁膜の形成はアルミニウムの融点に左右
され、高温形成することができず、普通は低温ＣＶＤ法
によるシリコン酸化膜、シリコン窒化膜が用いられる。Conventionally, wiring in a semiconductor device having multilayer wiring is drawn out to the top layer, and bonding pads for connection to electrodes and external leads are provided there. However, in the case of multilayer wiring, aluminum is usually used for the wiring, so 2
The formation of an interlayer insulating film of more than one layer depends on the melting point of aluminum and cannot be formed at a high temperature, so a silicon oxide film or a silicon nitride film formed by low-temperature CVD is usually used.

従って層間絶縁層は機械的に弱いものとなっており、ま
たその境界面はより弱いものとなって（・る。Therefore, the interlayer insulating layer is mechanically weak, and its interface is even weaker.

従って多層配線を形成した半導体装置の最上層に形成し
たボンディングバットは機械的に弱く問題である。これ
に対し第５図に示した実施例では、電極配線３０は、そ
の近傍にポンディングパッドを設けることなく、側面が
階段状に形成された絶縁膜を超えて第１層絶縁膜１の上
にのび、そこにボンディングパ・ラドを形成している。Therefore, the bonding bat formed in the uppermost layer of a semiconductor device having multilayer wiring is mechanically weak, which is a problem. On the other hand, in the embodiment shown in FIG. 5, the electrode wiring 30 is placed on the first layer insulation film 1 beyond the insulation film whose side surface is formed into a stepped shape without providing a bonding pad in the vicinity thereof. It stretches out and forms a bonding pad there.

第１層の絶縁膜は通常熱酸化により形成したシリコン酸
化膜であるから低温ＣＶＤ形成の絶縁膜にくらべ緻密で
機械的強度も大きく配線の信頼性は勿論のことポンディ
ングパッドの特性向上を大幅に進めることが出来る。The first layer of insulating film is usually a silicon oxide film formed by thermal oxidation, so it is denser and has greater mechanical strength than an insulating film formed by low-temperature CVD, which not only improves the reliability of wiring but also greatly improves the characteristics of bonding pads. You can proceed to

第６図は本発明の他の実施例を示す半導体装置の断面図
である。図にお（・′ｃ１〜３は絶縁膜、４０は第１層
金属膜でＧＮＤラインである。４１は第２層金属配線で
信号ラインである。４２は第３層金属層、４３は第３層
金属層と第１層金属層を結ぶ側面接続金属層であるが、
側面は前記実施例と同様階段状になっているので良好な
接続を形成することができ、かつ自由な層の接続が可能
であるため信号ライン４１を容易にシールドすることが
でき、本発明の効果が顕著であることがわかる。FIG. 6 is a sectional view of a semiconductor device showing another embodiment of the present invention. In the figure (・'c1 to 3 are insulating films, 40 is a first layer metal film and a GND line, 41 is a second layer metal wiring and a signal line, 42 is a third layer metal layer, and 43 is a GND line). It is a side connection metal layer that connects the third metal layer and the first metal layer,
Since the side surfaces are stepped like in the previous embodiment, a good connection can be formed, and since free layer connections are possible, the signal line 41 can be easily shielded. It can be seen that the effect is significant.

以上説明したとおり本発明によれば、絶縁膜を階段状に
形成したため段差は小さくなりこの部分に形成した配線
の信頼度を向上させることができ、またこの部分で隣接
しない層の配線を接続することが出来、またこの階段部
を利用し横方向配線をすることも可能で、これにより迂
回配線もでき、またこの階段部を超えて外部へ配線を引
き出すことも容易になり、設計の自由度を大幅に増大さ
せることができ、それにより半導体装置の小型化、高信
頼化に対する寄与も非常に太き（・という効果がある。As explained above, according to the present invention, since the insulating film is formed in a step-like manner, the step difference becomes small and the reliability of the wiring formed in this part can be improved, and the wiring in non-adjacent layers can be connected in this part. It is also possible to use this stairway to run horizontal wiring, which allows for detour wiring, and also makes it easy to route wiring outside beyond this stairway, increasing flexibility in design. This has the effect of significantly increasing the size of semiconductor devices, thereby making a significant contribution to the miniaturization and increased reliability of semiconductor devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の多層配線構造を有する半導体装置の断面
図、第２図は本発明の一実施例による半導体装置の断面
図、第３図および第４図は何れも本発明の一実施例によ
る半導体装置の概略斜視図、第５図及び第６図は何れも
本発明の他の実施例による半導体装置の断面図である。 １・・・・・・第１層絶縁膜、２・・・・・・第２層絶
縁膜、３・・・・・・第３層絶縁膜、４・・・・・・第
４層絶縁膜、５・・・・・・第５層絶縁膜、１１・・・
・・・第１層金属配線、１２・・・第２層金属配線、１
３・・・・・・第３層金属配線、１４・・・・・・第４
層金属配線、２０，３１，３２．３３・・・・・・側面
配線、３４．３５・・・・・・迂回配線、３０・・・・
・・電極配線、３０′・・・・・・側面配線、３０１・
・・・・ポンディングバット、４０・・・・・・ＧＮＤ
金属層、４１・・・・・・信号ライン、４２・・・・・
・第３金属層、４３・・・・・・側面金属層。 第７図　　　　　　−へ〜２ ／′ ８３区 ８４区 第５図FIG. 1 is a sectional view of a semiconductor device having a conventional multilayer wiring structure, FIG. 2 is a sectional view of a semiconductor device according to an embodiment of the present invention, and FIGS. 3 and 4 are both embodiments of the present invention. A schematic perspective view of a semiconductor device according to the present invention, and FIGS. 5 and 6 are all sectional views of a semiconductor device according to other embodiments of the present invention. 1...First layer insulating film, 2...Second layer insulating film, 3...Third layer insulating film, 4...Fourth layer insulating film Film, 5...Fifth layer insulating film, 11...
...First layer metal wiring, 12...Second layer metal wiring, 1
3...Third layer metal wiring, 14...Fourth layer
Layer metal wiring, 20, 31, 32.33...Side wiring, 34.35...Detour wiring, 30...
...Electrode wiring, 30'...Side wiring, 301.
...Ponding bat, 40...GND
Metal layer, 41...Signal line, 42...
- Third metal layer, 43...Side metal layer. Figure 7 -To~2/' Ward 83, Ward 84 Figure 5

Claims (4)

【特許請求の範囲】[Claims] （１）三層以上の配線構造を有する半導体装置において
、絶縁膜を階段状に形成した階段状絶縁膜部と、該階段
状絶縁膜部に形成された層間接続配線及び又は引き出し
配線とを含むことを特徴とする半導体装置。(1) A semiconductor device having a wiring structure of three or more layers, including a stepped insulating film portion in which an insulating film is formed in a stepped manner, and interlayer connection wiring and/or lead-out wiring formed in the stepped insulating film portion. A semiconductor device characterized by: （２）階段状絶縁膜部の配線が横方向配線を含むことを
特徴とする特許請求の範囲第（１）項記載の半導体装置
。(2) The semiconductor device according to claim (1), wherein the wiring of the stepped insulating film portion includes lateral wiring. （３）三層以上の配Ｐ！松造を有する半導体装置の絶縁
膜上に形成された型棒配線が第１層の熱酸化膜上に引き
出されポンディングパッドが形成されていることを特徴
とする特許Ｈ古来の範囲第（１）項記載の半導体装Ｔ。(3) Three or more layers of distribution points! Patent H ancient range No. 1 (1), which is characterized in that a type rod wiring formed on an insulating film of a semiconductor device having a matsuzukuri is drawn out onto a first layer of thermal oxide film to form a bonding pad. ) The semiconductor device T described in item 1. （４）信号ラインの上下に絶縁膜を介して形成された金
属膜が側面の金属膜で接続され、信号ラインがシールド
されていることを特徴とする特許請求の範囲第（１）項
記載の半導体装置。(4) The metal film formed above and below the signal line via an insulating film is connected by the metal film on the side surface, and the signal line is shielded. Semiconductor equipment.
JP57195476A 1982-11-08 1982-11-08 Semiconductor device Granted JPS5984551A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57195476A JPS5984551A (en) 1982-11-08 1982-11-08 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57195476A JPS5984551A (en) 1982-11-08 1982-11-08 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5984551A true JPS5984551A (en) 1984-05-16
JPS6362105B2 JPS6362105B2 (en) 1988-12-01

Family

ID=16341714

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57195476A Granted JPS5984551A (en) 1982-11-08 1982-11-08 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5984551A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0382453A (en) * 1989-08-25 1991-04-08 Takara Belmont Co Ltd X-ray camera device
JPH03191948A (en) * 1989-12-20 1991-08-21 Tokyo Emitsukusu:Kk Panoramic x-ray photographing apparatus

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS494622U (en) * 1972-04-13 1974-01-15
JPS51127265U (en) * 1975-04-09 1976-10-14
JPS52131455A (en) * 1976-04-28 1977-11-04 Hitachi Ltd Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS494622U (en) * 1972-04-13 1974-01-15
JPS51127265U (en) * 1975-04-09 1976-10-14
JPS52131455A (en) * 1976-04-28 1977-11-04 Hitachi Ltd Semiconductor device

Also Published As

Publication number Publication date
JPS6362105B2 (en) 1988-12-01

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