JPS5978569A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5978569A JPS5978569A JP57188664A JP18866482A JPS5978569A JP S5978569 A JPS5978569 A JP S5978569A JP 57188664 A JP57188664 A JP 57188664A JP 18866482 A JP18866482 A JP 18866482A JP S5978569 A JPS5978569 A JP S5978569A
- Authority
- JP
- Japan
- Prior art keywords
- receiving element
- impurity
- ion
- implanted
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 239000012535 impurity Substances 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 abstract description 12
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 238000005468 ion implantation Methods 0.000 abstract description 5
- 230000035945 sensitivity Effects 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 241001137307 Cyprinodon variegatus Species 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical group [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 125000004437 phosphorous atom Chemical group 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/1443—Devices controlled by radiation with at least one potential jump or surface barrier
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Light Receiving Elements (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、受光素子とＭＯＳ型トランジスタを集積する
半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device that integrates a light receiving element and a MOS transistor.
受光素子はＩＬＫＤと対にし、機械的な変位を検出する
装置として非常に多くの分野で使用されている。しかし
、受光素子の出力が小さいため、制御信号等に用いるに
は、増巾回路が、又デジタル信号にするには、その回路
が必要となる。そこで受光素子と増巾等の回路を同一基
板上に形成した集積回路は、従来よりバイポーラＩＣ内
に受光素子を含むことによって作られている。しかし、
パイボーラエＣではＭＯ３工Ｃに較べて、消費電力が大
きい、動作電源電圧範囲が狭い、動作温度範囲が狭い、
雑音余裕度が小さい、集積度が低い等の欠点を有してい
る。近年、電子機器の小型・軽量・低消費電力化が急速
に進み、さらに工Ｃの動作速度と集積密度が高まるにつ
れ、消費電力が過大になり、熱設計が難かしくなってき
ている。The light receiving element is paired with an ILKD and is used in many fields as a device for detecting mechanical displacement. However, since the output of the light-receiving element is small, an amplification circuit is required to use it as a control signal, and an amplification circuit is required to convert it into a digital signal. Therefore, integrated circuits in which a light-receiving element and a circuit such as an amplifier are formed on the same substrate have conventionally been made by including the light-receiving element in a bipolar IC. but,
Compared to MO3C, Piborae C consumes more power, has a narrower operating power supply voltage range, and has a narrower operating temperature range.
It has drawbacks such as low noise margin and low degree of integration. In recent years, electronic devices have rapidly become smaller, lighter, and have lower power consumption, and as the operating speed and integration density of electronic devices have increased, power consumption has become excessive and thermal design has become difficult.
そのため、受光素子を含む集積回路においても、バイポ
ーラトランジスタによる回路では対応できなくなり回路
部のＣ！ＭＯ３化が必須となりつつある。又、受光素子
を含む集積回路は、機構部分に使用される頻度が多いた
め、電源電圧変動が大きく、温度変動も大きく、雑音が
高い等の悪環境化におかれる。この点においても、回路
部の０ＭＯ８化は、必須である。本発明は回路部をＭＯ
Ｓ型トランジスタで構成し、かかるバイポーラトランジ
スタによる受光素子を含む集積回路の欠点を除失したも
のである。Therefore, even in integrated circuits that include light-receiving elements, circuits using bipolar transistors cannot cope with the C! Converting to MO3 is becoming essential. Furthermore, since integrated circuits including light receiving elements are frequently used in mechanical parts, they are exposed to adverse environments such as large fluctuations in power supply voltage, large temperature fluctuations, and high noise. In this respect as well, it is essential to convert the circuit section to 0MO8. The present invention allows the circuit section to be
It is constructed of S-type transistors and eliminates the drawbacks of integrated circuits that include light-receiving elements using such bipolar transistors.
本発明は、受光素子とＭ ＯＳ型トランジスタを同一チ
ノブ内に集積し、且つ受光素子の能力をより高感度化し
た半導体装置を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device in which a light receiving element and a MOS transistor are integrated in the same chinobu, and the ability of the light receiving element is made more sensitive.
以下実施例に基づいて本発明の詳細な説明する。The present invention will be described in detail below based on examples.
まず従来のＣＭＯＳ Ｉ Ｏ製造プロセスを第１図に示
す。First, a conventional CMOS IO manufacturing process is shown in FIG.
α）同図Ａに於て、１０ρ・ｃｍ程度のｎ型Ｓ」ウェハ
ー１の全面にドナー不純物（リン原子）をイオン打込み
する ２゜
ｂ）同図Ｂに於て、Ｐ型ＷＥＬＬを形成するため、マス
クろを用いアクセプタ不純物（はう素原子）をイオン打
込みする ４゜
Ｃ）イオン打込みした不純物を活性化、さらにある程度
（ドナー不純物は１０μ毒程度、アクセブタ不純物では
８μｍ程度）の深さまでのＷＥＬＬを形成するため、ド
ライブインする。α) In Figure A, donor impurities (phosphorus atoms) are ion-implanted into the entire surface of the n-type S'' wafer 1 of approximately 10ρ cm. 2゜b) In Figure B, a P-type WELL is formed. Therefore, the acceptor impurity (boron atoms) is ion-implanted using a mask filter. 4°C) Activates the ion-implanted impurity, and then implants the implanted impurity to a certain depth (approximately 10 μm for donor impurities and approximately 8 μm for acceptor impurities). Drive-in to form WELL.
ｄ）以下、Ｐ型・ｎ型ストッパー形成 ＬＯＯＯ３酸化 ボリンリコン配線・ゲート形成 ｐ型不純物拡散 コンタクト穴形成 ＡＬ配線 保護膜形成 パッド穴形成 等のプロセスとなる。d) Below, P type/n type stopper formation LOOO3 oxidation Bolin Recon wiring/gate formation p-type impurity diffusion contact hole formation AL wiring Protective film formation pad hole formation etc. process.
次に、受光素子（フォトダイオード）を含むＣＭＯ８工
０製造プロセスを第２図に示す。Next, FIG. 2 shows a CMO 8-0 manufacturing process including a light receiving element (photodiode).
ｅ）同図Ａにおいて、後工程でつくられるｐ型ＷＥＬＬ
との接合で、最適なフォトダイオードとなる任意のη型
Ｓ１ウェハー（比抵抗５０Ω・ｃｍ程度）７に、マスク
６全用い選択的にＭＯ３工Ｃ部分のみに、ドナー不純物
をイオン打込みする ２゜
ｆ）同図Ｂに於て、ｐ型Ｗ Ｂ Ｌ Ｌを形成するため
、マスク３を用いアクセプタ不純物をイオン打込みする
４゜
この時、受光素子部５にもイオン打込み４し、ｐ −ｎ
接合フォトダイオードを形成する。e) In Figure A, the p-type WELL created in the subsequent process
Donor impurity is ion-implanted into an arbitrary η-type S1 wafer (resistivity of about 50 Ω cm) 7, which will become an optimal photodiode, using the entire mask 6 and selectively implanting donor impurities into only the MO3 process C part 2°. f) In the same figure B, in order to form p-type WBLL, acceptor impurity is ion-implanted using mask 3. 4゜At this time, ions are also implanted into light-receiving element part 5, and p-n
Form a junction photodiode.
７）イオン打込みした不純物を活性化、さらにある程度
以上の深さでＷＥＬＬが形成でき、かつフォトダイオー
ドが高感度化する接合深さとなるように、不純物をドラ
イブインする。7) Activate the ion-implanted impurity and drive in the impurity so that a WELL can be formed to a certain depth or more and the junction depth is such that the photodiode has high sensitivity.
フォトダイオードの接合深さは、入射する光の波長によ
り、波長が比較的短いときには接合深さを浅く、入射光
波長が比較的長いときには、接合深さを深くすることに
より、高感度化できる。これは、入射光波長が長いほど
、光の半導体への浸入する距離が深くなるためである。The junction depth of the photodiode depends on the wavelength of the incident light; when the wavelength of the incident light is relatively short, the junction depth is made shallow, and when the wavelength of the incident light is relatively long, the junction depth is made deep, thereby increasing the sensitivity. This is because the longer the wavelength of the incident light, the deeper the distance that the light penetrates into the semiconductor.
ｈ）以下、前記通常０Ｍ０８ＩＣ製造プロセスと同一。h) The following is the same as the above-mentioned normal 0M08IC manufacturing process.
この製造工程によりＭＯ３工Ｃ部分６は通常の製造工程
で作成される場合と、ＷＥＬＬ深さが異なるのみで、ト
ランジスタの特性上同一となり、工程も第１図Ａと第２
図Ａに示されるように、フォト工程が１回増加するだけ
である。又、フォトダイオード部分５については、最適
の接合深さ、最適の基板不純物濃度にすることができる
。さらに、第２図Ａに示されるように、ドナー不純物が
イオン打込みされないことにより、ドナー不純物のイオ
ン打込みによる基板表面の結晶格子の乱れをなくすこと
ができる。結晶格子が乱れると、乱れたンリコン原子が
、電子・正孔の再結合中心となり、少数キャリアのライ
フタイムが減少する。Through this manufacturing process, the MO3 workpiece C part 6 is the same in terms of transistor characteristics, with the only difference being the WELL depth, compared to when it is created through a normal manufacturing process.
As shown in Figure A, only one photo step is required. Further, for the photodiode portion 5, the optimum junction depth and substrate impurity concentration can be set to an optimum value. Furthermore, as shown in FIG. 2A, since the donor impurity is not ion-implanted, it is possible to eliminate disturbances in the crystal lattice on the substrate surface caused by the ion-implantation of the donor impurity. When the crystal lattice is disordered, the disordered phosphor atoms become centers for recombination of electrons and holes, reducing the lifetime of minority carriers.
すなわち、光入射によって生れた電子・正孔が、電流と
ならずに、半導体中で再結合してしまい、フォトダイオ
ードの効率の減少につながる。又、フォトダイオードの
ｐ型ＷＥＬ、Ｔ、部分に、余分なドナー不純物の存在を
、がなり少なく、すなわちもとの基板中に含まれる数だ
けにおさえられるため、ｐ型ＷＥＬＬ中の不純物濃度（
ドナ一原子子アクセフタ原子）を必要最少限にできる。In other words, electrons and holes generated by light incidence recombine in the semiconductor instead of becoming a current, leading to a decrease in the efficiency of the photodiode. In addition, since the presence of extra donor impurities in the p-type WELL, T, portion of the photodiode can be suppressed to a small number, that is, to the number contained in the original substrate, the impurity concentration in the p-type WELL (
(donor single atom, acceptor atom) can be minimized.
このことはキャリアの不純物散乱を最少限におさえるこ
とになり、キャリアの拡散長を長くできる。このことは
フォトダイオードの効率の増加につながる。This minimizes the impurity scattering of carriers and increases the carrier diffusion length. This leads to an increase in photodiode efficiency.
すなわち、受光素子部分にドナー不純物をイオン打込み
しないために、キャリアのライフタイム及び拡散長を長
くでき、フォトダイオードの高効率化が達成できる。That is, since donor impurities are not ion-implanted into the light-receiving element portion, carrier lifetime and diffusion length can be lengthened, and high efficiency of the photodiode can be achieved.
上記の例では、ｎ型基板ＬＯＣＯ３−３ｉゲートプロセ
スについて述べたが、同様にｐ型基板Ｌ○ｃ ｏ ｓ、
さらにブレチーＳ１ゲート、ＡＬアゲートロセスにも適
用できる。In the above example, the n-type substrate LOCO3-3i gate process was described, but the p-type substrate L○cos,
Furthermore, it can be applied to Bletchy S1 gate and AL agate process.
本発明は、受光素子とＭ ＯＳ 工Ｃを同一チノブ内に
構成することにより、配線容量による伝播時間、遅れ時
間等を小さくでき、実装面積を小さくできる。また、受
光素子信号をＭＯ３ＩＯで増幅することにより、出力信
号をそのまま制御信号に用いる、さらに複数の受光素子
とマイクロ・プロセッサを内蔵することにより、より高
度な制御信号を発生させ、用いることができるなどすぐ
れた効果を有する。In the present invention, by configuring the light receiving element and the MOS device C in the same chinobu, propagation time, delay time, etc. due to wiring capacitance can be reduced, and the mounting area can be reduced. In addition, by amplifying the light receiving element signal with MO3IO, the output signal can be used as a control signal as it is, and by incorporating multiple light receiving elements and a microprocessor, more advanced control signals can be generated and used. It has excellent effects such as
また本発明で、フォト・インタラプタ、フォトカブラ、
回転数検出等の信号を、この受光素子とＭＯ８型トラン
ジスタを集積する半導体装置により、受光素子への外付
は回路なしに得ることも可能である。The present invention also provides a photo interrupter, a photo coupler,
By using a semiconductor device that integrates this light receiving element and an MO8 type transistor, it is also possible to obtain signals such as rotation speed detection without external circuitry to the light receiving element.
第１図は、通常のＱ Ｍ ＯＳ Ｉ Ｃ製造プロセスの
ｐ型ＷＥＬＬを構成するまでの概略を示している。
第２図は、受光素子とＭ′ｏＳ型トランジスタを集積し
た半導体装置製造プロセスのｐ型ＷＥＬＬを構成するま
での概略を示す。
第１図Ａは、全面ドナー不純物イオン打込み工程図。第
１図Ｂは、ｐ型ＷＥＬＬイオン打込み工程図。第２図Ａ
は、受光素子部をマスクし、選択的にドナー不純物をイ
オン打込みする工程図。第２図Ｂは、受光素子部分のｐ
型領域及びＭ ＯＳ ＸＣ部のｐ型ＷＥＬＬ領域イオン
打込み工程図。
１ニア１型（比抵抗１０Ω−ｃｍ ） Ｓ１基板２：ド
ナー不純物打込み
３＝マスク（レジスト）
４：アクセプター不純物打込み
５：受光素子部分
（Ｓ：ＭＯ８工Ｃ部分FIG. 1 shows an outline of a typical QMOS IC manufacturing process up to the construction of a p-type WELL. FIG. 2 schematically shows a process for manufacturing a semiconductor device in which a light receiving element and an M'oS type transistor are integrated, up to the construction of a p-type WELL. FIG. 1A is a diagram showing the entire surface donor impurity ion implantation process. FIG. 1B is a p-type WELL ion implantation process diagram. Figure 2A
is a process diagram for selectively ion-implanting donor impurities while masking the light-receiving element portion. Figure 2B shows p of the light receiving element part.
FIG. 4 is a process diagram of ion implantation of the p-type WELL region of the type region and the MOS XC section. 1 near 1 type (specific resistance 10 Ω-cm) S1 substrate 2: Donor impurity implantation 3 = mask (resist) 4: Acceptor impurity implantation 5: Light receiving element part (S: MO8 process C part
Claims (1)
、受光素子領域とＭＯ８工Ｃ領域の基板の比抵抗及び不
純物濃度が異なっていることを特徴とする半導体装置。1. A semiconductor device comprising a light-receiving element section and a MO8IO on the same semiconductor substrate, the light-receiving element region and the MO8I-C region having different resistivities and impurity concentrations in the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57188664A JPS5978569A (en) | 1982-10-27 | 1982-10-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57188664A JPS5978569A (en) | 1982-10-27 | 1982-10-27 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5978569A true JPS5978569A (en) | 1984-05-07 |
| JPH0475666B2 JPH0475666B2 (en) | 1992-12-01 |
Family
ID=16227685
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57188664A Granted JPS5978569A (en) | 1982-10-27 | 1982-10-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5978569A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0191453A (en) * | 1987-10-02 | 1989-04-11 | Fuji Photo Film Co Ltd | Solid-state image sensing device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5483386A (en) * | 1977-12-15 | 1979-07-03 | Matsushita Electric Ind Co Ltd | Semiconductor device |
-
1982
- 1982-10-27 JP JP57188664A patent/JPS5978569A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5483386A (en) * | 1977-12-15 | 1979-07-03 | Matsushita Electric Ind Co Ltd | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0191453A (en) * | 1987-10-02 | 1989-04-11 | Fuji Photo Film Co Ltd | Solid-state image sensing device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0475666B2 (en) | 1992-12-01 |
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