JPH0475666B2 - - Google Patents
Info
- Publication number
- JPH0475666B2 JPH0475666B2 JP57188664A JP18866482A JPH0475666B2 JP H0475666 B2 JPH0475666 B2 JP H0475666B2 JP 57188664 A JP57188664 A JP 57188664A JP 18866482 A JP18866482 A JP 18866482A JP H0475666 B2 JPH0475666 B2 JP H0475666B2
- Authority
- JP
- Japan
- Prior art keywords
- impurity
- receiving element
- diffusion layer
- impurity diffusion
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000012535 impurity Substances 0.000 claims description 35
- 238000009792 diffusion process Methods 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 11
- 238000000034 method Methods 0.000 description 11
- 238000005468 ion implantation Methods 0.000 description 5
- 125000004429 atom Chemical group 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000007943 implant Substances 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 125000004437 phosphorous atom Chemical group 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/1443—Devices controlled by radiation with at least one potential jump or surface barrier
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Light Receiving Elements (AREA)
- Solid State Image Pick-Up Elements (AREA)
Description
【発明の詳細な説明】
本発明は、受光素子とMOS型トランジスタを
集積する半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device that integrates a light receiving element and a MOS transistor.
受光素子はLEDと対にし、機械的な変位を検
出する装置として非常に多くの分野で使用されて
いる。しかし、受光素子の出力が小さいため、制
御信号等に用いるには、増巾回路が、又デジタル
信号にするには、その回路が必要となる。そこで
受光素子と増巾等の回路を同一基板上に形成した
集積回路は、従来よりバイポーラIC内に受光素
子を含むことによつて作られている。しかし、バ
イポーラICではMOSICに較べて、消費電力が大
きい、動作電源電圧範囲が狭い、動作温度範囲が
狭い、雑音余裕度が小さい、集積度が低い等の欠
点を有している。近年、電子機器の小型・軽量・
低消費電力化が急速に進み、さらにICの動作速
度と集積密度が高まるにつれ、消費電力が過大に
なり、熱設計が難かしくなつてきている。そのた
め、受光素子を含む集積回路においても、バイポ
ーラトランジスタによる回路では対応できなくな
り回路部のCMOS化が必須となりつつある。又、
受光素子を含む集積回路は、機構部分に使用され
る頻度が多いため、電源電圧変動が大きく、温度
変動も大きく、雑音が高い等の悪環境化におかれ
る。この点においても、回路部のCMOS化は、
必須である。本発明は回路部をMOS型トランジ
スタで構成し、かかるバイポーラトランジスタに
よる受光素子を含む集積回路の欠点を除去したも
のである。 Light-receiving elements are paired with LEDs and are used in a wide variety of fields as devices for detecting mechanical displacement. However, since the output of the light-receiving element is small, an amplification circuit is required to use it as a control signal, and an amplification circuit is required to convert it into a digital signal. Therefore, integrated circuits in which a light-receiving element and a circuit such as an amplifier are formed on the same substrate have conventionally been made by including the light-receiving element in a bipolar IC. However, compared to MOSICs, bipolar ICs have disadvantages such as higher power consumption, narrower operating power supply voltage range, narrower operating temperature range, lower noise margin, and lower degree of integration. In recent years, electronic devices have become smaller, lighter,
As power consumption continues to decrease rapidly, and IC operating speeds and integration densities increase, power consumption is becoming excessive and thermal design is becoming more difficult. Therefore, even in integrated circuits that include light receiving elements, circuits using bipolar transistors are no longer compatible, and it is becoming essential to use CMOS circuits in the circuit sections. or,
Since integrated circuits including light receiving elements are frequently used in mechanical parts, they are exposed to adverse environments such as large power supply voltage fluctuations, large temperature fluctuations, and high noise. In this respect as well, converting the circuit to CMOS
Required. In the present invention, the circuit section is constructed of MOS type transistors, and the drawbacks of an integrated circuit including a light receiving element made of such a bipolar transistor are eliminated.
本発明は、受光素子とMOS型トランジスタを
同一チツプ内に集積し、且つ受光素子の能力をよ
り高感度化した半導体装置の製造方法を提供を提
供することにある。以下実施例に基づいて本発明
を詳しく説明する。 SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device in which a light receiving element and a MOS transistor are integrated in the same chip and the ability of the light receiving element is made more sensitive. The present invention will be described in detail below based on Examples.
まず従来のCMOSIC製造プロセスを第１図に
示す。 First, Figure 1 shows the conventional CMOSIC manufacturing process.
ａ 同図Ａに於て、10Ω・cm程度のｎ型Siウエハ
ー１の全面にドナー不純物（リン原子）をイオ
ン打込みする ２。a In Figure A, donor impurities (phosphorus atoms) are ion-implanted into the entire surface of an n-type Si wafer 1 of approximately 10Ω·cm.2.
ｂ 同図Ｂに於て、Ｐ型WELLを形成するため、
マスク３を用いアクセプタ不純物（ほう素原
子）をイオン打込みする ４。b In Figure B, to form a P-type WELL,
4. Ion implant acceptor impurity (boron atoms) using mask 3.
ｃ イオン打込みした不純物を活性化、さらにあ
る程度（ドナー不純物は10μm程度．アクセプ
タ不純物では8μm程度）の深さまでのWELLを
形成するため、ドライブインする。c Drive-in to activate the implanted impurities and form a WELL to a certain depth (approximately 10 μm for donor impurities and approximately 8 μm for acceptor impurities).
ｄ 以下、Ｐ型・ｎ型ストツパー形成 LOCOS酸化 ポリシリコン配線・ゲート形成 ｐ型不純物拡散 ｎ型不純物拡散 コンタクト穴形成 AL配線 保護膜形成 パツド穴形成 等のプロセスとなる。d Below, P type/n type stopper formation LOCOS oxidation Polysilicon wiring/gate formation p-type impurity diffusion n-type impurity diffusion contact hole formation AL wiring Protective film formation Pad hole formation etc. process.
次に、受光素子（フオトダイオード）を含む
CMOSIC製造プロセスを第２図に示す。 Next, it includes a light receiving element (photodiode).
Figure 2 shows the CMOSIC manufacturing process.
ｅ 同図Ａにおいて、後工程でつくられるｐ型
WELLとの接合で、最適なフオトダイオード
となる任意のｎ型Siウエハー（比抵抗50Ω・cm
程度）７に、マスク３を用い選択的にMOSIC
部分のみに、ドナー不純物をイオン打込みする
２。e In A of the same figure, the p-type produced in the subsequent process
Any n-type Si wafer (resistivity 50Ω・cm
degree) 7, selective MOSIC using mask 3
Ion-implant donor impurities only in the area 2.
ｆ 同図Ｂに於て、ｐ型WELLを形成するため、
マスク３を用いアクセプタ不純物をイオン打込
みする ４。f In Figure B, to form a p-type WELL,
Ion implant acceptor impurities using mask 3 4.
この時、受光素子部５にもイオン打込み４
し、ｐ−ｎ接合フオトダイオードを形成する。 At this time, ion implantation 4 is also applied to the light receiving element portion 5.
Then, a pn junction photodiode is formed.
ｇ イオン打込みした不純物を活性化、さらにあ
る程度以上の深さでWELLが形成でき、かつ
フオトダイオードが高感度化する接合深さとな
るように、不純物をドライブインする。フオト
ダイオードの接合深さは、入射する光の波長に
より、波長が比較的短いときには接合深さを浅
く、入射光波長が比較的長いときには、接合深
さを深くすることにより、高感度化できる。こ
れは、入射光波長が長いほど、光の半導体への
浸入する距離が深くなるためである。g. Activate the ion-implanted impurity and drive in the impurity so that a WELL can be formed at a certain depth and the junction depth is such that the photodiode has high sensitivity. The junction depth of the photodiode depends on the wavelength of the incident light, and sensitivity can be increased by making the junction shallower when the wavelength is relatively short and by increasing the junction depth when the wavelength of the incident light is relatively long. This is because the longer the wavelength of the incident light, the deeper the distance that the light penetrates into the semiconductor.
ｈ 以下、前記通常CMOSIC製造プロセスと同
一。h The following is the same as the normal CMOSIC manufacturing process described above.
この製造工程によりMOSIC部分６は通常の製
造工程で作成される場合と、WELL深さが異な
るのみで、トランジスタの特性上同一となり、工
程も第１図Ａと第２図Ａに示されるように、フオ
ト工程が１回増加するだけである。又、フオトダ
イオード部分５については、最適の接合深さ、最
適の基板不純物濃度にすることができる。さら
に、第２図Ａに示されるように、ドナー不純物が
イオン打込みされないことにより、ドナー不純物
のイオン打込みによる基板表面の結晶格子の乱れ
をなくすことができる。結晶格子が乱れると、乱
れたシリコン原子が、電子・正孔の再結合中心と
なり、少数キヤリアのライフタイムが減少する。
すなわち、光入射によつて生れた電子・正孔が、
電流とならずに、半導体中で再結合してしまい、
フオトダイオードの効率の減少につながる。又、
フオトダイオードのｐ型WELL部分に、余分な
ドナー不純物の存在を、かなり少なく、すなわち
もとの基板中に含まれる数だけにおさえられるた
め、ｐ型WELL中の不純物濃度（ドナー原子＋
アクセプタ原子）を必要最少限にできる。このこ
とはキヤリアの不純物散乱を最少限におさえるこ
とになり、キヤリアの拡散長を長くできる。この
ことはフオトダイオードの効率の増加につなが
る。すなわち、受光素子部分にドナー不純物をイ
オン打込みしないために、キヤリアのライフタイ
ム及び拡散長を長くでき、フオトダイオードの高
効率化が達成できる。 Due to this manufacturing process, the MOSIC part 6 is the same as that produced by the normal manufacturing process, except for the WELL depth, and the characteristics of the transistor are the same, and the process is also as shown in Figures 1A and 2A. , the number of photo steps increases by only one. Furthermore, the photodiode portion 5 can have an optimal junction depth and an optimal substrate impurity concentration. Furthermore, as shown in FIG. 2A, since the donor impurity is not ion-implanted, it is possible to eliminate disturbances in the crystal lattice on the substrate surface caused by the ion-implantation of the donor impurity. When the crystal lattice is disordered, the disordered silicon atoms become centers for recombination of electrons and holes, reducing the lifetime of minority carriers.
In other words, electrons and holes created by light incidence are
Instead of becoming a current, they recombine in the semiconductor,
leading to a decrease in photodiode efficiency. or,
Since the presence of extra donor impurities in the p-type WELL portion of the photodiode can be kept to a fairly small number, that is, to the number contained in the original substrate, the impurity concentration in the p-type WELL (donor atoms +
acceptor atoms) can be minimized. This minimizes the scattering of impurities in the carrier and increases the diffusion length of the carrier. This leads to an increase in the efficiency of the photodiode. That is, since donor impurities are not ion-implanted into the light-receiving element portion, the lifetime and diffusion length of the carrier can be lengthened, and high efficiency of the photodiode can be achieved.
上記の例では、ｎ型基板LOCOS・Siゲートプ
ロセスについて述べたが、同様にｐ型基板
LOCOS、さらにプレナーSiゲート、ALゲートプ
ロセスにも適用できる。 In the above example, the n-type substrate LOCOS/Si gate process was described, but the p-type substrate
It can also be applied to LOCOS, planar Si gate, and AL gate processes.
本発明は、受光素子とMOSICを同一チツプ内
に構成することにより、配線容量による伝播時
間、遅れ時間等を小さくでき、実装面積を小さく
できる。また、受光素子信号をMOSICで増幅す
ることにより、出力信号をそのまま制御信号に用
いる、さらに複数の受光素子とマイクロ・プロセ
ツサを内蔵することにより、より高度な制御信号
を発生させ、用いることができるなどすぐれた効
果を有する。さらに受光素子形成領域の不純物原
子数がMOSトランジスタ形成領域の不純物原子
数に比べて低くすることによつてキヤリアの不純
物散乱を抑え、キヤリアのライフタイム及び拡散
長を長くでき、受光素子の効率をを向上すること
が出来るという効果を有しております。 In the present invention, by configuring a light receiving element and a MOSIC in the same chip, propagation time, delay time, etc. due to wiring capacitance can be reduced, and the mounting area can be reduced. Additionally, by amplifying the photodetector signal with a MOSIC, the output signal can be used as a control signal as is, and by incorporating multiple photodetectors and a microprocessor, more sophisticated control signals can be generated and used. It has excellent effects such as Furthermore, by lowering the number of impurity atoms in the photodetector formation region compared to the number of impurity atoms in the MOS transistor formation region, impurity scattering of carriers can be suppressed, the carrier lifetime and diffusion length can be lengthened, and the efficiency of the photodetector can be increased. It has the effect of being able to improve the
更にMOSトランジスタ形成領域としてウエル
の形成工程と受光素子領域としての不純物拡散層
の形成を同時に行うので製造工程を大幅に増やす
必要がなく、したがつて信頼性の高い半導体装置
を得ることが出来るという効果も兼ね備えていま
す。 Furthermore, since the process of forming the well for the MOS transistor formation region and the formation of the impurity diffusion layer for the light-receiving element region are performed simultaneously, there is no need to significantly increase the number of manufacturing steps, making it possible to obtain a highly reliable semiconductor device. It also has effects.
また本発明で、フオト・インタラプタ、フオト
カプラ、回転数検出等の信号を、この受光素子と
MOS型トランジスタを集積する半導体装置によ
り、受光素子への外付け回路なしに得ることも可
能である。 In addition, in the present invention, signals from a photo interrupter, photo coupler, rotation speed detection, etc. can be connected to this light receiving element.
By using a semiconductor device that integrates MOS transistors, it is also possible to obtain the light receiving element without an external circuit.
第１図は、通常のCMOSIC製造プロセスのｐ
型WELLを構成するまでの概略を示している。
第２図は、受光素子とMOS型トランジスタを集
積した半導体装置製造プロセスのｐ型WELLを
構成するまでの概略を示す。第１図Ａは、全面ド
ナー不純物イオン打込み工程図。第１図Ｂは、ｐ
型WELLイオン打込み工程図。第２図Ａは、受
光素子部をマスクし、選択的にドナー不純物をイ
オン打込みする工程図。第２図Ｂは、受光素子部
分のｐ型領域及びMOSIC部のｐ型WELL領域イ
オン打込み工程図。
１……ｎ型（比抵抗10Ω・cm）Si基板、２…ド
ナー不純物打込み、３…マスク（レジスト）、４
…アクセプター不純物打込み、５…受光素子部
分、６…MOSIC部分、７…ｎ型（比抵抗50Ω・
cm）Si基板。
Figure 1 shows the normal CMOSIC manufacturing process.
This shows an outline of how to configure the type WELL.
FIG. 2 shows an outline of a semiconductor device manufacturing process in which a light receiving element and a MOS transistor are integrated until a p-type WELL is constructed. FIG. 1A is a diagram showing the entire surface donor impurity ion implantation process. Figure 1B is p
Type WELL ion implantation process diagram. FIG. 2A is a process diagram for selectively ion-implanting donor impurities while masking the light-receiving element portion. FIG. 2B is a diagram of the ion implantation process for the p-type region of the light-receiving element portion and the p-type WELL region of the MOSIC portion. 1... N-type (specific resistance 10 Ω cm) Si substrate, 2... Donor impurity implantation, 3... Mask (resist), 4
...Acceptor impurity implantation, 5...Photodetector part, 6...MOSIC part, 7...N type (specific resistance 50Ω・
cm) Si substrate.
Claims (1)
体基板より高い不純物濃度を有する第１導電型の
第１不純物拡散層を選択的に設ける工程、前記第
１不純物拡散層中及び前記半導体基板の一部に同
一導電型の不純物を同時に注入し、前記第１不純
物拡散層中にMOSトランジスタ形成領域となる
第２導電型の第２不純物拡散層を設けるととも
に、前記半導体基板中に受光素子形成領域となる
第２導電型の第３不純物拡散層を設ける工程を有
し、前記第２不純物拡散層に比べて、前記第３不
純物拡散層の方が少ない不純物原子数を有するこ
とを特徴とする半導体装置の製造方法。1. A step of selectively providing a first impurity diffusion layer of a first conductivity type having a higher impurity concentration than the semiconductor substrate in a low concentration semiconductor substrate of a first conductivity type; Impurities of the same conductivity type are simultaneously implanted into a portion of the semiconductor substrate to provide a second impurity diffusion layer of a second conductivity type that will become a MOS transistor formation region in the first impurity diffusion layer, and a light receiving element formation region in the semiconductor substrate. a step of providing a third impurity diffusion layer of a second conductivity type, wherein the third impurity diffusion layer has a smaller number of impurity atoms than the second impurity diffusion layer. Method of manufacturing the device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57188664A JPS5978569A (en) | 1982-10-27 | 1982-10-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57188664A JPS5978569A (en) | 1982-10-27 | 1982-10-27 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5978569A JPS5978569A (en) | 1984-05-07 |
| JPH0475666B2 true JPH0475666B2 (en) | 1992-12-01 |
Family
ID=16227685
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57188664A Granted JPS5978569A (en) | 1982-10-27 | 1982-10-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5978569A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0191453A (en) * | 1987-10-02 | 1989-04-11 | Fuji Photo Film Co Ltd | Solid-state image sensing device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5483386A (en) * | 1977-12-15 | 1979-07-03 | Matsushita Electric Ind Co Ltd | Semiconductor device |
-
1982
- 1982-10-27 JP JP57188664A patent/JPS5978569A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5483386A (en) * | 1977-12-15 | 1979-07-03 | Matsushita Electric Ind Co Ltd | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5978569A (en) | 1984-05-07 |
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