JP3139454B2 - Photodetector with built-in circuit - Google Patents
Photodetector with built-in circuitInfo
- Publication number
- JP3139454B2 JP3139454B2 JP10125126A JP12512698A JP3139454B2 JP 3139454 B2 JP3139454 B2 JP 3139454B2 JP 10125126 A JP10125126 A JP 10125126A JP 12512698 A JP12512698 A JP 12512698A JP 3139454 B2 JP3139454 B2 JP 3139454B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- conductivity type
- buried layer
- built
- receiving element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
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- Solid State Image Pick-Up Elements (AREA)
- Light Receiving Elements (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は回路が受光素子デバ
イスに内蔵された回路内蔵受光素子に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light receiving element with a built-in circuit in which a circuit is built in a light receiving element device.
【０００２】[0002]
【従来の技術】図４は従来の回路内蔵受光素子を示す断
面図である。ｐ-型シリコン基板１の表面にＡｓをイオ
ン注入することによりｎ+埋め込み層８が局部的に形成
され、更にその上に、ｎエピタキシャル層６が形成され
ている。そして、ｐ型不純物をエピタキシャル層８の表
面に拡散することにより、ｐ+層７がエピタキシャル層
６の表面に局部的に形成されており、これにより、ｐｎ
接合のフォトダイオードが形成されている。また、ｎ+
埋め込み層８に接触し、ｎエピタキシャル層６の表面に
到達するｎ+層５がｎエピタキシャル層６の厚さ方向に
延びて形成されている。そして、このｎ+層５が電源Ｖ
ｃｃに接続され、ｐ-基板１が接地ＧＮＤに接続され、
ｐ+拡散層７が回路部９に接続されている。なお、ｎエ
ピタキシャル層６だけでは不純物濃度が薄く、抵抗が高
くなるため、ｎ+層５が追加されている。従って、この
ｎ+層５は厚さが薄くなるように、通常、Ａｓ不純物を
注入することにより形成する。2. Description of the Related Art FIG. 4 is a sectional view showing a conventional light receiving element with a built-in circuit. An n + buried layer 8 is locally formed by ion-implanting As into the surface of the p − type silicon substrate 1, and an n epitaxial layer 6 is further formed thereon. Then, by diffusing the p-type impurity into the surface of the epitaxial layer 8, the p + layer 7 is locally formed on the surface of the epitaxial layer 6, whereby the pn
A junction photodiode is formed. Also, n +
An n + layer 5 which contacts buried layer 8 and reaches the surface of n epitaxial layer 6 is formed extending in the thickness direction of n epitaxial layer 6. The n + layer 5 is connected to the power supply V
cc, p - substrate 1 is connected to ground GND,
The p + diffusion layer 7 is connected to the circuit section 9. Note that the n + layer 5 is added because only the n epitaxial layer 6 has a low impurity concentration and a high resistance. Therefore, the n + layer 5 is usually formed by implanting As impurities so as to reduce the thickness.
【０００３】このように構成された従来の回路内蔵受光
素子においては、ｎエピタキシャル層６又はｎ+埋め込
み層８で発生したキャリアはｐ+層７までの距離が短い
ため、高速で回路部９へ到達する。基板１の深い領域で
発生して、表面付近まで時間をかけて拡散してきた遅い
キャリアはＶｃｃへ流れる。In the conventional light receiving element with a built-in circuit configured as described above, the carrier generated in the n epitaxial layer 6 or the n + buried layer 8 has a short distance to the p + layer 7, so that it can be transferred to the circuit section 9 at high speed. To reach. Slow carriers generated in a deep region of the substrate 1 and diffused over time near the surface flow to Vcc.
【０００４】図５は従来の他の回路内蔵受光素子を示す
断面図である、ｐ-基板１上に、ｎエピタキシャル層６
が成長されており、このｎエピタキシャル層６がｐ-基
板１に到達するｐ+層４により分離されてフォトダイオ
ードが構成されている。[0004] FIG. 5 is a sectional view showing another conventional circuit-integrated light-receiving element, p - on the substrate 1, n epitaxial layer 6
Are grown, and the n epitaxial layer 6 is separated by the p + layer 4 reaching the p − substrate 1 to form a photodiode.
【０００５】このように構成された回路内蔵受光素子に
おいては、ｐ-基板１とｎエピタキシャル層６との界面
のｐｎ接合の上下で発生したキャリアは再結合するもの
を除いて全て回路部９に流れる。In the light receiving element with a built-in circuit configured as described above, all the carriers generated above and below the pn junction at the interface between the p − substrate 1 and the n epitaxial layer 6 are re-coupled to the circuit section 9 except for those that recombine. Flows.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、図４に
示す回路内蔵受光素子においては、高速動作はするもの
の、多くのキャリアが電源Ｖｃｃに逃げてしまうため、
受光感度が０．１４Ａ／Ｗと低く、このため回路の増幅
度を高める必要性が生じ、出力ノイズ特性が悪いという
欠点を有する。これは表面付近のフォトカレントしか回
路部９に流れていかないため、一定のパワーの光を入力
しても、回路部９に流れる光電流は小さくなるからであ
る。However, in the light-receiving element with a built-in circuit shown in FIG. 4, although high-speed operation is performed, many carriers escape to the power supply Vcc.
The light receiving sensitivity is as low as 0.14 A / W, which necessitates increasing the degree of amplification of the circuit, and has the disadvantage of poor output noise characteristics. This is because only the photocurrent near the surface flows into the circuit section 9, and the photocurrent flowing through the circuit section 9 is reduced even if light of a constant power is input.
【０００７】また、図５に示す回路内蔵受光素子におい
ては、受光感度は０．５Ａ／Ｗと高いものの、ｐ-基板
１の深い領域で発生したキャリア（この場合、電子）が
拡散してｐｎ接合面に到達するまでに極めて長時間がか
かり、高速動作ができないという欠点がある（ｆｃ(-3d
B)＝１５ＭＨｚ）。即ち、例えばＣＤ（コンパクトディ
スク）で通常使用されている７８０ｎｍの波長の光では
数＋μｍの深さまで光が入るが、そこで発生した光がｐ
ｎ接合付近に到達するまでには数百ｎｓを要してしまう
ため、高速応答ができなくなる。In the light-receiving element with a built-in circuit shown in FIG. 5, although the light-receiving sensitivity is as high as 0.5 A / W, carriers (in this case, electrons) generated in a deep region of the p - substrate 1 diffuse and pn. There is a disadvantage that it takes an extremely long time to reach the bonding surface, and high-speed operation cannot be performed (fc (−3d
B) = 15 MHz). That is, for example, in the case of light having a wavelength of 780 nm which is generally used in a CD (compact disk), light enters to a depth of several + μm.
Since it takes several hundred ns to reach the vicinity of the n-junction, high-speed response cannot be performed.
【０００８】本発明はかかる問題点に鑑みてなされたも
のであって、受光感度が高いと共に、高速応答性が優れ
ている回路内蔵受光素子を提供することを目的とする。The present invention has been made in view of the above problems, and has as its object to provide a light receiving element with a built-in circuit which has high light receiving sensitivity and excellent high speed response.
【０００９】[0009]
【課題を解決するための手段】本発明に係る回路内蔵受
光素子は、第１導電型半導体基板と、この基板の表面に
局部的に形成された第２導電型埋め込み層と、この第２
導電型埋め込み層の上に形成された第１導電型埋め込み
層と、前記基板及び第１導電型埋め込み層の上に形成さ
れた第２導電型エピタキシャル層と、このエピタキシャ
ル層の表面に前記第１導電型埋め込み層に対向するよう
に形成された第１導電型層と、前記エピタキシャル層に
形成され前記第１導電型埋め込み層と前記第１導電型層
とを接続する第１導電型領域と、前記エピタキシャル層
に形成され前記第２導電型埋め込み層を素子表面に電気
的に導出する第２導電型領域とを有し、前記第２導電型
埋め込み層、前記第１導電型埋め込み層、前記エピタキ
シャル層及び前記第１導電型層の相互界面でｐｎ接合が
形成されていることを特徴とする。According to the present invention, there is provided a light receiving element with a built-in circuit, comprising: a semiconductor substrate of a first conductivity type; a buried layer of a second conductivity type formed locally on the surface of the substrate;
A first conductivity type buried layer formed on the conductivity type buried layer; a second conductivity type epitaxial layer formed on the substrate and the first conductivity type buried layer; A first conductivity type layer formed so as to face the conductivity type buried layer, a first conductivity type region formed in the epitaxial layer and connecting the first conductivity type buried layer and the first conductivity type layer; A second conductivity type region formed in the epitaxial layer and electrically leading the second conductivity type buried layer to an element surface; the second conductivity type buried layer; the first conductivity type buried layer; A pn junction is formed at a mutual interface between the layer and the first conductivity type layer.
【００１０】この回路内蔵受光素子において、前記第１
導電型埋め込み層は、平面視でストライプ状に形成され
ているか、又は前記第１導電型埋め込み層は、平面視で
格子状に形成されていることが好ましい。In this light receiving element with a built-in circuit, the first
It is preferable that the conductive type buried layer is formed in a stripe shape in plan view, or the first conductive type buried layer is formed in a grid shape in plan view.
【００１１】また、前記第１導電型層は回路部に接続さ
れ、前記第２導電型領域は電源Ｖｃｃに接続され、前記
基板は接地に接続することができる。The first conductivity type layer may be connected to a circuit portion, the second conductivity type region may be connected to a power supply Vcc, and the substrate may be connected to ground.
【００１２】[0012]
【発明の実施の形態】以下、本発明の実施例について添
付の図面を参照して具体的に説明する。図１は本発明の
実施例に係る回路内蔵受光素子を示す断面図である。ｐ
-シリコン基板１の上面にｎ+埋め込み層２が局部的に形
成され、このｎ+埋め込み層２の上に、ｐ+埋め込み層３
がパターン形成されている。ｎ+埋め込み層２は不純物
としてＰを使用することにより、深い位置まで拡散させ
ることが好ましい。このｎ+埋め込み層２及びｐ+埋め込
み層３を形成した後、ｎエピタキシャル層６が形成され
ている。そして、このｎエピタキシャル層６の表面に
は、ｐ型不純物を表面から拡散することによりｐ+層７
が形成されている。そして、ｎエピタキシャル層６に
は、ｐ+層７とｐ+埋め込み層３とを接続するｐ+層４が
形成されており、またｎ+埋め込み層２を表面に電気的
に導出するｎ+層５が形成されている。なお、ｐ+埋め込
み層３は図２に示すように平面視で櫛歯状又はストライ
プ状に形成されており、これにより、ｎ+埋め込み層２
とｎエピタキシャル層６とが広範囲で接触するようにな
っている。そして、ｎ+層５が電源Ｖｃｃに接続され、
ｐ-基板１が接地ＧＮＤに接続され、ｐ+拡散層７が回路
部９に接続されている。本実施例においては、ｐ+層７
とｎエピタキシャル層６との界面、ｎエピタキシャル層
６とｐ+埋め込み層３との界面及びｐ+埋め込み層３とｎ
+埋め込み層２との界面に形成されるｐｎ接合により、
フォトダイオードが形成されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be specifically described below with reference to the accompanying drawings. FIG. 1 is a sectional view showing a light receiving element with a built-in circuit according to an embodiment of the present invention. p
An n + buried layer 2 is locally formed on the upper surface of the silicon substrate 1, and ap + buried layer 3 is formed on the n + buried layer 2;
Are patterned. The n + buried layer 2 is preferably diffused to a deep position by using P as an impurity. After forming the n + buried layer 2 and the p + buried layer 3, an n epitaxial layer 6 is formed. The p + -type impurity is diffused from the surface of the n
Are formed. In the n epitaxial layer 6, ap + layer 4 connecting the p + layer 7 and the p + buried layer 3 is formed, and an n + layer for electrically leading the n + buried layer 2 to the surface. 5 are formed. Incidentally, p + buried layer 3 is formed in a comb shape or a stripe shape in plan view as shown in FIG. 2, thereby, n + buried layer 2
And the n epitaxial layer 6 are in contact with each other in a wide range. Then, the n + layer 5 is connected to the power supply Vcc,
The p − substrate 1 is connected to the ground GND, and the p + diffusion layer 7 is connected to the circuit section 9. In this embodiment, the p + layer 7
Interface between n + epitaxial layer 6, interface between n epitaxial layer 6 and p + buried layer 3 and interface between p + buried layer 3 and n +
+ Due to the pn junction formed at the interface with the buried layer 2,
A photodiode is formed.
【００１３】このように構成された本実施例の回路内蔵
受光素子においては、Ｓｉ基板及びＳｉ層内に光が入射
されると、その光エネルギーに応じたキャリア（電子・
ホール対）がＳｉ中に生成される。その際、発生したキ
ャリアは、拡散又はドリフトによりＳｉ中を移動し、ｐ
ｎ接合を介して光電流となる。In the light-receiving element with a built-in circuit according to the present embodiment, when light enters the Si substrate and the Si layer, carriers (electrons and electrons) corresponding to the light energy are applied.
Hole pairs) are generated in the Si. At that time, the generated carriers move in Si by diffusion or drift, and p
Photocurrent flows through the n-junction.
【００１４】本実施例においては、ｐ型基板１で発生し
たキャリア（この場合、電子）は表面方向へ拡散し、ｎ
+埋め込み層２とｎ+層５を介して電源Ｖｃｃへ流れる。
ｎ+埋め込み層２で発生したキャリア（この場合、ホー
ル）の一部は、表面方向に拡散し、ｐ+埋め込み層３、
ｐ+層４及びｐ+層７を介して回路部９へ流れ込む。同様
に、ｐ+埋めこみ層３、ｎエピタキシャル層６、ｐ+拡散
層７で発生したキャリアは回路部９へ流れ込む。In this embodiment, carriers (electrons in this case) generated in the p-type substrate 1 diffuse toward the surface, and n
It flows to power supply Vcc via + buried layer 2 and n + layer 5.
Some of the carriers (holes in this case) generated in the n + buried layer 2 diffuse in the surface direction, and the p + buried layer 3
It flows into the circuit section 9 via the p + layer 4 and the p + layer 7. Similarly, carriers generated in the p + buried layer 3, the n epitaxial layer 6, and the p + diffusion layer 7 flow into the circuit section 9.
【００１５】従って、ｎ+埋め込み層２より上方の層で
発生したキャリアが、フォトカレントとして回路部９に
流れ込むと共に、本実施例においては、深い領域までｎ
＋埋め込み層２が形成されているため、感度を高くする
ことができる。このため、本実施例においては、応答速
度を低下させることなく、受光感度を向上させることが
できる。例えば、応答速度をｆｃ(-3dB)＝２００ＭＨ
ｚ、受光感度を１．８倍(0.23A/W)に向上させることが
できる。Accordingly, carriers generated in the layer above the n + buried layer 2 flow into the circuit section 9 as a photocurrent, and in the present embodiment, n
Since the + buried layer 2 is formed, the sensitivity can be increased. Therefore, in this embodiment, the light receiving sensitivity can be improved without lowering the response speed. For example, if the response speed is fc (−3 dB) = 200 MH
z, the light receiving sensitivity can be improved 1.8 times (0.23 A / W).
【００１６】また、ｐ+埋め込み層３をストライプ状に
形成することにより、ｎエピタキシャル層６とｎ+埋め
込み層２を広範囲で接触させることができるので、ｎエ
ピタキシャル層６のキャリアを低抵抗で電源Ｖｃｃへ移
動させることができる。ｎ+埋め込み層２とｎエピタキ
シャル層６とが離れていれば、ｎエピタキシャル抵抗が
大きくなり、高速動作が得られなくなる。また、ｐ+埋
め込み層３がなければ、ｎ+埋め込み層２で発生したキ
ャリア（この場合、ホール）は、ｎエピタキシャル層６
を通過して表面のｐ+拡散層７まで拡散していかなけれ
ば、回路部９に流れることができない。そして、そのキ
ャリア移動は拡散で起こるため、極めて遅いものとな
る。従って、このキャリア移動域の途中にｐ+埋め込み
層３を設けることにより、拡散する距離が短くなり、高
速応答が可能となる。Further, by forming the p + buried layer 3 in a stripe shape, the n epitaxial layer 6 and the n + buried layer 2 can be brought into contact over a wide range, so that the carrier of the n epitaxial layer 6 can be supplied with a low resistance by a power source. Vcc. If n + buried layer 2 and n epitaxial layer 6 are separated from each other, n epitaxial resistance increases, and high-speed operation cannot be obtained. If there is no p + buried layer 3, carriers (holes in this case) generated in the n + buried layer 2 are
, It cannot flow to the circuit section 9 unless it diffuses to the p + diffusion layer 7 on the surface. Since the carrier movement occurs by diffusion, it becomes extremely slow. Therefore, by providing the p + buried layer 3 in the middle of the carrier movement region, the diffusion distance is shortened, and high-speed response is possible.
【００１７】次に、図３を参照して本発明の第２実施例
について説明する。上記実施例は、図２に示すように、
ｐ+埋め込み層３がストライプ状をなすものであった
が、本実施例は、図３に示すように、ｐ+埋め込み層３
の形状を格子状としている。Next, a second embodiment of the present invention will be described with reference to FIG. In the above embodiment, as shown in FIG.
p + but buried layer 3 was intended to form a stripe, this embodiment, as shown in FIG. 3, p + buried layer 3
Has a lattice shape.
【００１８】本実施例においては、ｎ+埋め込み層２か
らｐ+層７までの平均の距離がより短くなるため、更に
一層高速化することができる。In this embodiment, since the average distance from the n + buried layer 2 to the p + layer 7 is shorter, the speed can be further increased.
【００１９】[0019]
【発明の効果】以上説明したように、本発明によれば、
第２導電型埋め込み層、前記第１導電型埋め込み層、前
記エピタキシャル層及び前記第１導電型層の相互界面で
ｐｎ接合が形成されており、これらのｐｎ接合界面で生
じた光電流は、第１導電型領域及び第１導電型層を介し
て回路部に流れるので、十分な電流が回路部に流れ、感
度が極めて高い。また、本発明は、第１導電型埋め込み
層を設けたので、キャリアの拡散距離は短くて済み、応
答速度が高い。As described above, according to the present invention,
A pn junction is formed at the mutual interface between the buried layer of the second conductivity type, the buried layer of the first conductivity type, the epitaxial layer, and the layer of the first conductivity type, and the photocurrent generated at the pn junction interface is Since the current flows to the circuit portion through the one conductivity type region and the first conductivity type layer, a sufficient current flows to the circuit portion, and the sensitivity is extremely high. Further, in the present invention, since the first conductivity type buried layer is provided, the diffusion distance of the carrier can be short, and the response speed is high.
【図１】本発明の実施例に係る回路内蔵受光素子を示す
断面図である。FIG. 1 is a cross-sectional view showing a light-receiving element with a built-in circuit according to an embodiment of the present invention.
【図２】同じくそのｐ+埋め込み層３の平面パターンを
示す図である。FIG. 2 is a view showing a plane pattern of the p + buried layer 3 similarly.
【図３】本発明の他の実施例におけるｐ+埋め込み層３
の平面パターンを示す図である。FIG. 3 shows a p + buried layer 3 according to another embodiment of the present invention.
FIG. 4 is a diagram showing a plane pattern of FIG.
【図４】従来の回路内蔵受光素子を示す断面図である。FIG. 4 is a cross-sectional view showing a conventional light receiving element with a built-in circuit.
【図５】従来の他の回路内蔵受光素子を示す断面図であ
る。FIG. 5 is a cross-sectional view showing another conventional light receiving element with a built-in circuit.
１：ｐ−シリコン基板 ２：ｎ＋埋め込み層 ３：ｐ＋埋め込み層 ４：ｐ＋層 ５：ｎ＋層 ６：ｎエピタキシャル層 ７：ｐ＋層 ８：ｎ＋埋め込み層 ９：回路部 1: p-silicon substrate 2: n + buried layer 3: p + buried layer 4: p + layer 5: n + layer 6: n epitaxial layer 7: p + layer 8: n + buried layer 9: circuit section
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 31/10 - 31/119 H01L 27/14 - 27/148 ──────────────────────────────────────────────────の Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 31/10-31/119 H01L 27/14-27/148
Claims (6)
面に局部的に形成された第２導電型埋め込み層と、この
第２導電型埋め込み層の上に形成された第１導電型埋め
込み層と、前記基板及び第１導電型埋め込み層の上に形
成された第２導電型エピタキシャル層と、このエピタキ
シャル層の表面に前記第１導電型埋め込み層に対向する
ように形成された第１導電型層と、前記エピタキシャル
層に形成され前記第１導電型埋め込み層と前記第１導電
型層とを接続する第１導電型領域と、前記エピタキシャ
ル層に形成され前記第２導電型埋め込み層を素子表面に
電気的に導出する第２導電型領域とを有し、前記第２導
電型埋め込み層、前記第１導電型埋め込み層、前記エピ
タキシャル層及び前記第１導電型層の相互界面でｐｎ接
合が形成されていることを特徴とする回路内蔵受光素
子。A first conductivity type semiconductor substrate; a second conductivity type buried layer formed locally on the surface of the substrate; and a first conductivity type buried layer formed on the second conductivity type buried layer. Layer, a second conductivity type epitaxial layer formed on the substrate and the first conductivity type buried layer, and a first conductivity type formed on the surface of the epitaxial layer so as to face the first conductivity type buried layer. A mold layer, a first conductivity type region formed in the epitaxial layer and connecting the first conductivity type buried layer to the first conductivity type layer, and a second conductivity type buried layer formed in the epitaxial layer. A second conductivity type region that is electrically derived on the surface, and a pn junction is formed at a mutual interface between the second conductivity type buried layer, the first conductivity type buried layer, the epitaxial layer, and the first conductivity type layer. Is formed A light receiving element with a built-in circuit, characterized in that:
ストライプ状に形成されていることを特徴とする請求項
１に記載の回路内蔵受光素子。2. The light-receiving element with a built-in circuit according to claim 1, wherein the first conductivity type buried layer is formed in a stripe shape in plan view.
格子状に形成されていることを特徴とする請求項１に記
載の回路内蔵受光素子。3. The light-receiving element with a built-in circuit according to claim 1, wherein the first conductivity type buried layer is formed in a lattice shape in a plan view.
いることを特徴とする請求項１乃至３のいずれか１項に
記載の回路内蔵受光素子。4. The light-receiving element with a built-in circuit according to claim 1, wherein the first conductivity type layer is connected to a circuit section.
されていることを特徴とする請求項１乃至４のいずれか
１項に記載の回路内蔵受光素子。5. The light-receiving element with a built-in circuit according to claim 1, wherein the second conductivity type region is connected to a power supply Vcc.
する請求項１乃至５のいずれか１項に記載の回路内蔵型
受光素子。6. The light receiving element with a built-in circuit according to claim 1, wherein the substrate is grounded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10125126A JP3139454B2 (en) | 1998-05-07 | 1998-05-07 | Photodetector with built-in circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10125126A JP3139454B2 (en) | 1998-05-07 | 1998-05-07 | Photodetector with built-in circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11330533A JPH11330533A (en) | 1999-11-30 |
| JP3139454B2 true JP3139454B2 (en) | 2001-02-26 |
Family
ID=14902501
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10125126A Expired - Fee Related JP3139454B2 (en) | 1998-05-07 | 1998-05-07 | Photodetector with built-in circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3139454B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102151856B1 (en) * | 2018-12-03 | 2020-09-03 | 정상옥 | Led light apparatus with heat radiating structure |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014041674A1 (en) * | 2012-09-14 | 2014-03-20 | 株式会社日立製作所 | Semiconductor photoreceptor element |
-
1998
- 1998-05-07 JP JP10125126A patent/JP3139454B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102151856B1 (en) * | 2018-12-03 | 2020-09-03 | 정상옥 | Led light apparatus with heat radiating structure |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH11330533A (en) | 1999-11-30 |
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