JPS5978563A - Programmable read only memory integrated circuit - Google Patents

Abstract

PURPOSE:To enable low voltage action by using a junction type element for a unit cell and an RTL (resistor-transistor logic) for a peripheral circuit. CONSTITUTION:Junction type transistors Q11, Q12, Q21, and Q22 having at least the first and second emitter regions are decided as memory cells, and the first emitters are connected to word lines r1 and r2 and collectors to bit lines l1 and l2. In the state that the base is not connected, the transistor turns off even when the first emitter becomes at a low potential; but, when the junction between the first emitter and the base is short-circuited, the transistor can be turned ON. Memory can be performed by such presence of short-circuit. Besides, the peripheral circuit of the memory is composed of the RTL as shown in the figure.

Description

【発明の詳細な説明】 本発明は、モノリシック集積回路化に好適なＰＲ，ＯＭ
（プロゲラマフ゛ル争リード・オンリー・メモリ）に関
するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention provides PR and OM suitable for monolithic integration.
(Regarding read-only memory, a programmer file conflict).

ＦＲＯＭには従来バイポーラ型とＭＯＳ型（ＥＰＲＯＭ
）がちシ、共に５Ｖ標準電源電圧で動作するものは多数
量産されているが、ＩＶクラスの低電源電圧で動作可能
なものは少なく、あってもせいぜい、メモリ・セルアレ
イのみで別チップで各種周辺回路を必要とし、メモリセ
ルアレイは完全デコードされていないため、端子数が多
く、集積化には極めて不利であった。Conventionally, there are two types of FROM: bipolar type and MOS type (EPROM).
) There are many products that can be mass-produced that operate with a standard power supply voltage of 5V, but there are few that can operate with a low power supply voltage of IV class, and even if there are, at most, the memory cell array is used as a separate chip for various peripherals. Since the memory cell array was not completely decoded, the number of terminals was large, which was extremely disadvantageous for integration.

本発明の目的は、周辺回路までメモリセルアレイと同一
チップに集積化し１■クラスの低電源電圧で動作可能な
モノリシック集積化に好適な低電力１１ｔＯＭを提供す
ることにある。An object of the present invention is to provide a low-power 11tOM suitable for monolithic integration, in which peripheral circuits are integrated on the same chip as a memory cell array, and can operate at a power supply voltage as low as 12 class.

本発明によれば、メモリセルアレイの単位セルに所謂ジ
ャレクション型の素子を使用し、且つ周辺回路に所謂Ｒ
Ｔ　Ｌ　（Ｒｅｓｉｓｔｏｒ−ＴｒａｎｓｉｓｔｏｒＬ
ｏｇｉｃ）を使用して組合せることによシ始めて１■で
動作可能なＰ　Ｒ，ＯＭが得られる。According to the present invention, a so-called jurection type element is used in a unit cell of a memory cell array, and a so-called R
T L (Resistor-Transistor L
By combining them using Logic), an operable PR,OM can be obtained from the beginning.

次に図面全参照して本発明について説明する。Next, the present invention will be explained with reference to all the drawings.

第１図は本発明の実施例である。FIG. 1 shows an embodiment of the invention.

本図においてＱｌｌ　ｒ　Ｑ１２　ｒ　Ｑ２１　ｒ　Ｑ
２２は２行２列（便宜上２行２列であられすが、一般の
１行ｍ列に拡張出来る事はいうまでもない）のマトリク
スに配置されたメモリセルである。本図では、各セルは
未書込状態に相当し、たとえばＱｕで第１エミッタＥ、
がベース（電極はない）に対し逆バイアス（定電位）が
かかっても、トランジスタはＯＦＦしている。次に、後
述の所定の方法で電気的に書込むつまりエミッタＥ１と
ベースのジャンクションヲ短絡させると％Ｅ１はベース
に直結し、セルＱｏは第２図の如くなり、ＢＩにある正
電位が印加されると、トランジスタはＯＮ出来る。この
トランジスタのＯＮ、ＯＦＦを情報し、０に対応させる
事によシ、所謂ＦＲＯＭが形成出来る。なお、抵抗器Ｒ
Ｃは、書込時のまわシこみ電流を制限するための抵抗器
であり、且つ読出動作時の電流（本例では抵抗器Ｒ，，
Ｒ８等で決まる）に対しては無視しうる程度の電位降下
しか生じないような値に設定されている。In this figure, Qll r Q12 r Q21 r Q
Reference numeral 22 denotes memory cells arranged in a matrix of 2 rows and 2 columns (for convenience, this is 2 rows and 2 columns, but it goes without saying that it can be expanded to a general 1 row and m columns). In this figure, each cell corresponds to an unwritten state, for example, Qu has a first emitter E,
Even if a reverse bias (constant potential) is applied to the base (no electrode), the transistor remains OFF. Next, when electrical writing is performed using a predetermined method described later, that is, the junction between the emitter E1 and the base is shorted, %E1 is directly connected to the base, the cell Qo becomes as shown in Figure 2, and a positive potential is applied to BI. When this happens, the transistor can be turned on. A so-called FROM can be formed by recording ON/OFF information of this transistor and making it correspond to 0. In addition, the resistor R
C is a resistor for limiting the transfer current during writing, and the current during reading operation (in this example, resistors R, ,
(determined by R8, etc.) is set to a value that causes only a negligible potential drop.

さて従来は、この型のメモリセルは、メモリセルマトリ
クスだけの形では知られていたが、メモリセル数が少し
多くなるとたちまち端子数が著増し、（たとえば３２　
Ｘ　３２＝　１．０２４ビツトの時、信号端子だけで３
２＋３２＝６４本）且つこれに見合う、やはシ端子数の
多い周辺回路を別に用意せねばならず、モノリシック集
積化には大変不適であった。特に本メモリセルマトリク
スは、各セルの限流抵抗Ｒｃがある関係で低電力動作に
適しておシ、就中Ｖｃｃ二１ｖ程度の低電圧低電力動作
に好適であるが、その場合周辺回路も当然同じ低電圧電
源で動作せねばならないが、従来本形成のメモリセルと
同一チップに製造可能な周辺回路は知られていなかった
。Conventionally, this type of memory cell was known only in the form of a memory cell matrix, but as the number of memory cells increases slightly, the number of terminals increases rapidly (for example, 32
When X 32 = 1.024 bits, only the signal terminal has 3
2+32=64) and a peripheral circuit with a correspondingly large number of terminals had to be separately prepared, making it extremely unsuitable for monolithic integration. In particular, this memory cell matrix is suitable for low-power operation because of the current-limiting resistor Rc of each cell, and is especially suitable for low-voltage and low-power operation with a Vcc of about 1 V. Naturally, it must operate with the same low-voltage power supply, but conventionally, there has been no known peripheral circuitry that can be manufactured on the same chip as the memory cell formed in this way.

本発明によれば、第１図の実施例に見られるように、行
・列の周辺回路にＲＴ　Ｌ論理回路を導入する事によシ
、はじめてＶｃｃ＝ＩＶ程度の低電圧動作の可能な、モ
ノリシック集積化に好適なＦ　ＲＯＭが得られる。According to the present invention, as seen in the embodiment of FIG. 1, by introducing RT L logic circuits into the peripheral circuits of rows and columns, low voltage operation of about Vcc=IV is possible for the first time. A F ROM suitable for monolithic integration is obtained.

本例においては行（ｒｌ　、ｒ２　）側、列側（１１，
１２）周辺回路共各行（列）ドライバはここでは２人力
ＮＯＲ形式で示しており、これら入力は、さらに第３図
（こ示す如き正補出力発生回路の出力Ａ、Ａ’で駆動す
る事によシ、２進（Ｂ　Ｉ　ＮＡＲＹ　）入力Ａを複数
個受けてフルデコードする事が可能になる。In this example, the row (rl, r2) side and the column side (11,
12) The peripheral circuits and each row (column) driver are shown here in a two-man NOR format, and these inputs are further driven by the outputs A and A' of the correction output generation circuit shown in Figure 3. It is now possible to receive and fully decode a plurality of binary (BI NARY) inputs A.

当然端子数は著減し、たとえば先の３２×３２の場合信
号入力はわずか１０本で済む。これらの回路において、
行・列ドライバの負荷抵抗几１．几、。Naturally, the number of terminals is significantly reduced; for example, in the case of 32×32, only 10 signal inputs are required. In these circuits,
Load resistance of row/column driver 1. Rin,.

Ｒ３ＪＬ４等は書込時には書込電源のまわりこみバスと
なるので、セルの抵抗Ｒｃと同じくその大きさにまわシ
こみ電流量が書込電源にくらべ充分小さいよう考慮せね
ばならない。出力端子Ｏに接続されたセンス回路はここ
では最も単純なｌｔ、／ｈｋ入力とする２人力ＮＯＲ形
式のトランジスタＱｏｔ　＋　ＱＯ２で構成したが、変
形は几ＴＬ回路の範囲でも種々ありうる。センスアンプ
の入力抵抗器Ｒ３，、Ｒ４，ははやはシ書込時のまわシ
こみに対して限流抵抗器として働いている。Since R3JL4 and the like serve as a wrap-around bus for the write power supply during writing, consideration must be given to ensuring that the amount of the wrap-around current is sufficiently smaller than the write power supply, similar to the resistance Rc of the cell. The sense circuit connected to the output terminal O is here constructed of the simplest two-power NOR type transistor Qot + QO2 with lt and /hk inputs, but various modifications may be made within the scope of the TL circuit. The input resistors R3, R4 of the sense amplifier function as current-limiting resistors against rotation during writing.

Ａ１＋Ａ２＋Ａ３＋Ａ４は書込のための行・列ドライバ
であるが、セル及び読出用周辺回路には上述のようにま
わりこみ電流に対して限流抵抗がはいるよう配慮しであ
るので、通常のＦＲＯＭと同じ回路が使える。実例を各
々第４図、第５図に示す。書込動作時には専用電源Ｖｃ
ｃｐ、Ｖｐを使う。これらのドラ１バのデコード入力回
路（図示せず）は、周知のＴＴＬ回路やＲＴＬ回路が使
えその２進（Ｂ　Ｉ　ＮＡＲ’Ｙ　）入力端子は読出用
２進（Ｂ　Ｉ　ＮＡＲＹ　）入力の対応入力と共通に出
来る。なお又、その他の論理回路を）（、Ｔ　Ｌ論理で
組んで同一チップに収納する事も可能である。たとえば
、ＢＩＮ’ＡＲ，Ｙアドレス入力Ａ（複数）をレジスタ
・バッファする事も可能であるし、又シフトレジスタで
受けてシリアル−パラレル変換すれば入力端子数を僅か
２本（入力データとクロック）に減らせる。出力０（複
数）もレジスタバッファやシフトレジスタバッファする
ことが出来る。A1+A2+A3+A4 are row/column drivers for writing, but the cells and reading peripheral circuits are designed to have current-limiting resistance against the wrap-around current as mentioned above, so they are the same as normal FROM. circuit can be used. Examples are shown in FIGS. 4 and 5, respectively. Dedicated power supply Vc during write operation
Use cp and Vp. The decoding input circuit (not shown) of these drivers can be a well-known TTL circuit or RTL circuit, and its binary (BI NAR'Y) input terminal is compatible with the read binary (BI NARY) input. Can be used in common with input. Furthermore, it is also possible to combine other logic circuits with )(,TL logic and store them on the same chip.For example, it is also possible to register and buffer the BIN'AR, Y address inputs A (multiple). Also, by receiving it in a shift register and converting it from serial to parallel, the number of input terminals can be reduced to just two (input data and clock). Output 0 (multiple) can also be buffered in a register or shift register.

このようにして、Ｖｃｃ＝ＩＶ程度で動作可能で且つプ
ログラマブルは集積化されたＦＲＯＭが提供出来、且つ
本技術は狭義のＦＲＯＭにとどまらず、プログラマブル
な素子マトリクスを含む任意の論理回路に適用出来るの
で、本発明の効果は犬である。In this way, it is possible to provide a programmable integrated FROM that can operate at approximately Vcc=IV, and the present technology is not limited to FROM in a narrow sense, but can be applied to any logic circuit including a programmable element matrix. , the effect of the present invention is on dogs.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の実施例を示す図、第２〜５図は第１図
の発明に関連する各機能ブロックの具体例を示す図であ
る。 Ｑｕ−Ｑ２□・・・・・・Ｒ，０ＭセルＡｌ（Ａ２）FIG. 1 is a diagram showing an embodiment of the present invention, and FIGS. 2 to 5 are diagrams showing specific examples of each functional block related to the invention of FIG. Qu-Q2□・・・R, 0M cell Al (A2)

Claims (3)

【特許請求の範囲】[Claims] （１）少なく共第１および第２のエミッタ領域を有する
トランジスタと、１つの抵抗器を有し、該トランジスタ
のコレクタが列線に、該第１のエミッタが行線に、該第
２のエミッタが該抵抗器を介して接地されてなる記憶セ
ルが複数個性・列に配されてなるアレイを有し、その行
および列デコーダ回路の少なく共一部がＲＴＬ論理によ
シ構成されていることを特徴とするＰＲ，ＯＭ集積回路
。(1) a transistor having at least a common first and second emitter region and a resistor, the collector of the transistor being in a column line, the first emitter being in a row line, and the collector of the transistor being in a column line; has an array in which a plurality of memory cells are arranged in individual columns, each of which is grounded through the resistor, and at least a common part of the row and column decoder circuits is configured by RTL logic. PR, OM integrated circuit featuring: （２）上記行デコーダが各行あたり、コレクタが共通に
行線と負荷抵抗器に接続され、エミッタが接地され、ベ
ースが直接又は別の抵抗器を介して各々入力端子に接続
された複数個のトランジスタからなることを特徴とする
特許請求の範囲第（１）項に記載のＦＲＯＭ集積回路。(2) For each row, the row decoder has a plurality of collectors whose collectors are commonly connected to the row line and the load resistor, whose emitters are grounded, and whose bases are each connected to an input terminal directly or through another resistor. The FROM integrated circuit according to claim 1, characterized in that it is composed of a transistor. （３）上記列デコーダが各列あだシ、コレクタが共通に
列線と負荷抵抗器に接続され、エミッタが接地され、ベ
ースが直接又は抵抗器を介して各々入力端子に接続され
た複数個のトランジスタと、コレクタが共通接続されて
出力端子となり、ベースが各々抵抗器を介して各列線に
接続され、エミッタが接地された別の複数個のトランジ
スタを含むことを特徴とする特許請求の範囲第（１）項
に記載のＰＲ，ＯＭ集積回路。(3) A plurality of the above column decoders are arranged in each column, the collectors are commonly connected to the column line and the load resistor, the emitters are grounded, and the bases are connected to the input terminals directly or through resistors. and another plurality of transistors whose collectors are commonly connected to serve as output terminals, whose bases are connected to each column line via a resistor, and whose emitters are grounded. PR, OM integrated circuit according to scope item (1).