JPS5973846U - semiconductor circuit - Google Patents
semiconductor circuitInfo
- Publication number
- JPS5973846U JPS5973846U JP16949782U JP16949782U JPS5973846U JP S5973846 U JPS5973846 U JP S5973846U JP 16949782 U JP16949782 U JP 16949782U JP 16949782 U JP16949782 U JP 16949782U JP S5973846 U JPS5973846 U JP S5973846U
- Authority
- JP
- Japan
- Prior art keywords
- drain
- inverter circuit
- comparator
- circuit
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Logic Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図はプルアップ用抵抗を用いたＴＴＬＩＣとＣＭＯ
３ＩＣの接続図、第２図は一般のレベルシフタ回路、第
３図及び第４図は各々本考案の実施例を示す等価回路図
である二゛ツ
なお図において、１・・・・・・ＴＴＬＩＣ，２・・・
・・・ 。
ＣＭＯ３ＩＣ，３・・・・・・プルアンプ用抵抗、４・
・・・・・入力段インバータ回路、５・・・・・・コン
パレータ回路、６・・・・・・コンパレータ回路、７・
・・・・・基準電圧源、８−・・・・・・帰還抵抗、９
・・・・・・入力段インバータ回路、１０、ＴＯ’・・
・・・・コンパレータ回路の入力端子、 １１・・・
・・・コンパレータ回路の出力端子、１２゜１４・・・
・・・Ｎチャンネル型トランジスタ、１３・・・・・・
Ｐチャネル型トランジスタ、である。Figure 1 shows TTLIC and CMO using pull-up resistors.
3IC connection diagram, Figure 2 is a general level shifter circuit, and Figures 3 and 4 are equivalent circuit diagrams showing embodiments of the present invention.In the two diagrams, 1...TTLIC ,2...
.... CMO3IC, 3... Resistor for pull amplifier, 4.
... Input stage inverter circuit, 5 ... Comparator circuit, 6 ... Comparator circuit, 7.
...Reference voltage source, 8-...Feedback resistor, 9
...Input stage inverter circuit, 10, TO'...
...Input terminal of comparator circuit, 11...
...Comparator circuit output terminal, 12°14...
...N-channel transistor, 13...
It is a P-channel transistor.
Claims (1)
の出力をゲートに接続したＭＯＳ ｌ−ランジスタ１と
、少なくとも２個のインバータ回路１とインバータ回路
２を有し、該コンパレータの一方の入力に基準電圧源を
接続し、他の入力は該インバータ回路１のゲートとドレ
インに接続し、該インバータ回路１及びインバータ回路
２の電源を該ＭＯＳトランジスタ１のドレイン又はソー
スに接続し、ＭＯＳトランジスタ１のソース又はドレイ
ンは外部電源、ＶＤＤに接続されており、該インバータ
回路２のゲートを入力端子、ドレインを出力端子として
構成したことを特徴とする半導体回路。The CMO5 circuit has a comparator, a MOS l-transistor 1 whose gate is connected to the output of the comparator, and at least two inverter circuits 1 and 2, and a reference voltage source is connected to one input of the comparator. , the other input is connected to the gate and drain of the inverter circuit 1, the power supplies of the inverter circuit 1 and the inverter circuit 2 are connected to the drain or source of the MOS transistor 1, and the source or drain of the MOS transistor 1 is connected to the external power supply. , VDD, the gate of the inverter circuit 2 is configured as an input terminal, and the drain is configured as an output terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16949782U JPS5973846U (en) | 1982-11-09 | 1982-11-09 | semiconductor circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16949782U JPS5973846U (en) | 1982-11-09 | 1982-11-09 | semiconductor circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5973846U true JPS5973846U (en) | 1984-05-19 |
Family
ID=30370280
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16949782U Pending JPS5973846U (en) | 1982-11-09 | 1982-11-09 | semiconductor circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5973846U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60237720A (en) * | 1984-05-11 | 1985-11-26 | Seiko Epson Corp | Output circuit |
-
1982
- 1982-11-09 JP JP16949782U patent/JPS5973846U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60237720A (en) * | 1984-05-11 | 1985-11-26 | Seiko Epson Corp | Output circuit |
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