JPS5969970A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5969970A JPS5969970A JP18187082A JP18187082A JPS5969970A JP S5969970 A JPS5969970 A JP S5969970A JP 18187082 A JP18187082 A JP 18187082A JP 18187082 A JP18187082 A JP 18187082A JP S5969970 A JPS5969970 A JP S5969970A
- Authority
- JP
- Japan
- Prior art keywords
- type region
- resistor layer
- gate
- type
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 238000005468 ion implantation Methods 0.000 claims abstract 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052787 antimony Inorganic materials 0.000 abstract description 4
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 4
- 239000011574 phosphorus Substances 0.000 abstract description 4
- 230000035945 sensitivity Effects 0.000 abstract description 4
- 239000012535 impurity Substances 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract 2
- 230000002349 favourable effect Effects 0.000 abstract 1
- 230000000903 blocking effect Effects 0.000 description 5
- 230000002457 bidirectional effect Effects 0.000 description 3
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 description 1
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 210000003734 kidney Anatomy 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/7404—Thyristor-type devices, e.g. having four-zone regenerative action structurally associated with at least one other device
- H01L29/7408—Thyristor-type devices, e.g. having four-zone regenerative action structurally associated with at least one other device the device being a capacitor or a resistor
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Abstract
Description
【発明の詳細な説明】
技術分野
この発明は半導体装置に関し、より詳しくは逆阻止３端
子サイリスクや２方向性３端子ザイリスタ等のゲート電
極伺きの３端子サイリスクにおけるゲート電流感度なら
びにその制御に関する。DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a semiconductor device, and more particularly to gate current sensitivity and control thereof in a three-terminal thyristor connected to a gate electrode, such as a reverse blocking three-terminal thyristor or a bidirectional three-terminal zyristor.
背景技術
逆阻止３端子サイリスタや２方向性３端子ザイリスタ等
の３ ｉ／：ｉｉｔ子サイリスタは、ゲートに信号を与
えてターン・オンできるため、各種の分腎で広く利用き
れている。BACKGROUND TECHNOLOGY 3I/:IIT child thyristors, such as reverse blocking three-terminal thyristors and bidirectional three-terminal thyristors, can be turned on by applying a signal to the gate, and are therefore widely used in various kidney systems.
すなわち、逆阻止３端子サイリスタを例に説明すると、
このサイリスタｌは第１図および第２１図に示す構造を
有する。第１図はサイリスタ１の平面図を示し、第２図
は第１図のｎ−ｎ線に沿う断面図を示す。図において、
２．はＮ型の基板領域で、その両主面に全拡散によって
Ｐ欄領域３，４が形成され、さらに一方のＰ型領域４内
にＮ型領域５が選ＪＲ的に形成されている。６，７はＮ
型領域２と各Ｐ型領域３．４との間のＰＮ接合８，９よ
りも深く杉ｊ戊されたメサｔｆ、ｉｉ部で、］、０．１
１は前記メいるガラス等の絶縁保、８１１膜である。１
２ 、 ］、 ３ 、 コ、 ４はそれぞれ前記Ｐ型領
域３，４およびＮ型領域５に形成され／と１．アノード
電極、ケート電イ１叙およＯ・カソード電極である。In other words, taking a reverse blocking three-terminal thyristor as an example,
This thyristor l has the structure shown in FIGS. 1 and 21. FIG. 1 shows a plan view of the thyristor 1, and FIG. 2 shows a sectional view taken along line nn in FIG. In the figure,
2. is an N-type substrate region, and P column regions 3 and 4 are formed by full diffusion on both main surfaces thereof, and an N-type region 5 is selectively formed in one P-type region 4. 6 and 7 are N
In the mesa tf, ii section, which is deeper than the PN junctions 8, 9 between the type region 2 and each P-type region 3.4, ], 0.1
Reference numeral 1 denotes the 811 film, which is an insulator such as the above-mentioned glass. 1
2, ], 3, ko, and 4 are formed in the P-type regions 3, 4 and N-type region 5, respectively; and 1. The anode electrode, the cathode electrode, and the cathode electrode.
］二組の→ノーイリスタ１を使用する場合は、アノード
電４ｉ阪Ｅ、 ２とカソード電４永ｌ ４との間に、ア
ノード電極］２が正電位となる所定の電圧を与えておい
て、ゲート電極１３とカソード電４ｄｉ、１４間にゲー
ト電流（■ｏＴ）を流してターン・オンきせる。] When using two sets of →noirristors 1, a predetermined voltage is applied between the anode electrode 4, 2 and the cathode electrode 4, so that the anode electrode 2 has a positive potential. A gate current (■oT) is caused to flow between the gate electrode 13 and the cathode electrodes 4di and 14 to turn them on.
また、導通状態のサイリスタｌのアノード％ｍ ４ｉｍ
］ ２とカソード電イ余１４との間に、カソード電イ
命コ−４が正電位となる逆電圧を与えて、ターン・オフ
させる。Also, the anode %m of the thyristor l in the conductive state 4im
] A reverse voltage is applied between the cathode electrode 2 and the cathode electrode 14 so that the cathode electrode 4 has a positive potential, thereby turning it off.
上記のターン−オン動作において、サイリスタ］、をタ
ーン・オンさせるに必要なゲート亀泥の値が小さい程、
消費電力が小さくなるので、特に電池を電源とするよう
な電子＠器においては、この値が１及的に小さい、いわ
ゆる高感度サイリスクが要求される。しかしながら、ケ
ート電流が５μＡ以ｒｐｔｃもなると、ノイズ等によっ
て誤動作しやすくなるという問題点がある。一方、実際
に１８感度ザイリスタのＲ’ｆｆ要そのものは、サイリ
スクの全需要のうちの権く一部であり、大部分はゲート
電流ＩＪ）１０〜５０μ八程度σ〕、いわゆる中感度サ
イリスクか要求されている。しかるに、高感度サイリス
ク吉中感度サイリスクを全く別の股泪にすることは、原
価高となってψましくないし、中感度づイリスクにおい
ても、用途によって要求さノするゲート屯ＭＣ範囲は種
々ある。このため、高感度サイリスクから中感度サイリ
スクまで、若干の変更でカバーできるようなサイリスク
が要望される。In the turn-on operation described above, the smaller the gate value required to turn on the thyristor,
Since power consumption is reduced, a so-called high-sensitivity risk is required, especially in electronic devices that use batteries as a power source. However, if the gate current exceeds 5 μA rptc, there is a problem that malfunctions are likely to occur due to noise or the like. On the other hand, in reality, the R'ff requirement of the 18-sensitivity Zyristor itself is a significant part of the total demand for the thyristor, and most of it is the gate current IJ) of about 10 to 50 μ8 σ], the so-called medium-sensitivity thyrisk requirement. has been done. However, it would be unreasonable to make the high-sensitivity risk and the medium-sensitivity risk completely different because it would increase the cost, and even for medium-sensitivity risks, there are various gate MC ranges required depending on the application. . Therefore, there is a need for a CyRisk that can cover the range from high sensitivity CyRisk to medium sensitivity CyRisk with a few changes.
発明の開示
この発明は、上記の問題点を解決し、要望を満足できる
半導体装置を提供することを目的とするものである。DISCLOSURE OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems and provide a semiconductor device that can satisfy the demands.
この発明は簡単に白えば、ゲート電流の制御の７’ｊ
メＰｃ ＄ ｌ！１４ （ト、 ３ ；ｉ％子サすリス
クノゲー１−− カソード間、２方向性３り、■子すイ
リスクの第１陽極とカソード間を、バルク内ま／ζはバ
ルク」二に形成した細条状の抵抗層で接続したことを特
徴とするものである。Simply put, this invention is based on 7'j of gate current control.
Me PC $l! 14 (T, 3; i%) between the cathode, two-way 3, ■ between the first anode and the cathode of the secondary, within the bulk or ζ is the bulk. It is characterized by being connected by a strip-shaped resistance layer.
すなわち、バルク内のＰ ’Ｎ接合を通る正規のゲート
電流路の他に、このゲート電流路に並列に前記抵抗ｊ￥
１によるバイパスゲート電流路を形成して、みかけ上の
ゲート電流を増大し、ゲート惹度を変化するようにし、
しかも前記抵抗層の抵抗値を制御することンＣよって、
バイパスケ−１−％ ｉｔ路に流れるゲート電流分を変
えて・ゲート電流値を要求される大きさに制御し得ると
いう作用効果を奏する。That is, in addition to the normal gate current path passing through the P'N junction in the bulk, the resistor j\ is connected in parallel to this gate current path.
1 to form a bypass gate current path to increase the apparent gate current and change the gate attraction,
Moreover, by controlling the resistance value of the resistance layer,
By changing the amount of gate current flowing through the bypass circuit, the gate current value can be controlled to a required level.
発明を実施する７こめの最良の形態 以下、この発明の実施例を図面を参照して説明する。7 Best Modes for Carrying Out the Invention Embodiments of the present invention will be described below with reference to the drawings.
第３図はこの発明の一実施例の逆阻止３端子ザイリスタ
２０の平面図を示し、第４図は第３図のｒｖ−■Ｉｇに
沿う断面図を示す。図において、次の点を除いては第１
図および第２図と同様であるため、同一部分ま７ｉｌ：
は対応部分には同一参照符号をイリシている。第１図お
よび第２図と相違する点は、第１に、Ｐ壁領域４内に選
択的に形成されたＮ型領域５が島状に形成されているこ
とである。換言すれば、ＰＮ接合９′が全部上１ｉＪＪ
において終端していることである。第２に、ケート′屯
イφ・（１３の］・とカソード電極、極１４の土との間
に、両電４！＆’、 ｌ ３ 、 Ｉ ４をほぼ一周す
る形状て細条状の抵抗層２１が形成されていることであ
る。この抵抗層２１は、例えばｉＪ型不純物であるリン
やアンチモンを、イオンｎ：、入〃、てＰ壁領域４内に
浅り１」ち込んで形成される。あるいは、Ｐ型領域４十
にリンやアンチモンを所定濃度で含む多結晶ンリニｊン
層を形成することによって月蛭成できる。FIG. 3 shows a plan view of a reverse blocking three-terminal zyristor 20 according to an embodiment of the present invention, and FIG. 4 shows a sectional view taken along the line rv--Ig in FIG. In the figure, the first
Since it is similar to Fig. 2 and Fig. 2, the same parts are included:
The same reference numerals are used for corresponding parts. The first difference from FIGS. 1 and 2 is that the N-type region 5 selectively formed within the P-wall region 4 is formed in the form of an island. In other words, the PN junction 9' is all above 1iJJ
It ends at . Second, between the cathode electrode and the soil of the pole 14, there is a strip-like structure that goes around the electrodes 4!&', l3, and I4. A resistive layer 21 is formed.This resistive layer 21 is formed by implanting, for example, iJ-type impurities such as phosphorus or antimony into the P wall region 4 at a shallow depth of 1". Alternatively, it can be formed by forming a polycrystalline layer containing phosphorus or antimony at a predetermined concentration in the P-type region 40.
より具体的に説明すると、１．４ｍ１ｏのサイリスク２
０において、Ｐ副領域４の表面不純物濃度は１ＯＩｓ
ａｔｏｍｓ ／、 オー タテｈ ルが、ゲート電極１
３とカソード電極１４との間の印加電圧、すなわちケ−
ト電圧（ｖ（）Ｔ）を帆６ｖ一定にした条件のドで、抵
抗層２１を設けない場合は、ゲート電流が数μＡ以下で
ある。これＶＣ対して抵抗層２１の長さを３．４７鴎、
幅をコ、５μＡ一定として、ゲート電流稲１．を１０μ
Ａｌこしようとする場合は、抵抗層２１の比抵抗ρＳを
約２６０”／、にする。同様に、稲、−２０μへの場合
はｐＳ中１３０％にし、■。Ｔ−３０μへの場合ｉ’ｊ
： Ｐ ｓ ： ８７ ｒＪＤＫ ’ａ ’ｉｉｉ ｆ
ル。To explain more specifically, Cyrisk 2 of 1.4 m1o
0, the surface impurity concentration of the P subregion 4 is 1OIs
atoms/, the outer layer is the gate electrode 1
3 and the cathode electrode 14, that is, the voltage applied between the cathode electrode 14 and the cathode electrode 14.
Under the condition that the gate voltage (v()T) is constant at 6V, and the resistance layer 21 is not provided, the gate current is several μA or less. For this VC, the length of the resistance layer 21 is 3.47mm,
With the width constant at 5 μA, the gate current is 1. 10μ
When using Al, set the specific resistance ρS of the resistance layer 21 to about 260"/. Similarly, when using rice, -20μ, set it to 130% in pS, and ■. When using T-30μ, set i 'j
: P s : 87 rJDK 'a 'iii f
Le.
なお、上記実施例では抵抗１「ご２１が、ゲート電（函
１３およびカソード電極１４をほぼ一周するように杉成
する場合について示したが、ゲート電極１３の下とカソ
ード電極１４の下゛との間の任意の２点間を結ぶもので
あればよい。In the above embodiment, the case where the resistor 1 and the resistor 21 are arranged so as to go around the gate electrode (the box 13 and the cathode electrode 14) is shown, Any two points between them may be connected.
さらに、この発明は逆阻１イニ３端子サイリスクのみな
らず、２方向性３端子サイリスタ等の他のサイリスクに
ついても同骸に実施てきる。Furthermore, the present invention can be applied not only to reverse blocking one-in-three-terminal thyristors but also to other thyristors such as bidirectional three-terminal thyristors.
第１図および第２図は従来の逆阻止３端子サイリスクを
示し、第１□□□は平面図で、第２図は第１図のＢ−１
１線に沿う断面図である。第３図および第４１メ）はこ
の発明の一実施例である逆阻止３端子サイリスクを示Ｌ
１第３図は平面図、第４図は第３図のｙ−ｙｈに沿う［
１シ「面図である。
２ ・ −導電型領域（Ｎ型領域）、
３．４・・ 反対導電型領域（Ｐ型領域）、５・・・・
・・第２の一導電型領域（Ｎ型領域）、］−２・・ ア
ノード電極、
１３ ・・−ゲ − ト γ＝ 手Ｉｔ １１４ ・
・ カ ソ − ・ド′亀イψＪ１２１・ 抵抗層。Figures 1 and 2 show a conventional reverse-blocking three-terminal circuit. Figure 1 is a plan view, and Figure 2 is B-1 in Figure 1.
FIG. 1 is a cross-sectional view along line 1; Figures 3 and 41) show a reverse-blocking three-terminal circuit that is an embodiment of the present invention.
1 Figure 3 is a plan view, Figure 4 is along y-yh in Figure 3 [
1 is a side view. 2. - conductivity type region (N type region), 3.4... opposite conductivity type region (P type region), 5...
...Second one-conductivity type region (N-type region), ]-2... Anode electrode, 13...-Gate γ= Hand It 114
・Caso ・Do'kame ψJ121・Resistance layer.
Claims (1)
反対導電型領域の少なくとも一方に第２の一導電型領域
を形成し、前記各反対導電型領域と第２の一導電型領域
とにそれぞれ電極を形成してなる半導体装Ｗにおいて、 前記第２の一導電型領域が形成された反対導電型領域の
電極と第２の一導電型領域の電極との間を、細条状の抵
抗層で接続したことを特徴とする半導体装置。 ２、 ｉｆｉ記抵抗層が、半導体装置のバルク内に形
成されたイオン注入層である、特許請求の範囲第１項記
載の半導体装置。 ３ 前記抵抗層が、半導体装置のバルク上に形成された
多結晶ンリコン層である、特許請求の範囲第１項記載の
半導体装置。[Claims] 1- A conductivity type region has opposite conductivity type regions on both main surfaces, a second one conductivity type region is formed in at least one of the opposite conductivity type regions, and each of the opposite conductivity type regions and a second one-conductivity type region, in which an electrode is formed in the opposite conductivity type region where the second one-conductivity type region is formed, and an electrode in the second one-conductivity type region. A semiconductor device characterized in that a strip-shaped resistance layer is connected between the two. 2. The semiconductor device according to claim 1, wherein the resistance layer is an ion implantation layer formed in the bulk of the semiconductor device. 3. The semiconductor device according to claim 1, wherein the resistance layer is a polycrystalline silicon layer formed on the bulk of the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18187082A JPS5969970A (en) | 1982-10-15 | 1982-10-15 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18187082A JPS5969970A (en) | 1982-10-15 | 1982-10-15 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5969970A true JPS5969970A (en) | 1984-04-20 |
Family
ID=16108282
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18187082A Pending JPS5969970A (en) | 1982-10-15 | 1982-10-15 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5969970A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0235706A2 (en) * | 1986-02-27 | 1987-09-09 | Kabushiki Kaisha Toshiba | Thyristor having a resistance element coupled to its gate, and method of making the same |
| JPH0550655U (en) * | 1991-12-11 | 1993-07-02 | 日本無線株式会社 | Button battery holder |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5387676A (en) * | 1977-01-13 | 1978-08-02 | Toshiba Corp | Semiconductor control rectifier |
| JPS5447492A (en) * | 1977-09-21 | 1979-04-14 | Nec Corp | Thyristor |
| JPS5556658A (en) * | 1978-10-23 | 1980-04-25 | Nec Corp | Thyristor |
| JPS5565461A (en) * | 1978-11-10 | 1980-05-16 | Oki Electric Ind Co Ltd | Semiconductor switch |
| JPS5641179A (en) * | 1979-09-10 | 1981-04-17 | Mitsubishi Heavy Ind Ltd | Liquid dredger |
-
1982
- 1982-10-15 JP JP18187082A patent/JPS5969970A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5387676A (en) * | 1977-01-13 | 1978-08-02 | Toshiba Corp | Semiconductor control rectifier |
| JPS5447492A (en) * | 1977-09-21 | 1979-04-14 | Nec Corp | Thyristor |
| JPS5556658A (en) * | 1978-10-23 | 1980-04-25 | Nec Corp | Thyristor |
| JPS5565461A (en) * | 1978-11-10 | 1980-05-16 | Oki Electric Ind Co Ltd | Semiconductor switch |
| JPS5641179A (en) * | 1979-09-10 | 1981-04-17 | Mitsubishi Heavy Ind Ltd | Liquid dredger |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0235706A2 (en) * | 1986-02-27 | 1987-09-09 | Kabushiki Kaisha Toshiba | Thyristor having a resistance element coupled to its gate, and method of making the same |
| JPH0550655U (en) * | 1991-12-11 | 1993-07-02 | 日本無線株式会社 | Button battery holder |
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