JPS60137054A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS60137054A JPS60137054A JP25053583A JP25053583A JPS60137054A JP S60137054 A JPS60137054 A JP S60137054A JP 25053583 A JP25053583 A JP 25053583A JP 25053583 A JP25053583 A JP 25053583A JP S60137054 A JPS60137054 A JP S60137054A
- Authority
- JP
- Japan
- Prior art keywords
- region
- resistance
- type
- high concentration
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000009792 diffusion process Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 6
- 239000010703 silicon Substances 0.000 abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- 238000000034 method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000002775 capsule Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0802—Resistors only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
この発明は、Ｐｎ接合への逆バイアス電圧の印加によっ
て空乏層の厚さが変化することを利用して抵抗の値を変
えることが可能な半導体集積回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to a semiconductor integrated circuit in which the value of resistance can be changed by utilizing the change in the thickness of a depletion layer by applying a reverse bias voltage to a Pn junction. It is related to circuits.
従来例の構成とその問題点
半導体集積回路において、可変抵抗素子の要望が強く、
神々の電気回路に応用が考えられている。Conventional configurations and their problems In semiconductor integrated circuits, there is a strong demand for variable resistance elements.
Applications are being considered for electrical circuits for the gods.
従来は、第１図に示すように、ａとｂの２端子間に高抵
抗Ｒ，および低抵抗Ｒ２とダイオードＤの直列接続体が
並列に接続された回路構成をなし、これを半導体基板に
集積化した構造となっている。Conventionally, as shown in Fig. 1, a circuit configuration was formed in which a series connection body of a high resistance R, a low resistance R2, and a diode D were connected in parallel between two terminals a and b, and this was connected to a semiconductor substrate. It has an integrated structure.
この構造の可変抵抗素子の電圧−電流特性の代表例を第
２図に示す。ダイオードにかかるバイアス電圧が低い場
合および逆バイアスの場合には、ダイオードがＯＦＦ状
態であるので可変抵抗素子のＯＮ状態となり抵抗値はＲ
２で決まる値となる。A typical example of the voltage-current characteristics of a variable resistance element having this structure is shown in FIG. When the bias voltage applied to the diode is low or reverse biased, the diode is in the OFF state, so the variable resistance element is in the ON state and the resistance value is R.
The value is determined by 2.
ところで、この構造では、可変できる抵抗値かで制御で
きない不都合もあった。However, this structure also has the disadvantage that it cannot be controlled by the variable resistance value.
発明の目的
本発明は、上記の不都合をことごとく排除するで連続的
に変化することを利用して連続的に抵抗値を変えること
古ができる半導体集積回路の提供を目的とするものであ
る。OBJECTS OF THE INVENTION It is an object of the present invention to provide a semiconductor integrated circuit which eliminates all of the above-mentioned disadvantages and allows the resistance value to be continuously changed by utilizing continuous change.
発明の構成
本発明の半導体集積回路は、−導電形の半導体基板上に
形成された逆導電形の半導体層中にこれとは逆導電形の
抵抗領域が形成され、同抵抗領域内にこれとけ逆導電形
で拡散前面が同抵抗領域を貫通する高濃度領域が形成さ
れ、前記抵抗領域と前記高濃度領域に電極が形成された
構造のものである。この構造によれば、抵抗の実効断面
積が空乏層厚さの変化により変わることができ抵抗の値
を連続的に可変にすることができる。Structure of the Invention In the semiconductor integrated circuit of the present invention, a resistance region of an opposite conductivity type is formed in a semiconductor layer of an opposite conductivity type formed on a semiconductor substrate of a negative conductivity type, and a resistance region of a conductivity type opposite to the semiconductor layer is formed on a semiconductor substrate of a negative conductivity type. It has a structure in which a high concentration region of opposite conductivity type and a diffusion front penetrating the same resistance region is formed, and electrodes are formed in the resistance region and the high concentration region. According to this structure, the effective cross-sectional area of the resistor can be changed by changing the thickness of the depletion layer, and the value of the resistor can be continuously varied.
実施例の説明
第３図（ａｊは本発明の半導体集積回路の特徴部分であ
る抵抗領域内に電流方向に対して垂直に複数個の高濃度
のｎ影領域が抵抗領域を貫通して形成された構造の上面
図、第３図（ｂ）はその上面図のＸＸ′線部の縦断面図
である。本実施例はＰ形シリコン基板１の中に作り込ま
れたｎ形の埋め込み層２の上部には周囲がＰ形の分離領
域３で包囲されたｎ形の島領域４があり、この島領域４
の中にＰ形の抵抗領域５が形成され、この抵抗領域内に
拡散前面が抵抗領域を貫通しｎ形埋め込み層２に達する
高濃度ｎ影領域６が形成され、高濃度ｎ影領域６と抵抗
領域５にそれぞれ電極アと８が設けられている。なお９
は、電極とのオーミックコンタクトをはかる高濃度のオ
ーミック接触層である。Description of the Embodiment FIG. 3 (aj is a characteristic part of the semiconductor integrated circuit of the present invention in which a plurality of high concentration n-shaded regions are formed perpendicularly to the current direction in the resistor region penetrating the resistor region. FIG. 3(b) is a vertical cross-sectional view taken along line XX' of the top view.This embodiment shows an n-type buried layer 2 formed in a p-type silicon substrate 1. There is an n-type island region 4 surrounded by a P-type isolation region 3 on the upper part of the island region 4.
A P-type resistance region 5 is formed in the resistance region, and a high concentration n shadow region 6 is formed in which the diffusion front penetrates the resistance region and reaches the n type buried layer 2. Electrodes A and 8 are provided in the resistance region 5, respectively. Note 9
is a highly doped ohmic contact layer that makes ohmic contact with the electrode.
次に、−に記の構造を得るための製造方法を第４図〜第
７図を参照して具体的に説明する。なお第４図〜第７図
は、第３図（ａ）のＹＹ’線部の製造縦断面図である。Next, a manufacturing method for obtaining the structure shown in (-) will be specifically explained with reference to FIGS. 4 to 7. Note that FIGS. 4 to 7 are manufacturing longitudinal cross-sectional views taken along line YY' in FIG. 3(a).
まず、Ｐ形シリコン基板１の中に酸化シリコン膜をマス
クとしてアンチモンＳｂあるいは砒素ＡＳをスピンオン
法やイオン注入法あるいはカプセル法により選択的にド
ープしてｎ形埋め込み層２を形成する。こののち、表面
の酸化シリコン膜をすべて除去し、引き続いて表面全体
に比抵抗が０．５〜１０ΩＣＴＴＩのｎ形シリコン層を
１〜３０μｍの厚さにエピタキシャル成長させ、表面に
酸化シリコン膜１０を形成する。この酸化シリコン膜１
ｏをマスクとしてｎ形埋め込み層２を包囲する領域にボ
ロンＢを選択的にドープしてＰ形分離領域３を作り込み
島領域４を形成する（第４図）。First, an n-type buried layer 2 is formed in a P-type silicon substrate 1 by selectively doping antimony Sb or arsenic AS by a spin-on method, an ion implantation method, or a capsule method using a silicon oxide film as a mask. After this, all the silicon oxide film on the surface is removed, and then an n-type silicon layer with a resistivity of 0.5 to 10 ΩCTTI is epitaxially grown on the entire surface to a thickness of 1 to 30 μm to form a silicon oxide film 10 on the surface. do. This silicon oxide film 1
Boron B is selectively doped into a region surrounding the n-type buried layer 2 using the mask 0 as a mask to form a p-type isolation region 3 and an island region 4 (FIG. 4).
次に、島領域４内にリンｐｆｆ：イオン注入法あるいは
熱拡散法により選択的に拡散させ拡散前面がｎ形埋め込
み層２に達する深さの高濃度ｎ影領域６を複数個形成す
る（第５図）。なおこの拡散工程は、トランジスタのコ
レクタ抵抗減少のためのコレクタウオール領域形成と同
時になされる。Next, a plurality of high-concentration n shadow regions 6 are formed in the island region 4 by selectively diffusing phosphorus PFF by ion implantation or thermal diffusion to a depth where the diffusion front reaches the n-type buried layer 2. Figure 5). Note that this diffusion step is performed simultaneously with the formation of a collector all region for reducing the collector resistance of the transistor.
この後、酸化シリコン膜１０を全て除去し、新たに酸化
シリコン膜１１を形成し、この酸化シリコン膜１１をマ
スクとして高濃度ｎ影領域６を含む部分に表面不純物濃
度が１０１７〜１ｏ”／Ｃ１ｔ！の選択拡散領域をボロ
ンで形成しＰ形の抵抗領域５を形成する。つづいて、高
濃度ｎ影領域６内にトランジスタのエミッタ領域形成と
同時に電極とのオーミックコンタクトをはかるため高濃
度のオーミック接触ｊ曽９を形成する（第６図）。After that, the silicon oxide film 10 is completely removed, a new silicon oxide film 11 is formed, and using this silicon oxide film 11 as a mask, the surface impurity concentration is 1017 to 1o''/C1t in the portion including the high concentration n shadow region 6. A selective diffusion region ! is formed of boron to form a P-type resistance region 5. Next, a high concentration ohmic film is formed in the high concentration n shadow region 6 in order to form an emitter region of the transistor and at the same time make ohmic contact with the electrode. A contact j so 9 is formed (FIG. 6).
しかるのち、抵抗領域５の両端部分およびオーミック接
触１曽９内に電極を形成するためコンタクト部分を露出
させ、これらの部分に高純度のアルミニウムＡβあるい
はシリコンＳｉを重量比で１％含んだＡ４を用いて電極
７と８を形成する（第７図）。After that, the contact portions are exposed to form electrodes at both ends of the resistance region 5 and in the ohmic contact 9, and A4 containing 1% by weight of high-purity aluminum Aβ or silicon Si is applied to these portions. The electrodes 7 and 8 are formed using the same method (FIG. 7).
以上の工程を経て高濃度ｎ影領域６に繋がる電極７に抵
抗電極８よりも高い電圧を印加すると、空乏層が抵抗領
域６内に広がり抵抗の実効断面積を小さくして抵抗値を
大きくできる可変抵抗器が形成される。When a voltage higher than that applied to the resistive electrode 8 is applied to the electrode 7 connected to the high concentration n shadow region 6 through the above steps, a depletion layer spreads within the resistive region 6, reducing the effective cross-sectional area of the resistor and increasing the resistance value. A variable resistor is formed.
以上説明した本発明の半導体集積回路の製造方法では、
高濃度ｎ影領域６に繋がる電極７を各高濃度ｎ影領域６
の表面にコンタクト窓をあけて取り出しているが、抵抗
の値によってはこの高濃度ｎ影領域６０表面にコンタク
ト窓が形成できないほど狭い場合がある。この場合には
、第８図で示すように高濃度ｎ影領域６を抵抗領域６内
に形成すると同時に抵抗領域外にも高濃度ｎ影領域１２
を形成し、ｎ形埋め込み層２を通じて両者を接続し、抵
抗領域外の広い高濃度ｎ影領域１２にコンタクト窓をお
けて電極７を形成する構造にするとともできる。In the method for manufacturing a semiconductor integrated circuit of the present invention described above,
The electrodes 7 connected to the high concentration n shadow areas 6 are connected to each high concentration n shadow area 6.
Although a contact window is formed on the surface of the n-shade region 60 to take out the contact window, the contact window may be so narrow that a contact window cannot be formed on the surface of the high concentration n shadow region 60 depending on the resistance value. In this case, as shown in FIG. 8, a high concentration n shadow region 6 is formed within the resistance region 6, and at the same time a high concentration n shadow region 12 is formed outside the resistance region.
It is also possible to form a structure in which the two are connected through the n-type buried layer 2, and the electrode 7 is formed by placing a contact window in a wide high concentration n shadow region 12 outside the resistance region.
以上実施例の半導体集積回路のｆ１゛４造では、抵抗領
域内に拡散前面が抵抗領域を貫通した高濃度ｎ影領域が
、抵抗の電流方向に対して垂直に存在している。このた
め、高濃度ｎ影領域と抵抗領域間に逆バイアスを印加す
ると抵抗領域が高濃度ｎ影領域より不純物濃度が薄いの
で抵抗領域側に大部分空乏層が広がる。すると抵抗領域
を通過する電流の実効断面積が高濃度ｎ影領域の両側よ
り小さくなる。その結果抵抗値が大きくかつ変化率も大
きくなる。このように逆バイアス電圧を連続的に変化さ
せると空乏層の広がりが連続的に変化し、それによって
抵抗の実効断面積が連続的に変化することにより抵抗価
も連続的に変化させることができる。In the f1-4 structure of the semiconductor integrated circuit of the above embodiment, a high concentration n shadow region in which the diffusion front penetrates the resistor region exists perpendicularly to the current direction of the resistor. Therefore, when a reverse bias is applied between the high concentration n shadow region and the resistance region, the depletion layer mostly spreads toward the resistance region because the impurity concentration of the resistance region is lower than that of the high concentration n shadow region. Then, the effective cross-sectional area of the current passing through the resistance region becomes smaller than that on both sides of the high concentration n shadow region. As a result, the resistance value becomes large and the rate of change also becomes large. In this way, by continuously changing the reverse bias voltage, the spread of the depletion layer changes continuously, and as a result, the effective cross-sectional area of the resistance changes continuously, and the resistance value can also change continuously. .
また、抵抗の絶対値および抵抗の変化：￥、ｌ−Ｊ：第
３図（ａ）に示すように高濃度ｎ影領域６の長さβａ、
ギャップβｂおよび個数によって決定することができ、
低抵抗から高抵抗１で高範囲の可変抵抗素子か可能とな
る効果が奏される。In addition, the absolute value of resistance and the change in resistance: ¥, l-J: As shown in FIG.
It can be determined by the gap βb and the number of pieces,
The effect is that a variable resistance element with a high range from low resistance to high resistance 1 can be used.
また、高濃度ｎ影領域６がｎ形の島領域４に連繋しＣい
るため、抵抗領域の接合面には必ず逆バイアスがかかり
、抵抗電流のリーク電流は発生しない効果も奏される。Further, since the high concentration n shadow region 6 is connected to the n-type island region 4, a reverse bias is always applied to the junction surface of the resistance region, and there is also an effect that no leakage current of the resistance current occurs.
発明の効果
以上のように、本発明によれば抵抗値を連続的に変化し
うる半導体集積回路を提供できるので、工業的価値が高
い。Effects of the Invention As described above, the present invention has high industrial value because it can provide a semiconductor integrated circuit whose resistance value can be changed continuously.
第１図は、従来の可変抵抗素子の回路図、第２図は第１
図の電圧−電流特性図、第３図（２Ｌ） （ｂ）はそれ
ぞれ本発明の可変抵抗素子の上面図、断面構造図、第４
図〜第７図は本発明の１実施例にかかる１・・・・・Ｐ
形シリコン基板、２・・・・・ｎ形埋め込み層、３・・
・・Ｐ形分離領域、４・・・・・ｎ形の島領域、５・・
・Ｐ形の抵抗領域、６・・・・・・高濃度ｎ形領域、７
・・・バイアス電圧供給用電極、８・・・・・抵抗電極
、９・・・・・オーミック接触層、１０．１１・・・・
・・酸化シリコン膜、１２・・・・・抵抗領域外のコン
タクト用高濃度ｎ形領域。
代理人の氏名 弁理士 中 屋敷 男 ほか１名第１爾
ａ
第２図
第 ３ 口
第４図Figure 1 is a circuit diagram of a conventional variable resistance element, and Figure 2 is a circuit diagram of a conventional variable resistance element.
The voltage-current characteristic diagram in Figure 3 (2L) (b) is a top view, cross-sectional structure diagram, and Figure 4 (b) of the variable resistance element of the present invention, respectively.
Figures 1 to 7 are 1...P according to one embodiment of the present invention.
shaped silicon substrate, 2... n-type buried layer, 3...
...P-type isolation region, 4...N-type island region, 5...
・P-type resistance region, 6...High concentration n-type region, 7
... Bias voltage supply electrode, 8 ... Resistance electrode, 9 ... Ohmic contact layer, 10.11 ...
...Silicon oxide film, 12...High concentration n-type region for contact outside the resistance region. Name of agent Patent attorney Nakayashiki Otoko and 1 other person Figure 2 Figure 3 Portion Figure 4
Claims (5)
の半導体層中に一導電形の抵抗領域が形成され、同抵抗
領域内に逆導電形で拡散前面が前記抵抗領域を貫通する
高濃度領域が形成され、前記抵抗領域と前記高濃度領域
に電極が形成されていることを特徴とする半導体集積回
路。(1) - A resistance region of one conductivity type is formed in a semiconductor layer of an opposite conductivity type formed on a semiconductor substrate of a conductivity type, and a diffusion front surface of the opposite conductivity type penetrates the resistance region within the same resistance region. A semiconductor integrated circuit characterized in that a high concentration region is formed, and electrodes are formed in the resistance region and the high concentration region.
形の埋め込み層が形成されていることを特徴とする特許
請求の範囲第１項に記載の半導体集積回路。(2) The semiconductor integrated circuit according to claim 1, wherein a buried layer of a conductivity type opposite to that of the resistive region is formed in the semiconductor substrate directly below the resistive region.
特徴とする特許請求の範囲第１項又は第２項に記載の半
導体集積回路。(3) The semiconductor integrated circuit according to claim 1 or 2, wherein the high concentration region is connected to the buried layer.
の高濃度領域が作り込まれていることを特徴とする特許 集積回路。(4) A patented integrated circuit characterized in that a high concentration region of opposite conductivity type is formed in a portion surrounding a resistive region of a semiconductor layer.
領域を包囲する部分に作り込まれた高濃度領域に電極が
形成されていることを特徴とする特許請求の範囲第１項
，第２項．第３項．第４項いずれかに記載の半導体集積
回路。(5) The buried layer serves as a connection region for the high concentration region and the electrode is formed in the high concentration region formed in a portion surrounding the resistance region. Section 2. Section 3. 4. The semiconductor integrated circuit according to any one of Item 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25053583A JPS60137054A (en) | 1983-12-26 | 1983-12-26 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25053583A JPS60137054A (en) | 1983-12-26 | 1983-12-26 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60137054A true JPS60137054A (en) | 1985-07-20 |
Family
ID=17209343
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25053583A Pending JPS60137054A (en) | 1983-12-26 | 1983-12-26 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60137054A (en) |
-
1983
- 1983-12-26 JP JP25053583A patent/JPS60137054A/en active Pending
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