JPS5940275A - Apparatus for calculating collector loss - Google Patents

Apparatus for calculating collector loss

Info

Publication number
JPS5940275A
JPS5940275A JP15219482A JP15219482A JPS5940275A JP S5940275 A JPS5940275 A JP S5940275A JP 15219482 A JP15219482 A JP 15219482A JP 15219482 A JP15219482 A JP 15219482A JP S5940275 A JPS5940275 A JP S5940275A
Authority
JP
Japan
Prior art keywords
output
collector loss
load
power amplifier
loss
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15219482A
Other languages
Japanese (ja)
Other versions
JPH0429983B2 (en
Inventor
Hideyasu Jikou
秀保 慈幸
Katsuhiko Higashiyama
勝比古 東山
Takeshi Sato
剛士 佐藤
Kazuo Toda
戸田 一雄
Takashi Fujii
喬 藤井
Shizuyoshi Matsubara
松原 静喜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP15219482A priority Critical patent/JPS5940275A/en
Publication of JPS5940275A publication Critical patent/JPS5940275A/en
Publication of JPH0429983B2 publication Critical patent/JPH0429983B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26Testing of individual semiconductor devices
    • G01R31/2607Circuits therefor
    • G01R31/2608Circuits therefor for testing bipolar transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

PURPOSE:To calculate the collector loss of an output transistor so as to include a no-signal time, by such simple constitution that a preliminarily measured and stored colector loss value is read out. CONSTITUTION:The output voltage of an electric power amplifier 1 to which load is added through a switch 8 and an output terminal 2 is addressed through an A/D converter 3 and the memory part in a microcomputer 4 is accessed. In this case, the preliminarily measured and stored collector loss of the output transistor of the amplifier is read out to be outputted through a D/A converter 5. On the other hand, when a switch 8 is changed over to bring the amplifier 1 to a no-load state, the detection output of a no-load detector 7 comes to a control signal to read out the collector loss of the output transistor at the time of no- signal from the memory part of the computer 4 regardless of the output of the amplifier 1. By this method, the collector loss of the output transistor is calculated so as to include a no-signal time by simple constitution.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、電力増幅器における出力トランジスタのコレ
クタ損失を簡単に算出するとともに、スピーカ等の負荷
が切り離されているときは、電力増幅器の出力のいかん
にかかわらず、無信号時の出力トランジスタのコレクタ
損失が得られるようにしたコレクタ損出算出装置に関す
るものである。
[Detailed Description of the Invention] Industrial Application Field The present invention not only easily calculates the collector loss of an output transistor in a power amplifier, but also calculates the output of the power amplifier when a load such as a speaker is disconnected. Regardless, the present invention relates to a collector loss calculation device that can obtain the collector loss of an output transistor when there is no signal.

従来例の構成とその問題点 一般に出力段にSEPP(Single  Ended
Push  Pu1l)回路を備えた電力増幅器におい
ては、出力段のバイアス電流が出力トランジスタのコレ
クタ損失の変動により変動し、出方波形に歪を生ずる欠
点がある。
Conventional configurations and their problems Generally, SEPP (Single Ended) is used in the output stage.
A power amplifier equipped with a PushPull) circuit has the disadvantage that the output stage bias current fluctuates due to fluctuations in the collector loss of the output transistor, causing distortion in the output waveform.

発明の目的 本発明は簡単な構成でこのような出力トランジスタのコ
レクタ損失を求めることができるようにするとともに、
負荷が切り離されているときは、3 、・−・。
Purpose of the Invention The present invention makes it possible to determine the collector loss of such an output transistor with a simple configuration, and
When the load is disconnected, 3,...

電力増幅器のいかんにかかわらず、無信号時の出力トラ
ンジスタのコレクタ損失が得られるようにしたものであ
る。
Regardless of the power amplifier, the collector loss of the output transistor when there is no signal can be obtained.

発明の構成 本発明は電力増幅器の出力に対するコレクタ損失の変化
を予め記憶手段に記憶しておき、実際の出力を記憶手段
に入力し、入力された実際の出力に対応するコレクタ損
失を記憶手段から出力するようにしたものである。そし
て電力増幅器の出力端と負荷の間に挿入されたスイッチ
の開閉に連動して負荷検出手段により負荷の断続状態を
示す信号を出力し、この出力を記憶手段に入力し、負荷
が切り離されているときは、電力増幅器のいかんにかか
わらず、記憶手段に記憶した無信号時の出力トランジス
タのコレクタ損失を読み出すようにしたものである。
Structure of the Invention The present invention stores in advance the change in collector loss with respect to the output of a power amplifier in a storage means, inputs the actual output into the storage means, and stores the collector loss corresponding to the inputted actual output from the storage means. It is designed to be output. Then, in conjunction with the opening and closing of a switch inserted between the output terminal of the power amplifier and the load, the load detection means outputs a signal indicating the intermittent state of the load, and this output is input to the storage means, and the load is disconnected. When there is no signal, the collector loss of the output transistor at the time of no signal stored in the storage means is read out regardless of the power amplifier.

実施例の説明 図面は本発明の一実施例を示すものであり、1は5EE
P出力段をもつ電灯増幅器、2はスピーカ等の負荷に接
続される出力端子、3は電力増幅器1の出力電圧をディ
ジタル値に変換するA/D変換器、4は内部に記憶部を
有するマイクロコンピュータ、4a、4bはその入力ポ
ート及び出力ポート、5はマイクロコンピュータ4の出
力データを電圧に変換するD/A 変換器、6はその出
力端子である。7は負荷検出手段、7aはその一部を構
成する直流電源、8は電力増幅器1の出力端と負荷の接
続される端子2の間に挿入されたスイッチ8aと、直流
電源アaの出力端とマイクロコンピュータ4の入カポ−
)4cの間に挿入され、互に連動して切換わるスイッチ
である。
DESCRIPTION OF EMBODIMENTS The drawings show one embodiment of the present invention, and 1 is 5EE.
A lamp amplifier with a P output stage, 2 an output terminal connected to a load such as a speaker, 3 an A/D converter that converts the output voltage of the power amplifier 1 into a digital value, and 4 a microcomputer with an internal storage section. The computer, 4a and 4b are its input ports and output ports, 5 is a D/A converter that converts the output data of the microcomputer 4 into voltage, and 6 is its output terminal. 7 is a load detection means, 7a is a DC power supply forming a part thereof, 8 is a switch 8a inserted between the output terminal of the power amplifier 1 and the terminal 2 to which the load is connected, and the output terminal of the DC power supply a. and microcomputer 4 input capo.
) 4c and are switches that are switched in conjunction with each other.

次に、上記実施例の動作を説明する。Next, the operation of the above embodiment will be explained.

一般に、電力増幅器1の出力電圧に対するコレクタ損失
特性は、事前の測定により、たとえば第2図のように変
化することを知ることができる。
In general, it can be known from prior measurements that the collector loss characteristic with respect to the output voltage of the power amplifier 1 changes as shown in FIG. 2, for example.

そこで、これをたとえば第3図に示すように出力電圧を
○〜7の8つの電圧区間に分割し、各区間におけるコレ
クタ損失値を、第4図に示すようにマイクロコンピュー
タ4の記憶部の”○ooo”〜60111#の各アドレ
スに対応させてデータ5、・ 〜・ として記憶しておく。そして電力増幅器1の実際の出力
電圧をA/D 変換器3により4ビツト(厳密には3ピ
ントでよい)のディジタルデータv。
Therefore, the output voltage is divided into eight voltage sections from ○ to 7 as shown in FIG. 3, and the collector loss value in each section is stored in the memory section of the microcomputer 4 as shown in FIG. The data is stored as data 5, . The actual output voltage of the power amplifier 1 is converted into 4-bit (strictly speaking, 3 pins) digital data v by the A/D converter 3.

に変換し、このディジタルデータ■。を入力ボート4a
を介してマイクロコンピュータ4に入力し、これによっ
て記憶部のアドレスを指定して対応するコレクタ損失デ
ータP。を読み出す。このコレクタ損失データP0はD
/A 変換器6により電圧値に変換されて出力端子6に
出力される。これにより、電力増幅器1の出力電圧の変
化により変化する出力トランジスタのコレクタ損失の値
を常時とり出すことができる。したがってこのようにし
て得られたコレクタ損失値に応じてバイアス電圧を変化
させるようにすれば、出力段のアイドリンク電流の変動
を抑えることができる。
Convert this digital data into ■. Enter boat 4a
The data is input to the microcomputer 4 via the microcomputer 4, thereby specifying the address of the storage unit and the corresponding collector loss data P. Read out. This collector loss data P0 is D
/A It is converted into a voltage value by the converter 6 and output to the output terminal 6. Thereby, the value of the collector loss of the output transistor, which changes due to changes in the output voltage of the power amplifier 1, can be constantly extracted. Therefore, by changing the bias voltage according to the collector loss value obtained in this way, it is possible to suppress fluctuations in the idle link current of the output stage.

なお5以上はスイッチ8を切換えてスピーカを接続した
状態での動作であるが、スイッチ8によリスピー力を切
り離したときは、マイクロコンピュータ4の入カポ−)
4cに+vooが印加される。
Note that 5 and above operate with the speaker connected by switching the switch 8, but when the speaker power is disconnected by the switch 8, the input port of the microcomputer 4 is
+voo is applied to 4c.

このため、このときはマイクロコンピュータ4の6ベく
・ 制御により、電力増幅器1の出力電圧のいかんにかかわ
らず、無信号時のコレクタ損失(第3図の出力電圧区間
がo”のときのコレクタ損失)が読み出される。
Therefore, under the control of the microcomputer 4, regardless of the output voltage of the power amplifier 1, the collector loss when there is no signal (the collector loss when the output voltage section in Figure 3 is o'') loss) is read out.

なお、以上はすべて電圧値で動作させる場合について説
明したが、電流値で動作させるようにしてもよい。
In addition, although the case where the operation is performed using a voltage value has been described above, the operation may be performed using a current value.

発明の効果 本発明は記憶手段に予め出力電圧または出力電流に対応
したコレクタ損失値を記憶しておき、実際の出力電圧ま
たは出力電流を検出してこれを記憶手段に入力し、対応
するコレクタ損失値を読み出すようにしたものであるか
ら、簡単にしかも正確にコレクタ損失値を得ることがで
き、これに基づいて電力増幅器のバイアスを可変するよ
うにすれば、出力波形の歪を抑えることができる。しか
も本発明によれば、負荷を切り離した状態では、電力増
幅器の出力のいかんにかかわらず無信号時のコレクタ損
失を得ることができる。
Effects of the Invention The present invention stores the collector loss value corresponding to the output voltage or output current in the storage means in advance, detects the actual output voltage or output current, inputs it to the storage means, and stores the collector loss value corresponding to the output voltage or output current in advance. Since the value is read out, it is possible to easily and accurately obtain the collector loss value, and by varying the bias of the power amplifier based on this, distortion of the output waveform can be suppressed. . Moreover, according to the present invention, when the load is disconnected, the collector loss during no signal can be obtained regardless of the output of the power amplifier.

【図面の簡単な説明】[Brief explanation of the drawing]

7 /・−・ 第1図は本発明の一実施例のブロック図、第2図〜第5
図はその動作説明図である。 1・・・・・・電力増幅器、2・・・・・・出力端子、
3・・・・・・A/D 変換器、4・・・・・・マイク
ロコンピュータ、6・・・・・・D/A変換器、6・・
・・・・コレクタ損失値の出力端子。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第 
I 図 第2図 第3図 第5図
7/-- Figure 1 is a block diagram of an embodiment of the present invention, Figures 2 to 5
The figure is an explanatory diagram of the operation. 1...Power amplifier, 2...Output terminal,
3...A/D converter, 4...Microcomputer, 6...D/A converter, 6...
...Output terminal for collector loss value. Name of agent: Patent attorney Toshio Nakao and 1 other person
I Figure 2 Figure 3 Figure 5

Claims (1)

【特許請求の範囲】 電力増幅器の出力電圧または出力電流に対応する上記電
力増幅器の出力トランジスタのコレクタ損失の値を予め
記憶した記憶手段と、上記電力増幅器の実際の出力電圧
または出力電流を検出する出力検出手段と、上記電力増
幅器の出力端と負荷の間を開閉するスイッチに連動して
負荷の断続状態を示す信号を出力する負荷検出手段と、
上記記憶手段から出力されるコレクタ損失の値を電圧ま
たは電流信号として出力する手段とを備え、上記負荷検
出手段により検出された実際の出力電圧または出力電流
と上記負荷検出手段の出力とを上記記憶手段に入力し、
負荷が接続されているときは上記出力検出手段の出力に
対応するコレクタ損失の値を上記記憶手段から読み出し
、負荷が切り離されているときは上記出力検出手段の出
力のいかんにかかわらず、上記電力増幅器の出力電圧ま
た24・ 出力電流が○のときのコレクタ損失の値を読み出すよう
にしたコレクタ損失算出装置。
[Scope of Claims] Storage means that stores in advance the value of the collector loss of the output transistor of the power amplifier corresponding to the output voltage or output current of the power amplifier, and detecting the actual output voltage or output current of the power amplifier. output detection means, and load detection means that outputs a signal indicating an intermittent state of the load in conjunction with a switch that opens and closes between the output terminal of the power amplifier and the load;
means for outputting the value of the collector loss outputted from the storage means as a voltage or current signal, the actual output voltage or output current detected by the load detection means and the output of the load detection means are stored in the memory. Enter the means,
When a load is connected, the value of the collector loss corresponding to the output of the output detection means is read from the storage means, and when the load is disconnected, the above power is read out regardless of the output of the output detection means. A collector loss calculation device configured to read out the value of collector loss when the output voltage or output current of an amplifier is ○.
JP15219482A 1982-08-31 1982-08-31 Apparatus for calculating collector loss Granted JPS5940275A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15219482A JPS5940275A (en) 1982-08-31 1982-08-31 Apparatus for calculating collector loss

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15219482A JPS5940275A (en) 1982-08-31 1982-08-31 Apparatus for calculating collector loss

Publications (2)

Publication Number Publication Date
JPS5940275A true JPS5940275A (en) 1984-03-05
JPH0429983B2 JPH0429983B2 (en) 1992-05-20

Family

ID=15535111

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15219482A Granted JPS5940275A (en) 1982-08-31 1982-08-31 Apparatus for calculating collector loss

Country Status (1)

Country Link
JP (1) JPS5940275A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51144152A (en) * 1975-06-05 1976-12-10 Kikusui Denshi Kogyo Kk Power detector
JPS55122170A (en) * 1979-03-15 1980-09-19 Fujitsu Ltd Method of measuring lag time of integrated circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51144152A (en) * 1975-06-05 1976-12-10 Kikusui Denshi Kogyo Kk Power detector
JPS55122170A (en) * 1979-03-15 1980-09-19 Fujitsu Ltd Method of measuring lag time of integrated circuit

Also Published As

Publication number Publication date
JPH0429983B2 (en) 1992-05-20

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