JPS5932179A - Manufacture of solar battery - Google Patents

Manufacture of solar battery

Info

Publication number
JPS5932179A
JPS5932179A JP57143022A JP14302282A JPS5932179A JP S5932179 A JPS5932179 A JP S5932179A JP 57143022 A JP57143022 A JP 57143022A JP 14302282 A JP14302282 A JP 14302282A JP S5932179 A JPS5932179 A JP S5932179A
Authority
JP
Japan
Prior art keywords
layer
electrode
aluminum
back surface
paste
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57143022A
Other languages
Japanese (ja)
Other versions
JPH023310B2 (en
Inventor
Yuuji Tawara
裕滋 田原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hoxan Corp
Hokusan Co Ltd
Original Assignee
Hoxan Corp
Hokusan Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hoxan Corp, Hokusan Co Ltd filed Critical Hoxan Corp
Priority to JP57143022A priority Critical patent/JPS5932179A/en
Publication of JPS5932179A publication Critical patent/JPS5932179A/en
Publication of JPH023310B2 publication Critical patent/JPH023310B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

PURPOSE:To shorten the working time of manufacturing a solar battery and to reduce the cost of materials to be used by forming by baking a p<+> type layer after printing with aluminum paste and forming an aluminum back surface electrode of the aluminum paste layer. CONSTITUTION:An n<+> type layer which is covered with an Si oxidized film on the entire surface of a p type Si wafer by diffusing phosphorus or boron in the wafer. Then, the peripheral side part of the n<+> type layer is removed, and an aluminum layer A is printed on the back surface part of the n<+> type layer. Then, this is baked in the air. The aluminum paste is diffused in the p type layer of the Si wafer by this baking, a p<+> type layer is formed, and a back surface field which becomes an n<+>-P-P<+> type junction is advanced. In this manner, an aluminum back surface electrode A' with the layer A remains adjacent to the p<+> type layer. In this case, an aluminum passage oxidized layer A'' is formed on the surface of the electrode A'. Subsequently, this is etched with HF, an SiO2 layer is removed, and the layer A'' is also removed. Then, a surface electrode B is formed on the exposed surface.

Description

【発明の詳細な説明】 本発明はｌ）型シリコンウェハによって、１１４Ｐ　　
１）−１接合とした入隅′ＩＩＬ／ｌｌＩケ製造４−る
ための方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention provides 114P
1) It relates to a method for manufacturing an inner corner 'IIL/llI' which is a -1 joint.

従来から効率のよいＢ　Ｓ　Ｆ　（１’１ａｃｋ　５ｕ
ｒｆａｃｅＦｉｅｌｃｌ　）化された太陽電池が用いら
れているが、との種電池の製造は、次の如き１稈を経て
実施されている。Traditionally efficient B S F (1'1ack 5u
rfaceFielcl) solar cells are used, but the production of seed cells is carried out through one culm as follows.

すなわちＯ５１図の１．、稈説、明図か示す通り、先４
゛（イ）の１４１　＜　ｍ　、ＧされたＰ型シリコンウ
ェハにダＪし既′ｆ−１１のり１１り燐等を拡散さぜる
ことにより、（ロ）のようにＰ型シリコンウェハの全表
面にｎ”層乞Ｊ［モ成し７１　Ｐ　＋＋　’　　接合を
得るが、この際１１　”層はシリコン酸化膜に上って覆
われている０次１仁１”、　ｉｌｔ＋　）拡ｉｉｋ済Ｉ
）型シリコンウェハにおける裏面および１０１１面部分
の０４　層を除ノｌ−るのであるが、このためには当該
ｎ　＋？ｊに１１１４酸性レジス１インクをイ゛ノ２（
」μｍｎ１１・ざＪ７７稈たけスクリーン印１１ｉｌＩ
　Ｌ　−Ｃ”ｊ’ｔ、　ｔ’４さナタ後、ＩＩ　Ｆ−Ｉ
ｔ　Ｎ　０３１ｆ＋Ｗ、’、カＩＩ　Ｆ−１１Ｎ（Ｊ、
、　−ＣＩ１３　Ｃ００ＩＩ溶Ｑ　Ｉｃ　テゴノ千７グ
処理ずろが、研磨紙１仁よる機械研磨″！（１＋ｉｌｉ
すように１．て第２す、がくして同図ｅ・）の如きく、
σ〕か？！）ｒ嘗１ろ。In other words, 1 in diagram O51. , culm theory, as shown in the clear diagram, first 4
゛(A) 141 < m, by dipping onto the G-treated P-type silicon wafer and diffusing phosphorus, etc., the entire P-type silicon wafer as shown in (B). An n'' layer is formed on the surface to obtain a junction, but at this time the 11'' layer is covered by a silicon oxide film of 0th order 1'', ilt+) expanded I
) type silicon wafer, the 04 layer on the back surface and the 1011 side portion is removed, but for this purpose, the n+? Add 1114 Acid Resist 1 ink to Ino 2 (
”μmn11・zaJ77 culm screen mark 11ilI
L -C"j't, after t'4, II F-I
t N 031f+W,', Ka II F-11N (J,
, -CI13 C00II Melting Q Ic Tegono 1,700g process is mechanically polished with 1 layer of abrasive paper''! (1+ili
1. The second step is as shown in the same figure (e).
σ〕? ! )r嘗1ro.

次にＩ：　Ｈｊ：のもグ月仁つき、表面側におζプるシ
リ＝＋　＞酸化１１’Ｊ　％：　Ｉｆ　Ｆ　ｒこよりエ
ツチング処理［−て、これ４除去した後、そのＰ層裏面
側にＡ１７／ｆ、着ｈ’ｉ　ｔｌ）　’ｚ同図の使）に
示す通り１′（空蒸着により形成し、これを空気中にて
１．ｌ’Ａ成することで、当該へｌ、を１）層に（広１
１にさせ、これ１こよってＰＦ層を形成してｎ”　　Ｐ
　　Ｉ）→接合とする１３３　Ｆ化処理を行なうのであ
る。Next, I: Hj: Nomoguzuki etched, zeta on the surface = + > Oxidation 11'J A17/f on the side, attached h'i tl) 'z As shown in the same figure, 1' (formed by empty evaporation, and by forming 1.l'A in air, l' , into 1) layer (wide 1
1 and form a PF layer by this 1 to form n”P
I) → 133 F conversion treatment is performed.

上記１（Ｓ　Ｊ”化処理により１．１１層の裏面に０４
１着残存し、た（へ）に示すＡｔ−酸化１１Ｓ！　＋２
１を、ｔｌ　Ｃｔ　。04 on the back side of the 1.11 layer by the above 1 (S J” processing)
One piece remained, At-oxidized 11S shown in ta(f)! +2
1, tl Ct.

Ｎ　ａ　ＯＨ溶ｆ１．＋仁より除去して（１・）の状態
とな１２、次て（チウ（ｌ刀に示す通り、真空蒸着法に
よってＰ＋層にはｉ’ｉ　−Ｐｄ−ＡｇまたはＴｉ−Ａ
ｇによる裏面電極（３）を・　ｎ＋層には１’ｉ−Ａｇ
による表面電極（４）を形成し、さらに要すれば両′市
極ｆ３１　＋４１１こ、プイノビングによろハンダ層（
！’ｉｌ　＋５１　’　を被着すると共に、表面？！ｆ
　４ｉｆｉ　ｆ４ｒにはさらに反射防電１１か（６）を
被装することになる。N a OH solution f1. The P+ layer is removed by vacuum evaporation to form a state of (1・).
1'i-Ag for the n+ layer.
If necessary, form a surface electrode (4) by applying a solder layer (
! As well as applying 'il +51', the surface? ! f
4ifi f4r will be further coated with reflective protection 11(6).

このように、−上記（ＤＡｔ蒸着１ｃ」：るｎ　Ｓ　ｌ
”化人陽電池の製造方法番こよれば、■］型シリコンウ
ェハの拡散処理により得られた。−Ｉ一層につき、その
裏面部分の全面にわたって、これを除去した後、Ｂ１１
−化処理を行なうから、当該除ノミ作業に可成りの労力
と時間とを明することＮなり、４ｒｃ１１Ｆ工７チング
処理と１ｌｃＡ４；Ｑ：はＮａ０１１による処理を夫々
施さねばならないだけでなく、別途Δｇｊ−用いて１１
１極をＬｉＸ空蒸着するため、このためにも相当の作Ｓ
’ｓ　ｌｌ＆　１ｉＪｌ　’；ｚ　′Ｊ”ｊ、　Ｌ、か
つ使用資１’　１．高６１１１につくため、太陽電池の
安６１１１な提供ができ斤い欠陥があ７、。Thus, - the above (DAt evaporation 1c': n S l
According to the manufacturing method of ``Kajin solar cell,'' it was obtained by diffusion treatment of a type silicon wafer.
Since the flea removal process requires considerable effort and time, 4rc11F and 1lcA4;Q: not only have to be treated with Na011, but also separately. Δgj-using 11
Since one pole is vacuum-deposited with LiX, a considerable amount of work is required for this purpose.
's ll & 1iJl '; z 'J"j, L, and used resources 1' 1. Due to the height of 6111, there are defects that prevent us from providing solar cells at a cheap price7.

これに対し０′１２図の１稈説明図に示す、ＡＩベース
トを用いたＢＳＦ化太陽ＷＬ池の製ヌ省方法（ｉ、ＩＩ
”　ｉｆｆ：　）７法の難点をｌ」成り改善し得るもの
となっている。On the other hand, the method for manufacturing a BSF solar WL pond using AI base (i, II
``if: )'' The disadvantages of the 7 methods can be improved.

１なわら同θくでは、（イ）（Ｉ：Ｉ）か前記方法の（
イ）（ロ）と１゛＜同じであり、次にｌｌ’ｉｌ　ｌ１
１１Ｘ１〜分の＋１１゛層のみ丘除ノ、してｅうｑ）　
ＩＪいくなし、ｌ欠に１１　Ｆエツチングに」、り表裏
面のツリー１ン酸化暎を除去し７た（二）に対し、−Ｃ
１その裏面ｌｌｌ１目こＡｔベース）・層（１）′　を
スクリーン印ｂｉｌｌ　して（ホ）のｔｉｌ＋　＜なし
、当該ベース１の溶媒を千備１１１１熱により蒸発させ
た後、空気中にて填：ＩＩ９．するのである。1, but in the same θ, (I) (I:I) or (I) of the above method.
A) (B) and 1゛< are the same, then ll'il l1
11X1~min +11゛ layer only hill removed, then euq)
In contrast to (2), which removed the tree oxidation on the front and back surfaces, -C
1. On the back side of the base 1), screen mark the layer (1)' and til + <None. After evaporating the solvent of the base 1 with Senbi 1111 heat, fill it in air. :II9. That's what I do.

この焼成処理によって、Ａｔペーストは裏面１１＋ｌｌ
　ノｎ　’　層を突き破ってＩ）型シリコンウェハの１
）層に拡１１（シて７Ｊき、この結果同図（へ）に示す
通り、Ｉ’１ＩＶｉ＋仁隣接１−、た１トド層を形成す
ることができるのであり、このようにしてｎ”’　Ｐ　
　Ｉ’＋接合となるＴ３　Ｓ　ｌ・”化処理を進行させ
、この際Ｔ、）　−１層の面にはＡ、　１ペー　スト酸
化層（２１′　が形成される０ 次でこのΔｔペースト酸化層（２１′　　をＩＩ　（：
　ｔ、Ｎａ０１１溶液にて除去し、得られた（１・）に
７１シて、￥５面屯極ｆ３１’　、表面？ｌ（極ｔ４１
’、ハンダ層ｔｒ＋＃　ｔｒ、＋／／／そして反射時１
１１模（６）′が形成されて行く（勇（ＩＪｌＧ）の１
稈は１）ｉＩ記ＪＪ法と同］２である。By this baking process, the At paste becomes 11+ll on the back side.
1 of the I) type silicon wafer by breaking through the non' layer.
) layer is expanded by 7J, and as a result, as shown in the same figure (f), it is possible to form a layer of I'1IVi + adjacent 1-, t1, and in this way n"' P
At this time, this Δt paste oxidation process is carried out to form an I'+ junction, and this Δt paste oxidation layer (21') is formed on the surface of the T,)-1 layer. Layer (21' to II (:
t, removed with Na011 solution, 71 points on the obtained (1.), ¥5 surface polarity f31', surface? l (pole t41
', solder layer tr+# tr, +/// and 1 when reflected
11 models (6)' are formed (Yu (IJlG)'s 1
The culm is 1) iI same as JJ method] 2.

−［、記のＡ、　ｔペーヌトによるＢ　Ｓ＋”化入隅電
池の製造によｉｌげ、Ａｉｌ方法の如＜ｎ”　　層の＃
！’ｎ１部分除にＬ稈が省略され、これにより可成りそ
の一作猶時間を短縮することができるもの＼、や（ｉす
５Ｉ０２の除去とＡｔペ−〕１酸重層化２１′　の除去
とが必要であるだけでなく、Ａｇ、Ｔｉ−Ａｇ′４ｆを
用いての電極形成が不可欠であるため、作急性の向にに
も限度があり、かつ屯イ販ｊ１ぞ成のために貴金属が用
いられるため前価な入隅’ｆｌＬ　ｉｆｆとなる点につ
いての改善（、、ｔなされていない。- [, A of the above, according to the production of B S+'' layer cells by t paint, # of the <n'' layer according to the Ail method.
! The L culm is omitted in the 'n1 partial removal, which can considerably shorten the time required for one crop. Not only is it necessary, but it is also essential to form electrodes using Ag or Ti-Ag'4f, so there is a limit to how quickly they can be made, and precious metals are not used for the purpose of local sales. Improvements have not been made regarding the point where the input corner 'flLiff' becomes a predetermined value.

本発明は上記の如き問題点に忽み、Ａｔべ−スト印刷後
の焼成処理によって、Ｉ）十層を形成すると共に、当該
Ａｔペースト尼１によってＡｔ。In view of the above-mentioned problems, the present invention forms 1) 10 layers by a firing process after At base printing, and at the same time, the At paste layer 1 forms At.

裏面宙、極が１１６成されるようにし、しがも、ノリー
ｒン酸化ＩＦ・３とＡｔペースト酸化層の除去を同時（
Ｃ？１ない？ＩＦるようにして、１１１記従来法の介意
を解消し、ようとするもので、その！待機とするところ
は、１１７（４）シリ７ンウェハに対して燐等（こよる
１広ｆｔ’＜り匹丁甲褒Ｊ＋ｉ！ｉずこと（こより、当
月１ンエハの全表面にノリーＩン酸化１１％’ｊでＤゎ
〕したｎ　”　層５：）ヒ成１〜、当該「１）層の周側
部分を除ノてして、同Ｉ＋　”層の裏面部分にＡｔベー
ストを印１１１すし、これを′；３気中にて焼１ｊ’２
．することにより、Ａｔベーストを、シリ−ノン酸化＋
１ｔｔＨ１１１罎−Ｐｉの裏面部分から前記ｌｌ型シリ
：７ンウエハの１１層に拡１１（させ■臼層をＩｔｅ　
；Ｉｖ、　、ｌ　Ｚ、　ｃ　トＴ、１１１１）Ｉ）Ｉ　
接合とするＩ（Ｓｔ”化処理％ｈ？＋“ない、仁れによ
ってＰ＋層に４１着されたＭ記Ａ　／−ペーフ日仁よる
Ａｔ裏面電極を残仔彫成ぜ１７め、次にこれを弗化水素
溶液にてエツチング処Ｊｌｐ　、−４ろこと（（Ｌす、
−１Ｌ記八を裏面電極４７）　４５面に１１（成さＪｌ
ているＡｔペースト酸化層と、ｎ１１記シリ：ｊン酸化
膜とを除去して、当該Ａｔ裏面電極と１１−ト層の表ｎ
＋ｉ　ｉ“ｉ１Ｘ分を一箸Ｖさせ、当該表面１１１５分
（仁は表面屯４ｉ＠を常法に上り形成１することにある
。On the back side, the electrode was formed at 116, and the Noreen oxidation IF-3 and the At paste oxide layer were removed at the same time (
C? Isn't there 1? This is an attempt to eliminate the intervention of the conventional law in Article 111 by making it IF. On standby, 117 (4) silicon 7 wafers are oxidized with phosphorus, etc. n'' layer 5 with Dゎ] of 11%'j:) Remove the peripheral part of the layer 1~, and mark the At base on the back side of the layer 111. , Bake this in the air for 1j'2
．． By doing so, the At base is converted into silicon-non oxidized +
1ttH111 - Expand the 11 layer from the back side of the Pi to the 11 layers of the 7-inch wafer.
;Iv, ,l Z, c トT, 1111)I)I
I (St) processing to be bonded %h? was etched with a hydrogen fluoride solution.
-1L record 8 to back electrode 47) 11 (made Jl) to 45th side
The At paste oxide layer and the silicon oxide film of n11 are removed, and the At back electrode and the surface of the 11-t layer are removed.
+i i "i1X minute is made one chopstick V, and the said surface 1115 minutes (Jin is to climb the surface tun 4i@ in the usual manner and form 1.

本発明を１１３３図に示ずＬ稈説明図Ｃ仁よってｌｉＴ
細ｔ細説Ｃ説示ば、例えば同図（イ）の妬く直径３イン
チ、厚す：（ＯＯμｎ＋ｓｌΩαのｌｌ型シリコンウェ
ハを用ａル、従来例の如く燐拡散に上って同図（に）の
よ月こ、当該ウェハの↑而にゎたり１１＋層を形成する
のであり、この際形成さｉまたｎ＋ｆｌの面抵抗は５ｏ
Ω、／、　　、　Ｉ￥さは０２μ？？＋であった。The present invention is not shown in Figure 1133, but is shown in Figure 1.
For example, using a silicon wafer with a diameter of 3 inches and a thickness of (OOμn+slΩα) as shown in the same figure (A), phosphorus is diffused as in the conventional example. Noyotsuki forms an 11+ layer on the ↑ side of the wafer, and at this time, the sheet resistance of the formed layer i and n+fl is 5o.
Ω、／、、I￥さは02μ? ? It was +.

イして上記拡１枚処理により、そのｎ’　Ｉ（’Ｉｉは
５１０２であるシリコン酸化ｈ′つにより覆ゎ）するこ
と＼なるが、次１．稈では当該１’ｌ　’１　　層の周
側部分だけを従来例と同じく化学エツチング、柄挿研磨
等の１段により除去し、て、同図（）うの状態とする。Then, by the above-mentioned enlarging process, the n'I ('Ii is covered with silicon oxide h' which is 5102) is formed, but the following 1. In the culm, only the circumferential portion of the 1'l'1 layer is removed by one step of chemical etching, handle polishing, etc., as in the conventional example, resulting in the state shown in FIG.

さらにに）に示ず［稈番こあって、ｎ”Ｋの裏面部分す
なわち、そのシリコン酸化層面にＡｔペースト層Ａを、
スクリーン印刷するのであるが、このν□１１１Ｊ２川
したす１該ベースＩ・としては、２００〜３００メツシ
ユの−ｆルミニウム粉であす、印１１ｉ！ｌにより？：
ｔらｉ？たぞのｌｂ２１ｒｆｉｔ　８０〜］　２０μｍ
と＋ｉＪ戒りｊワく形成しておき、印１１ｉ１１後は２
００℃程度で１０〜１５分間、予備ＩＪ１１熱すること
で溶媒を蒸発させておく。Furthermore, (not shown in ) [there is an At paste layer A on the back surface of n''K, that is, on the silicon oxide layer surface,
I am going to screen print this ν□111J2 River Shitasu 1 The base I is 200 to 300 mesh of -f luminium powder, marked 11i! By l? :
tra i? Tazo's lb21rfit 80~] 20μm
And +iJ commandment jwawa form, after mark 11i11 is 2
The solvent is evaporated by heating the preliminary IJ11 at about 00°C for 10 to 15 minutes.

さらに１−記のものを、空気中にて８２５℃〜８７５℃
の温度、望ましくは８５０℃にて４〜６分間焼成ずろ〇 この焼成１７．ｌｊ処理こよって、Ａ　／、ベース］・
は裏面部 ０）１１に１３ける５ｉ０２、ｎ　　層を突き破って、
■）欅」シリ：１ンウエハのＰ層に拡散して行き、この
結束同図の（ホ）ＩＣｉＪｔ　’４−通り、Ｐ層に隣接
したＰ　＋に’ｉ　Ｓ：　１１４１にづ−るこｈができ
るのであり、かくして１１１１・　（ン　接合と斤る１
３　Ｓ　Ｆ化処理が４Ａ行するが、本発明てはＡｔペー
スト層Ａが、すべて１１８　Ｆ　ｆじに消費されてしオ
うのではなく、Ｐ＋層に隣接してへｔベース１層へによ
るＡｔ裏面電極Δ′が残存形１）見されるのであり、こ
の際Ａｔ裏面電極Ａ′の面にはＡｔべ〜スト酸化層Δ“
が形成さｉする。Furthermore, 825°C to 875°C in the air
17. Baking at a temperature of 4 to 6 minutes, preferably 850°C. Due to lj processing, A/, base]・
Breaks through the back surface 0) 11 to 13 5i02, n layer,
■) Keyaki's silicon: Diffuses into the P layer of the 1-n wafer, and as shown in the same figure, it spreads to the P + adjacent to the P layer as shown in the same figure. Thus, 1111.
3 SF processing is performed in 4A rows, but in the present invention, the At paste layer A is not completely consumed as 118 F f, but is instead consumed in one layer adjacent to the P+ layer. The At back electrode Δ' can be seen in the residual form 1), and at this time, an At base oxide layer Δ" is formed on the surface of the At back electrode A'.
is formed.

次に上記の（ホ）につきｒｔ　ト’エツチング処理を施
すのであるが、これには５０％の弗化水素水溶液に約１
０分間浸漬すればよく、当該処理により表面側のＳｉＯ
□　と裏面側に残存するＳｉＯ□とがｌｌ′Ｉ！失され
るだけでなく、Ａｔは両性金属で酸、アルカリの双方と
灰地、するから、ＩＩ　Ｐ＋こ」、すΔＬベースト酸化
層Ａ”も除去されることになる。Next, regarding (e) above, an RT etching process is performed, which involves adding approximately 1.
It is sufficient to immerse for 0 minutes, and this treatment removes the SiO on the surface side.
□ and SiO□ remaining on the back side are ll'I! In addition to being removed, since At is an amphoteric metal and reacts with both acids and alkalis, the oxide layer based on ΔL is also removed.

面上記エツチング処理によるＡ４ペースト酸化層Ａ　”
の除去を、より完全なものとするたぬ、さらに約５分間
稈度超？１波洗浄処理を行なうようにするのが望ましく
、これによってＡｔ裏面１１極八′の面と１１−１　層
の表面部分にあ・（Ｊる而とが謹聴され、（へ）−こ示
ずものが得られる。A4 paste oxide layer A” by etching process above the surface
To make the removal more complete, leave the culm for about 5 minutes. It is desirable to perform a single-wave cleaning process, so that the surface of the At back surface 11 pole 8' and the surface area of the layer 11-1 are carefully cleaned, and the You can get something.

次で」−記ｎ　”層の表面部分に、常法に↓す１’　ｉ
　−Ａ　ｇによる表面電極１３を形成し、さらに図示例
では、Ａｔ裏面亀＠Ａ’　と表面電極１３とに鍍金属ｃ
、ｃ’　を夫々施すようにしており、こハ、にはバッグ
メツ”ｔ、Ｚｎゾソキ、ＳｎメツＡ雪かｂｆ滴で１Ｖ、
す、ハングメ゛ツキをｈ（口せハＡｔ裏面電極の＋ｌ１
ｉｌ　ｆｌ’！−１’ｉ　ｉ向十できるとｊ＋、に、直
列抵ｌＩ＋５−・１・さくてき、７，１１メツキの場合
には、さらに＋ＴＩ＋４候性を１着火Ｌ　ＴＯること＼
な粋、Ｓ　ｎメッキで＋：ｉバッグ（１１−１かｂ１能
ｌため太陽電池の接続時（Ｃ１その作！ｉ４　（’１．
がよくなる。Next, write 1'i on the surface of the layer in the usual manner.
-A surface electrode 13 is formed by A g, and furthermore, in the illustrated example, the At back surface @A' and the surface electrode 13 are plated with metal c.
, c' are applied respectively, and in this case, 1V is applied with bag mettsu't, Zn soki, Sn mettsu A snow or bf drops,
Then, set the hang plate to +l1 of the back electrode.
il fl'! -1'i If it is possible to move towards i, then to j+, the series resistor lI+5-・1・cut, and in the case of 7,11 plating, further add +TI+4 weatherability to 1 ignition L TO＼
Nice, S n plating +: i bag (11-1 or b1 function) when connecting solar cells (C1 work! i4 ('1.
gets better.

尚表面’Ｈ’ｈ　＋４　＋３についてはｉ）（全処理で
はなく、−Ｙイ、ノビン法（こよりハンダを（１着でき
乙ので、回ｆＪぐ＋ｒ−Ｊ−リハ７・ダ１Ａ７ｉ　’；
７形成４−ろ、にうにしで噂、よく、さ１−１ｉｃ・仔
９ｙに１芯［５従来法と同１つく表面電極１λにｊｉ　
”、ｔｔ防＋ｔ、　ｌｊ’、＋４　ｌ）　ｆ　１１ｉｃ
ずようにし妹ものか、同図（ト）（こ７Ｉ：されている
。As for the surface 'H'h +4 +3, i) (not all processing, -Y, Novin method (soldering from this) (because one piece can be soldered, 1A7i');
Rumor has it that 7 formation 4-ro, 2 sea urchins, 1 core for 1-1ic, 1 core for 9y [5 same as the conventional method, 1 surface electrode 1λ for ji]
", tt defense + t, lj', +4 l) f 11ic
Is it a younger sister or something like that?

奉イ色明け１−ふ：　ｆＤ　ｉ屯り、Ａｔペースト層八
へＳ　ｌ（，１２のｌ二からＩｔ　−ｉ　　層（こ印刷
して焼］ｙ、するようｂＴ、　Ｌ斤から、広い而Ｊｕｌ
にわたってのＩＩ−’層のドロア去１稈をイて要に−４
ろことができ、これ（こよつでｉｉｊ成ｌ）のイ′ｌｌ
！ｌ′、時間台′ｆ５．−縮できるだ（・Ｊでなく、Ｉ
Ｑ　＋＋７．によるＨ　Ｓ　ｔ’化処理を施すことに１
つτｐＨ，・ｉ　％：　ｉｊ）ると同時に、Δｌ裏面Ｔ
往極Ａ′忙も形成してし１つようにしたから、改めてＡ
ｇ。1-F: From fD i to At paste layer 8, S l (, 12 l2 to It -i layer (print and bake) y, so that bT, from L loaf, wide Jul
After removing the 1st culm of the II-' layer, the main point is -4.
I'll be able to do this, and I'll be able to do this.
! l', timetable'f5. -It can be reduced (I, not J)
Q++7. 1 to perform H S t' processing by
τpH,・i %: ij) At the same time, Δl back surface T
Since I had already formed the last A′ busy, I decided to write A again.
g.

ＴｉＡｇ等＋１．１：　／：＋　ｎｉ　ｆｉ＋７）　７
ｉ　Ｍ　Ｉ稈’ｆｒ：　Ｊｉｌｆｊ　ス’ＩＩ　９もな
くなり、この結果作業時間の短縮はもとより、使用され
る質相からも、その（Ｒ：　＋ｊｌ−化を図ることかで
きろ。TiAg etc.+1.1: /:+ ni fi+7) 7
i M I culm'fr: Jilfj Su'II 9 will also be eliminated, and as a result, not only will the work time be shortened, but also from the quality used, it will be possible to make it (R: +jl-).

さら１こまたＳ　ｉ　Ｏ□　とＡ１ベースＩ・榮″化層
Ａ　”との除九をＩＩ　Ｆにより　・度にＴｉなうより
にしたので、この点からも作業１−稈の簡易化と能率向
上が実現できること＼なり、実際−）〕第１図の方法Ｉ
Ｃよるときは４０枚７２時間：ろ０分、弔２１ン１０ノ
５法では４０枚、／１時間のｔｔ（・１であったものか
、４０枚／　：３０分となった０ また本発明によって得られた製品につき、その　ｌ−Ｖ
　’に性力＼ら、　その’Ｄ、）　４’６　Ｉｕ　Ｍｌ
、　開１ｊＫ　’ｔ’ｌｆ、　ｌｊ−、％求めｔところ
、Ｆ表のη＋１＜第２図のＪ〕法による製品よりく５、
優れた特性を示し、また１、稈の１′簡略化（こも拘ら
ず第１図の方法による製品と同℃もしくはそれり−１−
の結果を得ることかできたＯ尚ｉ）ｉｊ記したノ・ンダ
鍍金１Ｃ」、りへｌ裏面電極をジノル［７たものにつき
、９０℃、湿度１　（１（１％による（ｉ１頼性試験ｆ
、　２００時間行なった結果、異常は認められなかった
。In addition, the division of S i O Efficiency improvement can be achieved ＼Actually-)〕Method I in Figure 1
According to C, 40 sheets 72 hours: 0 minutes, in the funeral 21-10-5 method, 40 sheets, / 1 hour tt (・1, 40 sheets / : 30 minutes 0. For the product obtained by the invention, its l-V
'ni sexual power\ra, so'D,) 4'6 Iu Ml
, Open 1jK 't'lf, lj-, % tWhere, from the product by the method η+1 in F table <J in Figure 2] 5,
It exhibits excellent properties, and also 1. 1' simplification of the culm (despite this, the temperature is the same or lower than that of the product produced by the method shown in Figure 1).
I was able to obtain the results of the following results.I) The back electrode was heated to 90°C and the humidity was 1% (by 1% (i1 reliability). exam f
After 200 hours of testing, no abnormalities were found.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はＡ　／、　ｌ’！空蒸Ｈ＋コ、ｔ：るＢ　Ｓ　
Ｆ化’ｒ’　ｉ　−Ａｇ　７１を極入隅ｉ１ｉ、池の製
造ｌ稈説明図、第２図はへＬベースト印１１ｉ１１１こ
↓る＋３８　＋”化”Ｌ’　ｉ　−Ａ　ｇ電イ七太陽電
池の製造１．稈説明図、第：３図は本発明ｉｃ係る太陽
電池の製造Ｉ稈説明図である〇八　・・・・・Δｔベー
スｌ一層 Ａ′　・・・・・Ａ、　を裏面？ｌＨｆ１Ａ″　・−・
−・Ａｔペースト酸化１１／ｉ■３　　・・・・・表面
電極 特許出願人 代理人　弁理１　　月　爪６　　　誠 第１図　　　第２図 第３図 ３９５−Figure 1 shows A/, l'! Air steam H + Ko, t:ru B S
F conversion 'r' i -Ag 71 is placed in the corner i1i, Pond production l culm explanatory diagram, Figure 2 is L base mark 11i111 ↓ + 38 + "Cation"L' i -A g electric seven suns Manufacturing of batteries 1. Culm explanatory diagram, Figure 3 is an explanatory diagram of I culm for manufacturing a solar cell according to the present invention. lHf1A″・−・
-・At paste oxidation 11/i■3...Surface electrode patent applicant's attorney Patent attorney 1 Month Nail 6 Makoto Fig. 1 Fig. 2 Fig. 3 395-

Claims (1)

【特許請求の範囲】 （ＩＩ　　＋１　＋ｌｌ＋＋シリニ］ンウ「ハ（こ燐、
ボロン等による拡１１（処理をＩｊｉｌｉずこと１仁よ
り、当該ウェハの全表面にシリコン酸化１１≧で伯われ
た１１＋層を形成し、当該■１一層の周側部分を除去し
て、同１１１層の裏面部分子こＡｔペーストを印１６す
し、これを空気中（こて焼成することにより、Ａｔペ−
］ｌｔシリコン酸化膜、１１１　　層の裏面部分から前
記“１）型シリコンウェハのＰ層に拡散さぜ１）１　　
層’ｔｌ杉１況することで、ロー１−　　ｐ　　ｐ　ト
接合とする＋３　Ｓ　Ｆ比処理を行ない、これに上ッテ
ｌ”−’　層に１１着された前記Ａｔペーストニ」、る
Δｌ裏面電極を残存形成せしめ、次にこｆＬ、％：弗化
水素溶７１々にてエッヂング処理することにより、ヒ記
Ａ、　を裏面電極の表面に形成さ：ｈ　テイルへｌベー
スｉ・酸化病と、前記シリコン酸化１トキとを除ノ、し
て、当該Ａｔ裏面電イ賑とを常法に５しり形成したこと
を特徴とする太陽電池の製造１ノ法。 （２）　　弗化水累溶１（１，＋こよろエソイング処理
の後に、Ｊ、７１音波洗滌を施して、Ａｔベース１酸化
層の除去を補完させるよりにしたことを４’！ｌ′徴と
する特＋ｉ’Ｆ　、ｌｌＩ！求の範囲第１項記載の太陽
１１１．池の製Ｊ２ｒ力法。 ＋３１ＡＡ裏面電極に、ハンダ、Ｚｎ、Ｓ　ｎ等による
鍍金処理が施される特ｉ′１．！Ｉ１１求の範囲；１〜
１項記載の太陽電池の製造方法。[Scope of Claims] (II +1 +ll++Sirini)
An enlarged 11+ layer with silicon oxide 11≧ is formed on the entire surface of the wafer using boron, etc., and the peripheral part of the 11 layer is removed. Mark 16 pieces of molecular At paste on the back side of the layer and heat it in the air (by firing it with a trowel).
]lt silicon oxide film, 111 Diffusion from the back side of the layer to the P layer of the "1) type silicon wafer1)1
By forming the first layer, a +3 SF ratio treatment is performed to form a low 1-pp joint, and on top of this, the above-mentioned At paste is applied to the 11th layer, and the back surface of the Δl After the electrode is formed and then etched with a hydrogen fluoride solution, marks A and A are formed on the surface of the back electrode. , the silicon oxide layer is removed, and the At back surface electrode layer is formed in a conventional manner. (2) After the fluoride water cumulative solution 1 (1, + Koyoro Esoing treatment), J, 71 sonic cleaning was performed to complement the removal of the At-based 1 oxide layer. The special +i'F, llI! Range of requirements The Taiyo 111. Ike's J2r force method described in item 1. The special i'1 where the +31AA back electrode is plated with solder, Zn, Sn, etc. .!I11 Search range; 1~
A method for manufacturing a solar cell according to item 1.
JP57143022A 1982-08-18 1982-08-18 Manufacture of solar battery Granted JPS5932179A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57143022A JPS5932179A (en) 1982-08-18 1982-08-18 Manufacture of solar battery

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57143022A JPS5932179A (en) 1982-08-18 1982-08-18 Manufacture of solar battery

Publications (2)

Publication Number Publication Date
JPS5932179A true JPS5932179A (en) 1984-02-21
JPH023310B2 JPH023310B2 (en) 1990-01-23

Family

ID=15329094

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57143022A Granted JPS5932179A (en) 1982-08-18 1982-08-18 Manufacture of solar battery

Country Status (1)

Country Link
JP (1) JPS5932179A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4703553A (en) * 1986-06-16 1987-11-03 Spectrolab, Inc. Drive through doping process for manufacturing low back surface recombination solar cells
DE19758712B4 (en) * 1996-12-20 2007-02-15 Mitsubishi Denki K.K. Silicon solar cell or semiconductor device production - involves electrical separation of p-n junction using glass-based material
JP2007201007A (en) * 2006-01-24 2007-08-09 Sharp Corp Photoelectric conversion element
EP1906455A1 (en) * 2005-06-22 2008-04-02 Kyocera Corporation Solar cell element and solar cell element manufacturing method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4703553A (en) * 1986-06-16 1987-11-03 Spectrolab, Inc. Drive through doping process for manufacturing low back surface recombination solar cells
DE19758712B4 (en) * 1996-12-20 2007-02-15 Mitsubishi Denki K.K. Silicon solar cell or semiconductor device production - involves electrical separation of p-n junction using glass-based material
EP1906455A1 (en) * 2005-06-22 2008-04-02 Kyocera Corporation Solar cell element and solar cell element manufacturing method
EP1906455A4 (en) * 2005-06-22 2010-12-01 Kyocera Corp Solar cell element and solar cell element manufacturing method
JP2007201007A (en) * 2006-01-24 2007-08-09 Sharp Corp Photoelectric conversion element

Also Published As

Publication number Publication date
JPH023310B2 (en) 1990-01-23

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