JPS5848420A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5848420A
JPS5848420A JP56146910A JP14691081A JPS5848420A JP S5848420 A JPS5848420 A JP S5848420A JP 56146910 A JP56146910 A JP 56146910A JP 14691081 A JP14691081 A JP 14691081A JP S5848420 A JPS5848420 A JP S5848420A
Authority
JP
Japan
Prior art keywords
layer
soldering
dissolved
heat
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56146910A
Other languages
Japanese (ja)
Inventor
Yasushi Nakamura
靖 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Home Electronics Ltd
NEC Corp
Original Assignee
NEC Home Electronics Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Home Electronics Ltd, Nippon Electric Co Ltd filed Critical NEC Home Electronics Ltd
Priority to JP56146910A priority Critical patent/JPS5848420A/en
Publication of JPS5848420A publication Critical patent/JPS5848420A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Abstract

PURPOSE:To easily and economically obtain a semiconductor device having a soldering layer at a rear electrode by a method wherein a lattice-like blocked film is formed with a heat-resistance photoresist material at the rear electrode side of a semiconductor wafer and furthermore, a soldering layer is formed by using soldering paste. CONSTITUTION:A lattice-like blocked film 11 partitioning each element 8 is formed with a photoresist material having higher heat-resistance performance than the melting point of solder at the rear electrode 9 side of a semiconductor wafer 7, and furthermore, a soldering paste layer 12 is formed on the whole area of the rear face. With the wager 7 heated, a dissolved soldering layer 14 having thin wall thickness and contacting with the blocked film 11 out of the dissolved layer condenses into a dissolved soldering layer 13 having thick film thickness and the blocked film 11 is exposed to the outside. Therefore the layer 14 is dissolved and removed. The obtained wafer 7 can be cut with a blade without causing blinding.

Description

【発明の詳細な説明】 この軸重は癲ｌ−極に牛日階を有する牛魯体、！＊童の
、Ｊ１ｉ１！造方法に関するものでめる・＆に面電極に
午田層を有する午、一体験−は、−苧嬶一体りエーハ（
以下単にクエーシ１と祢ｔ）【各素子に分−」し次仮、
拓／、鮎ＩＫ承、す方法によって平田層を形成する・ 即ち、この方法は加熱ヒータ１１１の上面ｔ−皺うホッ
トル−ト菟幻上にステム（３）ｔ−載せた状態において
、ステム１＄１上に適普の早出（４）￥ｒ供給し１、′
溶融させた牛用上に素子（６）の捩Ｉｆ］電極を接触さ
せて平田層上、形成するよ・うにしたものである・しか
し、仁の方決の場合、平田が溶融すると１１ＬＫｌ！化
被ａが形成されるので、単に素子（６）の蟲ｍ＊ｍｔ−
ｍ敞平田に接触させるだけでは＠看性能が患く、このｋ
め第Ｊ図ＩＫ示すように接触させｊＤ前に射もって溶融
牛田（６）を引掻き俸〜で！１１＆！鹸化被換を除去す
るか、或いは棄子１６１　ｔｆＩＩａ！ＩＩ牛ａｉ　４
ｇ３に押し付妙なか−ら所定時−こすククけるスクラブ
を行、なうことが必要となる。[Detailed Description of the Invention] This axle load is a cow body with a cow day scale at the epileptic pole! *Children's J1i1! Regarding the fabrication method, it is an experience that the surface electrode has a Gota layer.
Hereinafter, simply ``Kueshi 1'' and ``Net'') [divided into each element-'' and then temporary,
The flat layer is formed by the method of Taku/Ayu IK. In other words, this method involves placing the stem (3) on the upper surface of the heater 111 and placing the stem (3) on the wrinkled hot root tube. Appropriate early delivery on $1 (4) ¥r supply 1,'
The torsion electrode of the element (6) is brought into contact with the melted cow surface to form the Hirata layer. However, in the case of Jin's decision, when the Hirata is melted, 11 LKl! Since the cladding a is formed, it is simply m*mt- of the element (6).
Just letting him come into contact with M Hirata will hurt his nursing performance, this k
Make contact as shown in Figure J and shoot in front of JD to scratch the melted Ushida (6)! 11&! Eliminate saponification conversion or abandonment 161 tfIIa! II cow ai 4
It is necessary to apply a scrub at a predetermined time while pressing on g3.

−仁の結果、上記方法による七髪皺の機４１１が候ＫＫ
なル、而を嵩子、、４＆ｌ毎に牛す層會形叙するため工
数がかかり牛導体装箇のＩ１１！造コストが高（り、（
壽− これ１改善するものとして、予じめクエーハＯ頴動電−
の全Ｅｌｌｉに午田層【形式しておき、プレードを用い
て各素子に切断する方法が考えられる。ところがグレー
ドは例えば薄い基材にニラグルメツキを行なった後ダイ
ヤ七ンード粒子を埋め込んで形成されるダイヤモンド鉱
石の一柚であって、結合度が高いうえに粒子が和１がく
、柔軟で厚い牛用〜’ｋｖＪ断すると目脂まりが起きる
。よってこのままクエーハの切＃に続けるのは手口」能
である。- As a result of the above method, the number 411 of the seven hair wrinkles was obtained.
However, it takes a lot of man-hours to prepare a cow conductor for every 4&l. The manufacturing cost is high (ri, (
Hisashi - As an improvement to this, Quaha O's electrodynamics should be used in advance.
One possible method is to form a Gota layer on all the ellipses and cut it into each element using a blade. However, the grade is, for example, diamond ore that is formed by embedding diamond particles after performing niragurmetuki on a thin base material, and it has a high degree of bonding and the particles are 1 cal, making it flexible and thick. 'If you cut off kvj, your eyes will become oily. Therefore, it is Kueha's trick to continue as is.

この発明は、板囲電椰に千…層を名する牛導体ｔ−製造
すゐ過栓において生ずる上述した同一点を解決するため
、午導体りエーハの蟲（６）−極＠に各素子ｔ″区割る
格子状の区ｌｌ１４展を早出の融点より高い耐熱性肚を
封する耐熱レジスト材で形訳し、この部分に炒成される
肉厚の渉い苗敵午田層ｖ１！に面亀勧上にル歇される肉
厚の厚い溶融平田層に凝集させ、この後上記凶ｌ１ｌｌ
ｌ膜を除去し区割膜の跡に沿って牛導体りエーハを切締
ｒして単体の素子に分離するようにした牛導体装讃のｂ
造方法であって以下この発明の撓収【図に示す実ｌｉＩ
！！＠に従って脱明すると次の通りである・ 第３図において１７＋は従来の成形過によって製造され
るシリコン製のクエーハであって、このクエーハ（７）
の表面には所定の整列パターンに従って多数個の素子（
８）が形成されておシ、裏面の全域にはクロム、ニッケ
ル、スズ、銀ＮＩＶｉ−順次真空蒸看させた厚さが数μ
の鉄面Ｔｉ１極（９）が形成される。−は上記クエーハ
（７７の表面側からレゾ−マーキングに１って穿設され
に樋数の貫通孔であってタエーハ蟻１）の１ｋｉｋｌ−
極側の所定の整列パターンに従って平田層を炒成すると
きの位−一シ出しに用いる。In order to solve the above-mentioned same problem that occurs in the production of over-plugs, this invention has a thousand layers of electrical conductors in the electrical conductor. Translate the lattice-like section ll14 divided by t'' section with a heat-resistant resist material that seals the heat-resistant layer with a temperature higher than the melting point of the early stage, and the thick wading seedlings that are roasted in this section face the enemy Gota layer v1! It is agglomerated into a thick molten layer that is poured onto the surface of the turtle, and then the above-mentioned
B of the cow conductor assembly in which the membrane was removed and the conductor wire was cut along the traces of the dividing membrane to separate it into individual elements.
The manufacturing method of the present invention will be described below.
! ! The clarification according to @ is as follows. In Fig. 3, 17+ is a silicon quafer manufactured by conventional molding, and this quafer (7)
A large number of elements (
8) is formed, and the entire back surface is coated with chromium, nickel, tin, and silver NIVi, which have a thickness of several micrometers by successive vacuum vaporization.
A single iron-faced Ti pole (9) is formed. - is a through-hole of the number of troughs drilled from the surface side of 77 to the reso marking, and 1 kikl-
It is used for positioning when firing the Hirata layer according to a predetermined alignment pattern on the pole side.

第グー以下ｉこの発明に係る牛導体裁菖の製造方法によ
る成形−１Ｍ１松を示し、胃、７図における（１１）は
上記＆山ｉｌ！極（３）上に７オトレジスト法によって
形成されゐ格子状の区１＄１１膜であって、上記各素子
（８）　を区−ｊするため上配複敞の貫通孔−を利用し
素子（８）の整列パターンと幻応させて設ける・上記区
１ｌＩＩＩｉ４０υ鉱後から形成される溶融千…層によ
って溶解してしまうことのないように早出の融点より高
い耐熱性能を有する耐熱レジスト、材、例えばＮ社製Ｊ
′ＳＲ、ＣＢＲ痔で形成するし 曹は上記区割１４　（１１）　′ｔ″杉訳した後、クエ
ーハ（７）の、４面の全域に１、且つ区＃ｉ　Ｍ　（１
１）よシ若干厚く真檀させて被層゛した早出ペースト“
層゛であって、粉末状の早出と自偉裕剤を混ぜ合せ次も
のがらな９、ペース・ト状會呈し、シルゲスクリーン法
塾、によって均一の厚さに被゛看される。Part 1: Molding by the manufacturing method of the cow conductor iris according to this invention - 1M1 pine is shown below, and (11) in Figure 7 is the above & mountain il! A lattice-like section 1 film is formed on the electrode (3) by the photoresist method, and the through-holes in the upper layer are used to separate the above-mentioned elements (8). 8) A heat-resistant resist or material having a heat resistance higher than the melting point of the early melting point, such as a heat-resistant resist or material, is provided in parallel with the alignment pattern of 8). J made by N company
'SR, CBR Hemorrhoids form in the above section 14 (11) 't'' After translating the cedar, Quaha (7), 1 in the entire area of 4 sides, and ward #i M (1
1) Quick-release paste coated with a slightly thick layer of real wood.
The layer is made by mixing powdered quick release and self-enhancing agents, then forming into a paste, which is then coated to a uniform thickness using a silgescreen method.

次に上記クエーハ（７）を早出の融点に都黙し、上記午
田ペースト層鯖を浴融する′。この七き、区１Ｊ展（１
１）は早出の＃＆！点以上の耐熱性を胸するので融触し
てしまうことがなく、鮎Ｊし？Ｉに示すように若干に張
して初期の形状を七のｌま維持すゐ、そしてクエーハ（
７）の表面の全・域に丘って浴融した溶融早出階のうち
表面・電極（９）と接する肉厚の厚い＃融午ａｔ揄Ｑｉ
ｉｊ境界層に合金層を形成して裏ｒｆ１］１１極（９；
に強固に凝着し、−万区割展Ｏりと振する肉厚の淋い招
融平田層鱈は区魯ｊ′展０１）にに＆増してしまうこと
がな・く、周Ｈを引張られて肉厚の厚い溶融午田層輌に
凝集する０ 以上のようにして溶融平田層が各素子（８）毎の表面電
＆閣上に凝着すると区ｇ＃Ｊ展０１，１が外部に一田す
る。このあ七凝着した平田層側の″表面に飛び出し＊１
機溶剤を洗い落し、次いてクエーハ（７）ｔ−溶解液に
浸漬し第４図に示すように区割膜（Ｉｌｌ　ｔ−溶解除
来する。　　　′仁のようにして得られたクエーハ（７
）は区す展すυ跡に沿って１Ｉｋｉｋｌ電極（ｊｌｌが
誕出し、またこの鉄面電極ｔｉｌｌの犀さは歌声である
ので目詰ルを起すことなくプレー゛ドで切断することが
司能てあ為、そしてプレード′【ｍｌい１述した複数め
貫通孔−を利用し、裏向電＆　Ｔｉ１ｌ僑から区１１ム
Ｊの跡に沿ってクエー／−４７）　を単体の素子−に切
断分離する。或いはグレードによりて破断溝上一般し後
τ゛単体素子−に折少分離する９ 以上説明し穴様にこの置駒Ｏ牛魯体襞亀の製造方法は、
半導体クエーハのｈ面電極−に各素子を区割する格子状
の区１１Ｊ展を千円の融点よ゛夛高い耐熱性を有す耐熱
レジスト材で形成し、この部分に形成される肉厚の薄い
溶融早出層ｔ−表面電極上に形成される肉厚の厚い溶融
早出層に凝縮させ、この後上記区１１１展ｔ−除失し区
割膜の跡に沿って半導体クエーハを切断して単体の素子
に分離するようにし穴からクエーハのａ曲の全域に亘っ
て浴融した半田層を各素子に対応しｆｃＭ面電極の半田
層に区餉する１栓と、俗敵早出層よシ区割展會−出させ
る工程を同一に行なえ、而も区鞘ｋｔ除去した後はクエ
ーハを容易にグレードによって切断することができるか
ら、この結＊龜曲電極に平田層上有する午鳩体鋏重【容
易に、且つ安価に提供することができゐ−Next, the quaternary paste (7) is brought to its early melting point, and the mackerel in the Uda paste layer is melted in a bath. Kono Shichiki, Ward 1J Exhibition (1
1) is an early #&! It has a heat resistance higher than 100%, so it won't melt, making it perfect for Ayu J. Stretch it slightly as shown in I to maintain its initial shape, and then press Quaha (
7) Among the molten early floors that are molten on the whole area of the surface, there is a thick wall in contact with the surface/electrode (9).
Form an alloy layer on the ij boundary layer and reverse rf1] 11 poles (9;
The thick and lonely cod that sticks firmly to the surface and shakes slowly will not increase in size and increase the thickness of the cod. When the molten Hirata layer adheres to the surface of each element (8) as described above, the molten Hirata layer is pulled and aggregates into a thick molten Hirata layer. Ichida to the outside. This A7 sticks out to the surface of the Hirata layer side *1
The organic solvent is washed off, and then immersed in the Quafer (7) solution to form a divided membrane (Illt-dissolved) as shown in FIG.
), a 1kikl electrode (jll) is born along the υ trace that is separated, and since the sharpness of this iron surface electrode till is a singing voice, it is possible to cut it with a plaid without causing clogging. Then, using the plurality of through-holes mentioned above, cut the plaid (-47) into single elements along the traces of the 11mm J from the Urakoden & Ti1l. To separate. Or, depending on the grade, it is generally broken on the rupture groove and then folded and separated into τ゛single elements.
A lattice-like section 11J that divides each element on the h-plane electrode of the semiconductor wafer is formed using a heat-resistant resist material that has a heat resistance much higher than the melting point of 1,000 yen, and the thickness of the wall formed in this section is Thin molten quick-release layer t - Condensed into a thick molten quick-release layer formed on the surface electrode, and then expanded into the above-mentioned section 111 and removed, cutting the semiconductor wafer along the traces of the partition film to form a single piece. One plug is used to separate the solder layer from the hole to the solder layer of the fcM surface electrode corresponding to each element over the entire area of the quadrangle. The cutting process can be carried out in the same way, and after removing the sheath, the quaker can be easily cut according to the grade. Can be provided easily and inexpensively.

【図面の簡単な説明】[Brief explanation of drawings]

第７図及びｔｊ！；−図は機（３）電極に早出層上胸−
する早導体装−の従来の１ｉｉｉ造方法Ｙｔ説明した図
を示す、第３図乃至第４図はこの発明に４１ｋる牛椿体
装箇の鋏造方法ｔ−脱明する穴めの図で、艷Ｊ図線りエ
ーハの断ｉｊ［ｉを示し、第Ｖ図鉱りエーＩ−の裏面電
極ｗに区−ｊ展を形成した後、早出ペーストを被着し穴
状ｗＡを示し、第５図は浴融した半田層が凝集する状態
を示し、第２図は格子膜の跡に沿ってクエーハを切断し
車体の素子に分離する状態を示す・ （７）・・半導体クエーハ、（８）・・素子、（９）・
・裏面電極、帆）・・区割展、輌・・牛用ペースト層、
輪−・肉厚の厚い溶融早出層、（１４Ｊ・・内厚の薄い
溶融早出層、ｔｔ８Ｉ・・単体の素子。 第１図 第２　図 第３　閤 第４図Figure 7 and tj! ;-The figure shows the machine (3) electrode on the upper chest.
Figures 3 and 4 are diagrams illustrating the conventional 1III manufacturing method for fast conductor equipment, and are diagrams of the method for making 41k camellia body equipment with scissors according to the present invention. , Figure V shows the section ij [i of the line A, and after forming the section-j extension on the back electrode w of the ore A I-, the quick release paste is applied to show the hole-like shape wA. Figure 5 shows the state in which the solder layer melted in the bath is agglomerated, and Figure 2 shows the state in which the quafer is cut along the traces of the lattice film and separated into car body elements. (7) Semiconductor quafer, (8 )・Element, (9)・
・Back electrode, sail)・Section exhibition, vehicle・Cow paste layer,
Ring--Thick molten quick-release layer, (14J...Thin inner thickness molten quick-release layer, tt8I...Single element. Figure 1, Figure 2, Figure 3, Figure 4)

Claims (1)

【特許請求の範囲】[Claims] ＋１１　　多数の素子を形茂し大牛専体りエーハの−ｌ
電極側に上記各素子を区鯖する格子状の区船験を平田の
融点より高い絣熱性を刊する耐熱レジスト材で形威し、
更にこの区１１１Ｊ稜に嵐払させて表面電極測全−に細
当な厚さの４千絢ペ一スト層を形ＫＬ、次いτこの牛榛
体りエ−７ハを加熱して溶融早出／＃１全１會形賜この
、後区−一を除去し区餉展の跡に沿って牛港体りエーハ
を切−１して単体の素子に分融するよう３にしたこく七
特倣とする牛尋体敦−の鍮意方法・+11 A large number of elements are formed and the large bull is dedicated to Aha's -l
On the electrode side, we used a heat-resistant resist material that has a heat resistance higher than Hirata's melting point to form a grid-like structure that separates each of the above elements.
Furthermore, the ridge of this section 111J was swept away by a storm, and a layer of 4,000-gold paste of a certain thickness was applied to the total surface electrode measurement. Early release/#1 Complete 1 meeting format, after removing the second part and cutting the Ushiminato body Aha along the traces of the first part, I cut it into three so that it would split into a single element. Special imitation of Ushihiro Atsushi's brassy method.
JP56146910A 1981-09-16 1981-09-16 Manufacture of semiconductor device Pending JPS5848420A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56146910A JPS5848420A (en) 1981-09-16 1981-09-16 Manufacture of semiconductor device

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Application Number Priority Date Filing Date Title
JP56146910A JPS5848420A (en) 1981-09-16 1981-09-16 Manufacture of semiconductor device

Publications (1)

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JPS5848420A true JPS5848420A (en) 1983-03-22

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JP56146910A Pending JPS5848420A (en) 1981-09-16 1981-09-16 Manufacture of semiconductor device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0888200A (en) * 1994-09-14 1996-04-02 Nec Corp Semiconductor wafer, semiconductor device and tis manufacture

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5193867A (en) * 1975-02-17 1976-08-17 Handotaisochino seiho
JPS52127750A (en) * 1976-04-19 1977-10-26 Mitsubishi Electric Corp Production of semiconductor unit
JPS53115064A (en) * 1977-03-18 1978-10-07 Mitsubishi Electric Corp Method of producing hyb ic

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5193867A (en) * 1975-02-17 1976-08-17 Handotaisochino seiho
JPS52127750A (en) * 1976-04-19 1977-10-26 Mitsubishi Electric Corp Production of semiconductor unit
JPS53115064A (en) * 1977-03-18 1978-10-07 Mitsubishi Electric Corp Method of producing hyb ic

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0888200A (en) * 1994-09-14 1996-04-02 Nec Corp Semiconductor wafer, semiconductor device and tis manufacture

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