JPS5925417A - Switching circuit - Google Patents
Switching circuitInfo
- Publication number
- JPS5925417A JPS5925417A JP12217383A JP12217383A JPS5925417A JP S5925417 A JPS5925417 A JP S5925417A JP 12217383 A JP12217383 A JP 12217383A JP 12217383 A JP12217383 A JP 12217383A JP S5925417 A JPS5925417 A JP S5925417A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- switching circuit
- switching element
- load
- fetqs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Electronic Switches (AREA)
Abstract
Description
【発明の詳細な説明】
この発明はＦＤＴを用いたスイッチング回路に関し、特
に二端子の負荷素子を用いて出力ｖＭ、圧を任意の値に
設定することのできるスイッチング回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a switching circuit using an FDT, and more particularly to a switching circuit that can set the output vM and pressure to arbitrary values using a two-terminal load element.
ＭＩＳ−’ＩＣのスイッチング回路は、製造工程を簡単
にするためスイッチ素子と負荷素子を共にＭＩＳ Ｆ
ＩＤＴで構成しており、更に、スイッチングの過渡時に
電流消費を大きくしてスイッチング特性をよくするため
に、負荷素子としては、ゲートとソースを共に出力端子
に接続したデプリーション形のＭＩＳ ＦＦ：Ｔや、
ゲートをスイッチング回路における電源の高電位線（Ｖ
ＤＤ）よりも更に高い第２の電源（ＶＧＧ）に接続して
、三極管領域で動作し線形抵抗に近い負荷特性を示すエ
ンハンスメント形のＭＩＳ １”ＥＴが用いられる。In order to simplify the manufacturing process, the MIS-'IC switching circuit uses both the switch element and the load element as MIS F.
In addition, in order to increase current consumption during switching transients and improve switching characteristics, the load element is a depletion type MIS FF:T whose gate and source are both connected to the output terminal. ,
The gate is connected to the high potential line (V) of the power supply in the switching circuit.
An enhancement-type MIS 1''ET operating in the triode region and exhibiting a load characteristic close to a linear resistance is used, connected to a second power supply (VGG) higher than DD).
上記の負荷素子を用いた場合、スイッチ素子がオフ状態
の時ｐ出力レベルは、負荷素子のドレイン軍、庄と同じ
電位まで」二昇するため、ＩＣ内の一部の回路で信号の
ハイレベルを低くおさえて、ハイレベルカラローレプル
へのスイッチング時間の短縮をはかろうとする場合は、
第３の低インピーダンスの電圧源が必要になる。When using the above load element, when the switch element is in the off state, the output level rises to the same potential as the drain of the load element, so some circuits in the IC are at a high level of the signal. If you are trying to reduce the switching time to a high level Colorore pull by keeping the
A third low impedance voltage source is required.
この発明の目的は外部電源を追加せずに、出力のハイレ
ベルを電源電圧よ抄も低い任意の値に設定できる高速動
作可能なスイッチング回路を提供することにある。An object of the present invention is to provide a switching circuit capable of high-speed operation that can set the high level of the output to an arbitrary value that is lower than the power supply voltage without adding an external power supply.
一以下第１図及び第２図を参照して、本発明の一実施例
を説明する。第１図はそれぞれの素子にＮチャネルＭＩ
Ｓ ｌ”ＥＴを使用して構成した本発明の一実施例を
示すスイッチング回路であり、スイッチ素子Ｑｓは、共
通線（ＧＮＤ）と出力端子ｌＯとの間に接続され、負荷
素子ＱＬのゲート電極とソース電極は出力端子１０に、
ドレイン電極は出力電圧制限素子ＱＮＦ！のソース電極
に接続され（接続点１１）また出力′電圧制限素子Ｑｇ
のゲート電極は電圧源Ｖｃに接続され、ドレイン電極は
高電位ｍ （’Ｖ ＤＤ ）に接続されている。ここで
出力電圧制限素子ＱＥとスイッチ素子Ｑｓはエンハンス
メント形、負荷素子ＱＬはデプリーション形のＭＩＳ
ＦＪＤＴである。第１図の回路の負荷特性を第２図に
示す。２２は負荷素子Ｑ！、のドレイン電極とソース電
極の間をショートした時の出力１［、圧制限素子ＱＥの
負荷特性を示し、ドレイン電流が流れない時の電圧（Ｖ
Ｇ−ＶＴ）は出力電圧制限素子ＱＥのソース電圧がゲー
ト電極の電圧■Ｇよりもスレッシュホールド霜、圧ＶＴ
分だけ低くなることを表わし、また２２の傾きが垂直に
近いのはｓＱｖのチャネル幅をチャネル長よりも大きく
して大きなコンダクタンスを持たせることによりＱｇを
電流制限素子としてではなく、電圧制限素子として動作
させているだめである。２３は負荷素子Ｑｔ、のドレイ
ン電極を上記電圧制限素子ＱＥのソー、Ｘ、電圧（Ｖ、
−ＶＴ）と同じ電圧を発生し、内部インピーダンスが零
の電圧源に接続した場合の負荷特性を示す。２４は電圧
制限素子ＱＥと負荷素子ＱＬを直列に接続した第１図の
回路の負荷特性で、２２と２３から容易に求められるも
のである。One embodiment of the present invention will now be described with reference to FIGS. 1 and 2. Figure 1 shows N-channel MI for each element.
This is a switching circuit showing one embodiment of the present invention configured using S l"ET, in which a switch element Qs is connected between a common line (GND) and an output terminal lO, and a gate electrode of a load element QL. and the source electrode is connected to the output terminal 10,
The drain electrode is the output voltage limiting element QNF! (connection point 11) and the output voltage limiting element Qg.
The gate electrode of is connected to a voltage source Vc, and the drain electrode is connected to a high potential m ('V DD ). Here, the output voltage limiting element QE and the switching element Qs are of the enhancement type, and the load element QL is of the depletion type.
It is FJDT. The load characteristics of the circuit shown in FIG. 1 are shown in FIG. 22 is the load element Q! Output 1 [, when the drain electrode and source electrode of
G-VT), the source voltage of the output voltage limiting element QE is lower than the gate electrode voltage ■G, which is the threshold frost, the voltage VT
The reason why the slope of 22 is almost vertical is that the channel width of sQv is made larger than the channel length to have a large conductance, so that Qg is used not as a current limiting element but as a voltage limiting element. It's no use making it work. 23 connects the drain electrode of the load element Qt to the source of the voltage limiting element QE, X, voltage (V,
-VT), and shows the load characteristics when connected to a voltage source with zero internal impedance. 24 is the load characteristic of the circuit shown in FIG. 1 in which the voltage limiting element QE and the load element QL are connected in series, which can be easily obtained from 22 and 23.
２５はゲート電圧をＶＧとしたエンハンスメント形ＭＩ
Ｓ ］”１３Ｔを２４と同程度の負荷電流を持つ負荷
素子とした場合の負荷特性を表わし、電圧制限素子ＱＥ
のコンダクタンスを約百分の−にした場合の負荷特性に
一致する。25 is an enhancement type MI with a gate voltage of VG.
S]” represents the load characteristics when 13T is a load element with the same load current as 24, and the voltage limiting element QE
This corresponds to the load characteristics when the conductance is reduced to about -100%.
２０と２１はそれぞれスイッチ素子Ｑｓのオン状態とオ
フ状態における動作曲線を表わし、各負荷１行性曲線２
３〜２５との父点けそれぞれの負荷素子を使用１７た嚇
合のオン状態及びオフ状態での出力レベルを表わしてい
る。20 and 21 represent the operating curves of the switching element Qs in the on state and off state, respectively, and each load unidirectional curve 2
It shows the output level in the on state and off state using the respective load elements 3 to 25.
本発明を用いた場合の長所は、負荷特性２４が、（Ｖｏ
−ＶＴ ）の電圧を持つ低インピーダンスの電圧源に接
続されたデプリーション形Ｍｉｓ ］’Ｆ３Ｔの負荷
特性２３に近く、２５に示すようなエンハンスメン）Ｍ
ＩＳ Ｆ）！３Ｔを飽和領域で用いた場合の負荷特性
にくらべてスイッチングの過渡時における電流消費を大
きくして、スイッチング速度の同筆がはかれることと、
出力／Ｓイレペル設定用電圧源（Ｖａ）の内部インピー
ダンスは高くてもよいため、集積回路とした場合の電源
設定回路の占有面積は十分小さくてずみ、まだその電圧
も任意に設定できることである。The advantage of using the present invention is that the load characteristic 24 is (Vo
A depletion type Mis]' connected to a low-impedance voltage source with a voltage of
ISF)! Compared to the load characteristics when 3T is used in the saturation region, current consumption during switching transients is increased to achieve the same switching speed;
Since the internal impedance of the output/S level setting voltage source (Va) may be high, the area occupied by the power setting circuit when integrated circuit is sufficiently small, and the voltage can still be set arbitrarily.
以上の実施例ではＮチャネルＭＩＳ ＦＥＴ回路につい
て説明しだが、電源の極性を逆にすることによってＰチ
ャネルＭＩＳ ＦＥＴ回路にも同様に適用できる。ま
た出力電圧制限素子Ｑｇはゲート電圧（ＶＧ）を適当に
選ぶことによってデプリーション形Ｍ Ｉ Ｓ１ｉ”Ｄ
Ｔでも使用でき、負荷素子ＱＬはエンノ・ンスメント形
Ｍｉｓ ＦＬｉ’、Ｔを二極管領域で動作式せたもの
や、拡散抵抗でもよく、まだスイッチ素子には低抵抗の
オン状態と高抵抗のオフ状態を取る任意の素子が使え、
まだその直列または並列接続でもよい。In the above embodiment, an N-channel MIS FET circuit has been described, but the present invention can be similarly applied to a P-channel MIS FET circuit by reversing the polarity of the power supply. In addition, the output voltage limiting element Qg can be set to a depletion type M I S1i''D by appropriately selecting the gate voltage (VG).
T can also be used, and the load element QL can be an enhancement type Mis FLi', T operated in the diode region, or a diffused resistor, and the switch element can still have a low resistance on state and a high resistance off state. Any element that takes
It can still be connected in series or in parallel.
第１図は本発明の一実施例？示す回路図でｓＱｓはスイ
ッチ素子ｓＱＬは負荷素子、ＱＥは出力電ＬＬ制限素子
である。
第２図は第１図の回路の動作を示す電、０二対電流特性
図で、２０．２１はスイッチ素子の動作特性、２２〜２
５は負荷素子の負荷特性を示す。
め１図
６−Ｖｒ
めどロ
ア９−Is Fig. 1 an embodiment of the present invention? In the circuit diagram shown, sQs is a switch element, sQL is a load element, and QE is an output current LL limiting element. Figure 2 is a graph showing the operation of the circuit shown in Figure 1. 20.21 is the operating characteristic of the switch element, 22-2
5 shows the load characteristics of the load element. Me1 Figure 6-Vr Medoroa 9-
Claims (2)
出力端子と電源端子との間に接続された負荷素子として
の第１の電界効果トランジスタと電圧制限用の第２の電
界効果トランジスタとの直列回路とを有し、」二記第１
および第２のトランジスタを介して流れる電流が該スイ
ッチング素子が導通時に該スイッチング素子を介して基
準電位に流出される時の該出力端子の電位を一輪理の出
力信号となし、」二記スイッチング素子の入力信号と該
スイッチング素子の出力端子から得られる出力信号との
負荷特性を実質的に上記第１の電界効果トランジスタに
よって定め、」二記第２の電界効果トランジスタによっ
て上記スイッチング素子が非導通時の他論理の出力信号
の上記電源側のレベルを制御せしめるようにしたことを
特徴とするスイッチング回路。(1) A switching element, and a series circuit of a first field effect transistor as a load element and a second field effect transistor for voltage limitation connected between an output terminal of the switching element and a power supply terminal. "Have," 2nd Book 1
and the potential of the output terminal when the current flowing through the second transistor is drained to the reference potential through the switching element when the switching element is conductive is set as a single output signal; The load characteristics of the input signal of the input signal and the output signal obtained from the output terminal of the switching element are substantially determined by the first field effect transistor, and when the switching element is non-conducting by the second field effect transistor, A switching circuit characterized in that the level of the output signal of another logic on the power supply side is controlled.
ジョン型でありそのゲートは自身のソースに接続されて
いることを特徴とする特許請求の範囲第（１）項に記載
のスイッチング回路。(2) The first field effect transistor has a deg I7. −
2. The switching circuit according to claim 1, wherein the switching circuit is of John type and has its gate connected to its source.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12217383A JPS5925417A (en) | 1983-07-04 | 1983-07-04 | Switching circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12217383A JPS5925417A (en) | 1983-07-04 | 1983-07-04 | Switching circuit |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4921577A Division JPS53133359A (en) | 1977-04-27 | 1977-04-27 | Switching circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5925417A true JPS5925417A (en) | 1984-02-09 |
Family
ID=14829375
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12217383A Pending JPS5925417A (en) | 1983-07-04 | 1983-07-04 | Switching circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5925417A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0225249A2 (en) * | 1985-11-21 | 1987-06-10 | Digital Equipment Corporation | CMOS current switching circuit |
| EP0436876A2 (en) * | 1990-01-11 | 1991-07-17 | Siemens Aktiengesellschaft | NTL-integrated transistor switching stage |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50113164A (en) * | 1974-02-13 | 1975-09-05 | ||
| JPS53133359A (en) * | 1977-04-27 | 1978-11-21 | Nec Corp | Switching circuit |
-
1983
- 1983-07-04 JP JP12217383A patent/JPS5925417A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50113164A (en) * | 1974-02-13 | 1975-09-05 | ||
| JPS53133359A (en) * | 1977-04-27 | 1978-11-21 | Nec Corp | Switching circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0225249A2 (en) * | 1985-11-21 | 1987-06-10 | Digital Equipment Corporation | CMOS current switching circuit |
| EP0436876A2 (en) * | 1990-01-11 | 1991-07-17 | Siemens Aktiengesellschaft | NTL-integrated transistor switching stage |
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