JPS5924547B2 - nonvolatile memory transistor - Google Patents
nonvolatile memory transistorInfo
- Publication number
- JPS5924547B2 JPS5924547B2 JP13258176A JP13258176A JPS5924547B2 JP S5924547 B2 JPS5924547 B2 JP S5924547B2 JP 13258176 A JP13258176 A JP 13258176A JP 13258176 A JP13258176 A JP 13258176A JP S5924547 B2 JPS5924547 B2 JP S5924547B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon nitride
- memory transistor
- film
- nitride layer
- δvth
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 34
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 34
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000000969 carrier Substances 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 13
- 230000014759 maintenance of location Effects 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 4
- 229910052681 coesite Inorganic materials 0.000 description 4
- 229910052906 cristobalite Inorganic materials 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 229910052682 stishovite Inorganic materials 0.000 description 4
- 229910052905 tridymite Inorganic materials 0.000 description 4
- 239000000758 substrate Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000006993 memory improvement Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
Description
【発明の詳細な説明】
本発明は、不揮発性メモリトランジスタ特にＭＮＯＳ（
金属−窒化物一酸化物一半導体）メモリトランジスタの
改良に係わる。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to non-volatile memory transistors, particularly MNOS (
Related to the improvement of memory transistors (metal-nitride monoxide-semiconductor).
ＭＮＯＳメモリトランジスタは、周知の如くＳｉ３Ｎ濃
及びＳｉＯ２膜界面に存在するトラップ準位と半導体基
板との間の電荷の交換により、Ｓｉ３Ｎ４膜及びＳｉＯ
２膜界面に蓄積する電荷の変化量に対応するＭＮＯＳメ
モリトランジスタのしきい値電圧Ｖｔｈの変化を゛１’
’及び゛ｏ’’の情報に対応させている。As is well-known, the MNOS memory transistor has a Si3N4 film and an SiO2 film due to charge exchange between the trap level existing at the Si3N-concentrated and SiO2 film interface and the semiconductor substrate.
The change in the threshold voltage Vth of the MNOS memory transistor corresponding to the amount of change in the charge accumulated at the interface between the two films is expressed as ``1''.
It corresponds to the information of ' and o''.
かかるＭＮＯＳメモリトランジスタの信頼性、即ちメモ
リの保持特性は、そのしきい値電圧Ｖｔｈの変化量（シ
フト量）ΔＶｔｈに大きく依存し、一定の書込み電圧に
対してΔＶｔｈの大きいものほどメモリの保持時間が長
くなり信頼性が向上する。従来のＭＮＯＳメモリトラン
ジスタは、通常膜厚２０Ａ゜程度の薄いＳｉＯ２膜上に
膜厚５００〜７００Ａ゜程度のＳｉ３Ｎ４膜を形成し、
その上にゲート電極を形成した構造となつているが、こ
の場合にはΔＶｔｈが不十分で信頼性が低い。The reliability of such an MNOS memory transistor, that is, the memory retention characteristic, largely depends on the amount of change (shift amount) ΔVth in its threshold voltage Vth, and the larger ΔVth is for a constant write voltage, the longer the memory retention time is. is longer and reliability is improved. Conventional MNOS memory transistors typically form a Si3N4 film with a thickness of about 500 to 700 A° on a thin SiO2 film with a thickness of about 20 A°.
The structure has a gate electrode formed thereon, but in this case, ΔVth is insufficient and reliability is low.
本発明は、しきい値電圧Ｖｔｈの変化量ΔＶｔｈを大き
くしてメモリの保持時間を延ばし、且つ同時にゲート絶
縁層の耐圧をも高くして信頼性の高い不揮発性メモリト
ランジスタを提供するものである。実験によると、ＭＮ
ＯＳメモリトランジスタにおけるしきい値電圧Ｖｔｈの
変化量ΔＶｔｈは、ゲート部の窒化珪素（Ｓｉ３Ｎ４）
膜の成長条件に大きく依存している。The present invention provides a highly reliable nonvolatile memory transistor by increasing the amount of change ΔVth in the threshold voltage Vth to extend the memory retention time, and at the same time increasing the withstand voltage of the gate insulating layer. . According to experiments, MN
The amount of change ΔVth in the threshold voltage Vth in the OS memory transistor is
It is highly dependent on the film growth conditions.
すなわち、第１図に窒化珪素膜の成長条件の違いによる
ΔＶｔｈの変化及びそのメモリ保持特性を示すに、之は
ゲート部における酸化珪素（ＳｉＯ２）膜の厚みを２０
Ａ゜、窒化珪素（Ｓｉ３Ｎ４）膜の厚みを６５０Ａ０と
したＭＮＯＳメモリトランジスタで、その書込み電圧を
−３５Ｖ、１００ｍｓｅｃとした場合で、これから解る
ように窒化珪素膜の成長条件の違いによつてΔＶｔｈが
７．０Ｖ〜１０．５Ｖ（室温）と変化する。図中、点線
ａは読み出し電圧を示す。そして、この再現性は極めて
よく、各ロッド間でのΔＶｔｈのバラツキは±Ｏ、２Ｖ
程度である。窒化珪素膜はＳｉＨ４とＮＨ。を用いたＣ
ＶＤ（化学気相成長）法により形成するが、その成長条
件のうちでもΔＶｔｈに最も大きな影響を与えるのはＮ
Ｈ３とＳｉＨ４の流量比である。すなわち、ＮＨ３／
ＳｉＨ４二５０〜１５０のときΔＶｔｈは略１０．５Ｖ
程度（第１図の上限を示す曲線（Ｄ参照）となり、ＮＨ
３／５ｉＨ０＞３００のときΔＶｔｈは略７．０Ｖ程度
（第１図の下限を示す曲線（）参照）となる。これを窒
化珪素膜の組成でみると、珪素（Ｓｉ）を比較的多く含
む窒化珪素膜ではΔＶｔｈが大きく、窒素（Ｎ）を比較
的多く含む窒化珪素膜ではΔＶｔｈが小さくなる。従つ
て、ΔＶ，ｈの大きさ即ちメモリの保持特性からだけみ
ると、ＮＨ３／ＳｉＨ４＝５０〜１５０の成長条件によ
る窒化珪素膜が良好であることが解る。しかるに、一方
において窒化珪素膜自体の安定性、すなわちＢ−Ｔテス
トの合格率、従つてゲート絶縁層としての絶縁耐圧につ
いてみると、珪素（Ｓｌ）の多い窒化珪素膜は絶縁耐圧
が低く、窒素（Ｎ）の多い窒化珪素膜の方が絶縁耐圧が
高く安定性がある。そこで、本発明によるＭＮＯＳメモ
リトランジスタは第２図に示すように第１導電形型例え
ばＮ形のシリコン半導体基板１の一主面に第２導電形即
ちＰ形のソース領域２及びドレイン領域３を形成し、こ
のソース領域２及びドレイン領域３間のゲート部に対応
する半導体表面に例えば熱酸化による薄い酸化珪素（Ｓ
ｉＯ２）膜４を被着形成した後、この酸化珪素膜４上に
成長条件を連続的に変えて組成を異ならしめた窒化珪素
（ＳｉＮ４）膜５を形成する。That is, Fig. 1 shows the change in ΔVth due to different growth conditions of the silicon nitride film and its memory retention characteristics.
A゜, In the case of an MNOS memory transistor with a silicon nitride (Si3N4) film thickness of 650A0 and a write voltage of -35V and 100msec, as will be seen, ΔVth varies depending on the growth conditions of the silicon nitride film. It changes from 7.0V to 10.5V (room temperature). In the figure, the dotted line a indicates the read voltage. The reproducibility is extremely good, and the variation in ΔVth between each rod is ±O, 2V.
That's about it. The silicon nitride film is made of SiH4 and NH. C using
It is formed using the VD (chemical vapor deposition) method, and among the growth conditions, the one that has the greatest effect on ΔVth is N.
This is the flow rate ratio of H3 and SiH4. That is, NH3/
When SiH42 is 50 to 150, ΔVth is approximately 10.5V
degree (curve showing the upper limit in Figure 1 (see D), NH
When 3/5iH0>300, ΔVth is about 7.0V (see the curve () indicating the lower limit in FIG. 1). Looking at this in terms of the composition of the silicon nitride film, a silicon nitride film containing a relatively large amount of silicon (Si) has a large ΔVth, and a silicon nitride film containing a relatively large amount of nitrogen (N) has a small ΔVth. Therefore, it can be seen that the silicon nitride film grown under the growth condition of NH3/SiH4=50 to 150 is good when looking only from the magnitude of ΔV, h, that is, the retention characteristics of the memory. However, on the other hand, when looking at the stability of the silicon nitride film itself, that is, the pass rate of the B-T test, and therefore the dielectric strength voltage as a gate insulating layer, the silicon nitride film with a large amount of silicon (Sl) has a low dielectric strength voltage, and A silicon nitride film containing more (N) has higher dielectric strength and stability. Therefore, as shown in FIG. 2, the MNOS memory transistor according to the present invention has a source region 2 and a drain region 3 of a second conductivity type, that is, P type, on one main surface of a silicon semiconductor substrate 1 of a first conductivity type, for example, N type. For example, a thin silicon oxide (S
After the iO2) film 4 is deposited, a silicon nitride (SiN4) film 5 whose composition is varied by continuously changing the growth conditions is formed on the silicon oxide film 4.
すなわち、先づ成長条件をＮＨ３／ＳｉＨ４−５０〜１
５０として珪素の比較的多く含む第１の窒化珪素層６を
成長し、次に成長条件をＮＨ３／ＳｉＨ４〉３００とし
て窒素の比較的多く含む第２の窒化珪素層７を成長する
。That is, first, the growth conditions were changed to NH3/SiH4-50~1.
50, a first silicon nitride layer 6 containing a relatively large amount of silicon is grown, and then a second silicon nitride layer 7 containing a relatively large amount of nitrogen is grown under growth conditions of NH3/SiH4>300.
酸化珪素膜４の厚さは、キヤリアがトンネル現象で通過
し得る厚さに選定するもので、例えば２０Ａ０程度がよ
い。又、第１の窒化珪素層６の厚みは比較的に薄く５０
〜１００Ａ０程度、第２の窒化珪素層７の厚みは比較的
に厚く例えば５００〜６００Ａ０程度とすることができ
る。なお、第１の窒化珪素層６における厚み５０〜１０
０Ａ０というのは製造的に可能な値であつて、勿論５０
Ａ０以下の厚みとしてもよい。The thickness of the silicon oxide film 4 is selected to be such that carriers can pass therethrough by a tunneling phenomenon, and is preferably about 20A0, for example. Further, the thickness of the first silicon nitride layer 6 is relatively thin at 50 mm.
The thickness of the second silicon nitride layer 7 can be relatively thick, for example, about 500 to 600 A0. Note that the thickness of the first silicon nitride layer 6 is 50 to 10
0A0 is a value that is possible in manufacturing, and of course 50
The thickness may be A0 or less.
次いで、第２の窒化珪素層７上にゲート電極Ｇを形成し
、ソース領域２及びドレイン領域３に夫夫ソース電極Ｓ
及びドレイン電極Ｄを形成してＭＮＯＳメモリトランジ
スタを構成する。尚、８はＳｉＯ２膜等よりなる表面保
護膜である。上述せる構成のＭＮＯＳメモリトランジス
タによれば、そのゲート部において酸化珪素膜４上に接
する窒化珪素膜ば珪素を多く含む窒化珪素層６であるた
めに、第２図の曲線（１）で示すように、そのしきい値
電圧Ｖｔｈの変化量ΔＶｔｈが大きくなりメモリの保持
時間が長くなる。Next, a gate electrode G is formed on the second silicon nitride layer 7, and a source electrode S is formed on the source region 2 and drain region 3.
and a drain electrode D to form an MNOS memory transistor. Note that 8 is a surface protection film made of a SiO2 film or the like. According to the MNOS memory transistor having the above-described configuration, the silicon nitride film in contact with the silicon oxide film 4 at the gate portion is the silicon nitride layer 6 containing a large amount of silicon, so that Furthermore, the amount of change ΔVth in the threshold voltage Vth increases, and the memory retention time becomes longer.
しかも、第１の窒化珪素層６上には絶縁耐圧の高い窒素
を多く含む第２の窒化珪素層７が形成され、且つ之が第
１の窒化珪素層６より十分厚く形成されているためにゲ
ート絶縁層の絶縁耐圧が高くなり、全体として信頼性の
高い斯種不揮発性メモリトランジスタが得られる。Moreover, since the second silicon nitride layer 7 containing a large amount of nitrogen and having a high dielectric strength voltage is formed on the first silicon nitride layer 6, and is formed sufficiently thicker than the first silicon nitride layer 6, The dielectric breakdown voltage of the gate insulating layer is increased, and such a nonvolatile memory transistor with high reliability as a whole can be obtained.
第１図はＭＮＯＳメモリトランジスタの窒化珪素膜の成
長条件の違いによるしきい値電圧の変化量ΔＶｔｈの変
化及びそのメモリ保持特性を示す特性図、第２図は本発
明による不揮発性のＭＮＯＳメモリトランジスタの一例
を示す断面図である。
１は半導体基板、２はソース領域、３はドレイン領域、
４は酸化珪素膜、５は窒化珪素膜、６は珪素の比較的多
く含む窒化珪素層、７は窒素の比較的多く含む窒化珪素
層、Ｇはゲート電極、Ｓはソース電極、Ｄはドレイン電
極である。FIG. 1 is a characteristic diagram showing changes in threshold voltage variation ΔVth and its memory retention characteristics due to differences in the growth conditions of the silicon nitride film of an MNOS memory transistor, and FIG. 2 is a characteristic diagram showing the memory retention characteristics of the nonvolatile MNOS memory transistor according to the present invention. It is a sectional view showing an example. 1 is a semiconductor substrate, 2 is a source region, 3 is a drain region,
4 is a silicon oxide film, 5 is a silicon nitride film, 6 is a silicon nitride layer containing a relatively large amount of silicon, 7 is a silicon nitride layer containing a relatively large amount of nitrogen, G is a gate electrode, S is a source electrode, and D is a drain electrode. It is.
Claims (1)
順次キャリアがトンネル現象で通過し得る厚さの酸化膜
、珪素の比較的多く含まれた第１の窒化珪素層、窒素の
比較的多く含まれた第２の窒化珪素層及びゲート電極が
積層されて成る不揮発性メモリトランジスタ。1 In the gate region between the source and the drain, an oxide film having a thickness that allows carriers to pass through sequentially from the semiconductor surface by a tunnel phenomenon, a first silicon nitride layer containing a relatively large amount of silicon, and a first silicon nitride layer containing a relatively large amount of nitrogen. A nonvolatile memory transistor formed by laminating a second silicon nitride layer and a gate electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13258176A JPS5924547B2 (en) | 1976-11-04 | 1976-11-04 | nonvolatile memory transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13258176A JPS5924547B2 (en) | 1976-11-04 | 1976-11-04 | nonvolatile memory transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5357771A JPS5357771A (en) | 1978-05-25 |
| JPS5924547B2 true JPS5924547B2 (en) | 1984-06-09 |
Family
ID=15084666
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13258176A Expired JPS5924547B2 (en) | 1976-11-04 | 1976-11-04 | nonvolatile memory transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5924547B2 (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57186369A (en) * | 1981-05-13 | 1982-11-16 | Nec Corp | Semiconductor device |
| JPS5867072A (en) * | 1981-10-16 | 1983-04-21 | Nec Corp | Manufacture of semiconductor device |
| CA1188419A (en) * | 1981-12-14 | 1985-06-04 | Yung-Chau Yen | Nonvolatile multilayer gate semiconductor memory device |
| JP2747556B2 (en) * | 1986-03-31 | 1998-05-06 | 株式会社 半導体エネルギー研究所 | Method for manufacturing insulated gate field effect semiconductor memory device |
| JPH0642550B2 (en) * | 1987-08-10 | 1994-06-01 | 山形日本電気株式会社 | MIS type nonvolatile memory and method of manufacturing the same |
| JPH0779138B2 (en) * | 1987-08-31 | 1995-08-23 | 工業技術院長 | Non-volatile semiconductor memory device |
| JP2003068893A (en) * | 2001-08-28 | 2003-03-07 | Hitachi Ltd | Nonvolatile storage cell and semiconductor integrated circuit |
| WO2008123264A1 (en) | 2007-03-23 | 2008-10-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| JP5408930B2 (en) | 2007-08-31 | 2014-02-05 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
-
1976
- 1976-11-04 JP JP13258176A patent/JPS5924547B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5357771A (en) | 1978-05-25 |
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