JPS5923565A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5923565A JPS5923565A JP13192982A JP13192982A JPS5923565A JP S5923565 A JPS5923565 A JP S5923565A JP 13192982 A JP13192982 A JP 13192982A JP 13192982 A JP13192982 A JP 13192982A JP S5923565 A JPS5923565 A JP S5923565A
- Authority
- JP
- Japan
- Prior art keywords
- resist
- pattern
- coated
- polymer resin
- etched
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000002184 metal Substances 0.000 claims abstract description 6
- 229910052751 metal Inorganic materials 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 15
- 239000002952 polymeric resin Substances 0.000 claims description 12
- 229920003002 synthetic resin Polymers 0.000 claims description 12
- 238000010438 heat treatment Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 4
- 238000000992 sputter etching Methods 0.000 abstract description 4
- 239000000956 alloy Substances 0.000 abstract description 3
- 229910045601 alloy Inorganic materials 0.000 abstract description 3
- 238000001312 dry etching Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract 1
- 230000003213 activating effect Effects 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000011347 resin Substances 0.000 abstract 1
- 229920005989 resin Polymers 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000013078 crystal Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Abstract
Description
【発明の詳細な説明】
本発明は、ＧａＡＳ−ＦＥＴとこれらを基本に集積した
半導体装置の製法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a GaAS-FET and a method for manufacturing a semiconductor device basically integrated therewith.
ＧａＡ８−ＦＥＴ（電界効果トランジスタ）やＩＣ（集
積回路）の性能を向上するには、サブミクロン領域の加
工技術が必要となる。この目的のためには、電子線描画
による微細加工技術が検討されているが現状では、スル
ープットが上がらない欠点があった。従来の光露光技術
によシ、セルファラインによって加工精度を向上する試
みがあるが、従来の方法では、耐熱性が悪かったり、プ
ロセス加工上のマージンが小さかったりする欠点？有し
ていた。In order to improve the performance of GaA8-FETs (field effect transistors) and ICs (integrated circuits), processing technology in the submicron region is required. For this purpose, microfabrication techniques using electron beam lithography are being considered, but at present they have the drawback of not increasing throughput. There have been attempts to improve the processing accuracy using Selfa Line using conventional light exposure technology, but traditional methods have drawbacks such as poor heat resistance and small processing margins. had.
本発明の目的は、耐熱性に優れ、かつプロセス歩留りの
向上をはかったセル７アライン技術による半導体装置の
製法を提供することにある。An object of the present invention is to provide a method for manufacturing a semiconductor device using cell 7 alignment technology, which has excellent heat resistance and improves process yield.
ＧａＡＳ−ＦＥＴの基本構成図は第１図に示すようにＧ
ａＡＳ基板結晶４の表面にソース１、ドレイン２電極と
、この間隔にゲート３電極をもつ構造になっている。半
絶縁性ＧａＡ３４内に、オーミックをとるためのｎ＋層
５とＦＥＴ動作をさせる能動層６の領域がある。性能向
上にはソース１、ドレイン２間の直列抵抗を下げ、ゲー
ト３電極の静喧容量全小さくする必要があシ、このため
プロセス上の加工技術では、サブミクロンの加工と重ね
合せ精度を向上させる必要がある。従来の光露光による
加工技術ではゲート長が１μｍ以上しか実現できず、重
ね合せ精度もあまりよくなかった。The basic configuration diagram of GaAS-FET is shown in Figure 1.
The structure has a source 1 and a drain 2 electrodes on the surface of the aAS substrate crystal 4, and a gate 3 electrode at this interval. In the semi-insulating GaA 34, there are an n+ layer 5 for ohmic control and an active layer 6 for FET operation. In order to improve performance, it is necessary to lower the series resistance between source 1 and drain 2 and to reduce the total static capacitance of gate 3 electrode.For this reason, in process technology, submicron processing and overlay accuracy must be improved. It is necessary to do so. Conventional processing techniques using light exposure could only achieve a gate length of 1 μm or more, and the overlay accuracy was not very good.
本発明は、従来の光露光法によっても、セルファライン
技術によって、サブミクロンの加工と重ね合せ精度を同
時に向上した半導体製造装置の製法と提供したものであ
る。The present invention provides a method for manufacturing a semiconductor manufacturing apparatus that simultaneously improves submicron processing and overlay accuracy using the conventional light exposure method and the Selfaline technology.
以下、第２図を用いて本発明の一実施例を説明すると共
に本発明の詳細な説明する。Hereinafter, one embodiment of the present invention will be described using FIG. 2, and the present invention will be explained in detail.
第２図はＧａＡＳ−ＦＥ’ｌ’の製造工程図である。FIG. 2 is a manufacturing process diagram of GaAS-FE'I'.
半絶縁性ＧａＡＳ基板結晶１１の所要部分にあらかじめ
ホトレジストをマスクとしてＳｉイオンと打込み、熱処
理してｎ形動作層１２を形成する。Using a photoresist as a mask, Si ions are implanted in advance into required portions of the semi-insulating GaAS substrate crystal 11, and heat treated to form the n-type active layer 12.
ＧａＡＳ表面に５Ｉ０２膜２１と蒸着Ｓｉ膜２２を被着
してホトリングラフィ技術によってこれらの膜を加工す
る。各膜の厚さはそれぞれ数百ｎｍで、５ＩＯｚとＳｉ
膜はそれぞれリアクティブイオンエッチの反応ガスを選
別することで選択的にエツチングが可能である。パター
ン加工後、高濃度のＳｉイオンを打込んで熱処理によっ
てｎゝ形ネオ−ミツ２層１３形成する。この後、ｓｉｏ
、膜のみをサイドエッチしてパターンの断面形状を１字
形に加工する（第２図（ａ月。この構造は約９００Ｃの
熱処理に対してＱａＡｓの結晶性を劣化させることがな
いので、イオン打込み後のアニールにもパターンを残し
たまま処理できる特徴を有する。A 5I02 film 21 and a vapor-deposited Si film 22 are deposited on the GaAS surface, and these films are processed by photolithography. The thickness of each film is several hundred nm, and 5IOz and Si
The films can be selectively etched by selecting reactive ion etching reaction gases. After patterning, a high concentration of Si ions is implanted and a heat treatment is performed to form an n-shaped neo-mitsu layer 13. After this, sio
, only the film is side-etched to make the cross-sectional shape of the pattern into a single character shape (Fig. It has the feature that it can be processed with the pattern left intact even during subsequent annealing.
つづいて、ＧａＡＳ結晶１１の表面にポジ形ホトレジス
ト（例えばＡＺ１３５０Ｊ）を２〜３μｍの厚さに塗布
して、表面を平坦化させたあと、全面に紫外線と照射し
、現像する。この処理によって、サイドエッチされたパ
ターンの側面のみのレジス）３１が未照射のため残る（
第２図の））。この工程は、平行平板形のアッシャ装置
によっても処理することができる。ＡｕＧｅの合金４１
．４２を蒸着によって被着し、つづいてレジスト除去液
に浸し、サイドエッチされた側面に残したレジストを取
去る。約４００Ｃの熱処理によってｎ”−ＧａＡＳ１３
とＡｕＧｅ４１ をオーミック接触させる（第２図（
Ｃ）〕。側面につけたレジスト３１はＡ ＬＩ Ｑ ｅ
被着時の廻シ込みをさけるため有効である。つづいて、
この表面ｔ−ｆ、Ｑうように高分子樹脂５１（例えばホ
トレジスト〕を塗布して、表面を平坦にする。このあと
アッシャ装置を用いて高分子樹脂をエツチングして、パ
ターン２１，２２．４２の上面が露出した所で止める（
第２図（ｄ））。イオンミリング装置を用いて表面から
不用のＡｕＧｅ４２を取去ったあと、ドライエツチング
でＳ＋２Ｚおよび５ｉ０２２１を取去シ、孔６１をあけ
る（第２図（ｅ））。ここまでの工程によって、最初に
形成されたパターンと同一寸法、同一形状をもつ反転パ
ターンが高分子樹脂５１にレプリカされたことになる。Subsequently, a positive photoresist (for example, AZ1350J) is applied to a thickness of 2 to 3 μm on the surface of the GaAS crystal 11 to flatten the surface, and then the entire surface is irradiated with ultraviolet rays and developed. By this process, the resist (31) only on the side surface of the side-etched pattern remains because it has not been irradiated (
)) in Figure 2). This step can also be performed using a parallel plate type asher device. AuGe alloy 41
．． 42 is deposited by vapor deposition and then immersed in a resist removal solution to remove the resist left on the side-etched sides. n”-GaAS13 by heat treatment at about 400C
and AuGe41 are brought into ohmic contact (Fig. 2 (
C)]. The resist 31 attached to the side is A LI Q e
This is effective in avoiding twisting when adhering. Continuing,
A polymer resin 51 (for example, photoresist) is coated on the surface t-f, Q to make the surface flat.After that, the polymer resin is etched using an asher device to form patterns 21, 22, 42. Stop when the top surface of is exposed (
Figure 2(d)). After removing unnecessary AuGe 42 from the surface using an ion milling device, S+2Z and 5i0221 are removed by dry etching, and a hole 61 is made (FIG. 2(e)). Through the steps up to this point, an inverted pattern having the same dimensions and shape as the initially formed pattern has been replicated on the polymer resin 51.
つづいてゲート金属（例えばＴｉ／Ｐｔ／Ａｕと連続的
に蒸着）７１．７２を被着したあと、再々度レジスト（
例えばＡＺ１３５０Ｊ ）７３を厚く塗布する（第２図
（ｆ））。試料表面の一部にゲート金属７２０表面が現
われるまで、レジストをアッシャ装置を用いて一様に削
る。これによってゲート電極８１上のみにレジスト８２
が残され、つづいてイオンミリング装置を用いて、不用
のゲート金属を除去することができる（第２図（ｇ））
。高分子樹脂５１を取シ去ってソース８２、ドレイン８
３およびゲート８１電極をもつＧａＡＳ−ＦＥＴが作成
されたく第２図小））。Subsequently, after depositing the gate metal (e.g. sequentially deposited with Ti/Pt/Au) 71, 72, the resist (
For example, apply a thick coat of AZ1350J) 73 (Fig. 2(f)). The resist is uniformly scraped using an asher device until the surface of the gate metal 720 appears on a part of the sample surface. As a result, the resist 82 is formed only on the gate electrode 81.
is left behind, and then the unnecessary gate metal can be removed using an ion milling device (Figure 2 (g)).
. After removing the polymer resin 51, the source 82 and drain 8
A GaAS-FET with 3 and 81 gate electrodes was fabricated (Fig. 2, small)).
ｎ＋−オーミック層の形成に必要な熱処理に耐えるバク
ーン構造は、前記の実施例で述べた他に、Ｓ ｉＣｈ
ｔ Ｓ’３Ｎ４ ＋ Ｓ ｉ、 Ｐｓｏ （リン含有
ガラス）、Ｗ、Ｔｉ、ＭＯなどの材料全任意に組合せて
も可能である。また、二層の断面構造が丁字形であるこ
とも本質的なことでなく、例えば三層を用いた１字形の
断面であってもよいことは言うに及ばない。The Bakun structure that can withstand the heat treatment necessary for forming the n+-ohmic layer can be used in addition to those described in the above embodiments.
Any combination of materials such as t S'3N4 + Si, Pso (phosphorus-containing glass), W, Ti, and MO is also possible. Further, it is not essential that the cross-sectional structure of the two layers be T-shaped, and it goes without saying that it may be a single-shaped cross-section using three layers, for example.
本発明によれば、ソースおよびドレイン電極に対してゲ
ート電極がセルフアラインメントで形成できるので、各
部分の寸法を従来法で作ったものより縮めることができ
、これによってＦＥＴ％性の性能を向上できる効果があ
る。またソースおよびドレイン電極の直下にｎ＋−オー
ミック層をイオン打込みで形成できるので、直列抵抗を
下げる効果がある。ソース、ドレインおよびゲート電極
の形成に本発明では、高分子樹脂で決める形状、寸法を
基本としているため、蒸着時の廻シ込みやプロセス上で
の加工精度の劣化といった問題点が一斉なく、また高分
子樹脂のため加工後の除去が容易であり、これに附ずい
したプロセス・マージンが向上できる効果がある。According to the present invention, since the gate electrode can be formed in self-alignment with respect to the source and drain electrodes, the dimensions of each part can be made smaller than those made by conventional methods, thereby improving the FET performance. effective. Furthermore, since an n+-ohmic layer can be formed directly under the source and drain electrodes by ion implantation, the series resistance can be reduced. In the present invention, the shapes and dimensions of the source, drain, and gate electrodes are basically determined by the polymer resin, so there are no problems such as cutting in during vapor deposition or deterioration of processing accuracy during the process. Since it is a polymeric resin, it can be easily removed after processing, and has the effect of improving the associated process margin.
第１図はＧａＡＳ−ＦＥＴの断面図、第２図は本発明゛
の一実施例によるＦ Ｅ Ｔの製造工程図である。
１１・・・基板、１３・・・不純物領域、４１・・・絶
縁層、５１・・・高分子樹脂層、８１・・・ゲート電極
、８２・・・第 １ 目
′ｖＪ２FIG. 1 is a sectional view of a GaAS-FET, and FIG. 2 is a manufacturing process diagram of an FET according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 11... Substrate, 13... Impurity region, 41... Insulating layer, 51... Polymer resin layer, 81... Gate electrode, 82... 1st eye'vJ2
Claims (1)
してこの間にゲート電極を加工する際、ゲート電極に対
応する箇所に耐熱性の良い材料からなるパターンを形成
する工程と、前記半導体基板に、イオン打込みをして熱
処理する工程と、上記パターンの一部にサイドエッチを
施こす工程と、このサイドエッチされた側面に第１の高
分子樹脂を埋め、ソースおよびドレイン電極？形成する
工程と、前記第１の高分子樹脂を除去する工程と第２の
高分子樹脂をこれまで準備した半導体基板上に充てんし
て上記パターンの反転複製を作る工程と、ゲート金属を
被着して高分子樹脂をこの上面に覆う工程と、ゲート電
極？加工する工程と？有することを特徴とする半導体装
置の製法。1. When forming source and drain electrodes on a predetermined semiconductor substrate and processing a gate electrode between them, a step of forming a pattern made of a material with good heat resistance at a location corresponding to the gate electrode, and a step of forming a pattern made of a material with good heat resistance on the semiconductor substrate. , a step of performing ion implantation and heat treatment, a step of performing side etching on a part of the pattern, and filling the side etched side surface with a first polymer resin to form source and drain electrodes. a step of forming the first polymer resin; a step of removing the first polymer resin; a step of filling the semiconductor substrate prepared so far with a second polymer resin to create an inverted copy of the pattern; and depositing a gate metal. The process of covering this top surface with polymer resin and the gate electrode? What is the processing process? A method for manufacturing a semiconductor device comprising:
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13192982A JPS5923565A (en) | 1982-07-30 | 1982-07-30 | Manufacture of semiconductor device |
| US06/517,409 US4561169A (en) | 1982-07-30 | 1983-07-26 | Method of manufacturing semiconductor device utilizing multilayer mask |
| CA000433478A CA1206626A (en) | 1982-07-30 | 1983-07-28 | Method of manufacturing semiconductor device |
| EP83107520A EP0101960B1 (en) | 1982-07-30 | 1983-07-29 | Method of manufacturing a semiconductor device having a self-aligned gate electrode |
| KR1019830003551A KR910006673B1 (en) | 1982-07-30 | 1983-07-29 | Manufacturing method of semiconductor device |
| DE8383107520T DE3378239D1 (en) | 1982-07-30 | 1983-07-29 | Method of manufacturing a semiconductor device having a self-aligned gate electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13192982A JPS5923565A (en) | 1982-07-30 | 1982-07-30 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5923565A true JPS5923565A (en) | 1984-02-07 |
| JPH0358176B2 JPH0358176B2 (en) | 1991-09-04 |
Family
ID=15069502
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13192982A Granted JPS5923565A (en) | 1982-07-30 | 1982-07-30 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5923565A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61163662A (en) * | 1985-01-14 | 1986-07-24 | Agency Of Ind Science & Technol | Manufacture of field-effect transistor |
| JP2014099463A (en) * | 2012-11-13 | 2014-05-29 | Mitsubishi Electric Corp | Semiconductor device manufacturing method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5852880A (en) * | 1981-09-25 | 1983-03-29 | Oki Electric Ind Co Ltd | Manufacture of semiconductor element |
| JPS5896769A (en) * | 1981-12-04 | 1983-06-08 | Oki Electric Ind Co Ltd | Manufacture of semiconductor element |
-
1982
- 1982-07-30 JP JP13192982A patent/JPS5923565A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5852880A (en) * | 1981-09-25 | 1983-03-29 | Oki Electric Ind Co Ltd | Manufacture of semiconductor element |
| JPS5896769A (en) * | 1981-12-04 | 1983-06-08 | Oki Electric Ind Co Ltd | Manufacture of semiconductor element |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61163662A (en) * | 1985-01-14 | 1986-07-24 | Agency Of Ind Science & Technol | Manufacture of field-effect transistor |
| JP2014099463A (en) * | 2012-11-13 | 2014-05-29 | Mitsubishi Electric Corp | Semiconductor device manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0358176B2 (en) | 1991-09-04 |
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