JPS5923522A - Dry etching method - Google Patents
Dry etching methodInfo
- Publication number
- JPS5923522A JPS5923522A JP13349282A JP13349282A JPS5923522A JP S5923522 A JPS5923522 A JP S5923522A JP 13349282 A JP13349282 A JP 13349282A JP 13349282 A JP13349282 A JP 13349282A JP S5923522 A JPS5923522 A JP S5923522A
- Authority
- JP
- Japan
- Prior art keywords
- film
- pattern
- etching
- etched
- dry etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 16
- 238000001312 dry etching Methods 0.000 title claims abstract description 9
- 239000000463 material Substances 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 150000002500 ions Chemical class 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 7
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 229920005591 polysilicon Polymers 0.000 description 6
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- -1 arsenic ions Chemical class 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 101150071604 Atf5 gene Proteins 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、たとえば半導体材料のパターン形成における
ドライエツチング方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a dry etching method, for example in the patterning of semiconductor materials.
従来例の構成とその問題点
超ＬＳＩプロセスにおける、たとえば配線用材の微細パ
ターン形成にはドライエツチングが行われる。この方法
によるパターン形成はサイドエッチが少く、エツチング
パターンの壁面は垂直である。Conventional Structure and Problems In the VLSI process, dry etching is used, for example, to form fine patterns on wiring materials. Pattern formation by this method involves less side etching, and the walls of the etched pattern are vertical.
しかしながら、超ＬＳＩプロセスにおいては、エツチン
グ後、この形成されたパターンの上に、Ｓ ｉ０２ や
ＰＳＧあるいはその他の絶縁膜、あるいはＡｔなどの配
線被膜材料の層が重ねて形成される場合には、その下層
材料のパターンの端面が垂直壁面であると、この上の被
膜材料の被覆性が不十分で、しばしばこのパターンの端
部での、被膜にピンホールが発生したり、あるいは、被
膜がＭなどの配線材料であれば、それが断線を生じたり
する。このため、エツチングパターン断面形状に傾斜（
テーバ）をもたせて、そのパターン上に形成する被膜の
被覆性（ステップカバレッジ）を良くすることが必要で
ある。従来は、ウェットエツチング方法により、パター
ン壁面の横方向にエツチングして、エツチング断面に傾
斜を持たせることが行われるが、エツチング液組成、液
温の温度の変動により傾斜度のコントロールが困難であ
った０
発明の目的
本発明は、半導体装置における下層材料のパターン形成
の際に、被エツチング材料のエツチング断面形状に傾斜
をもたせるための方策を提供するものであり、これによ
り、この下層材料の表面側に形成される、絶縁膜や配線
被膜の被覆度を良くすることができる。However, in the VLSI process, when a layer of Si02, PSG, or other insulating film, or a wiring film material such as At is formed on the formed pattern after etching, If the end face of the pattern of the underlying material is a vertical wall surface, the coverage of the overlying film material is insufficient, and pinholes often occur in the film at the ends of this pattern, or the film is exposed to M, etc. If the wiring material is used, it may cause disconnection. Therefore, the cross-sectional shape of the etching pattern is inclined (
It is necessary to improve the coverage (step coverage) of the film formed on the pattern. Conventionally, a wet etching method is used to etch the pattern wall surface in the lateral direction to create a slope in the etched cross section, but it is difficult to control the degree of slope due to fluctuations in the etching solution composition and liquid temperature. OBJECTS OF THE INVENTION The present invention provides a method for imparting a slope to the etched cross-sectional shape of a material to be etched when patterning a lower layer material in a semiconductor device. The degree of coverage of the insulating film and wiring film formed on the side can be improved.
発明の構成
本発明は基板表面に形成された、被エツチング材料をド
ライエツチングによりパターン形成するに際し、あらか
じめ、前記被エツチング材料表面にｌＸ１０ ｃｍ
以上の高ドーズ量のイオンを注入し、しかる後に、圧
力１００ ｍ Ｔｏｒ ｒ以上で、前記被エツチング材
料を選択的にドライエツチングして、テーパ形状のエツ
チング断面を得ることを特徴とする。Structure of the Invention In the present invention, when forming a pattern on a material to be etched formed on the surface of a substrate by dry etching, a pattern of 1×10 cm is applied to the surface of the material to be etched in advance.
The method is characterized in that ions are implanted at a high dose as described above, and then the material to be etched is selectively dry etched at a pressure of 100 mTorr or more to obtain a tapered etched cross section.
この方法において、高ドーズ量で、被エツチング材料表
面にイオンを注入することにより、イオン衝撃と、表面
からの注入された不純物の濃度分布に従って、表面近傍
はど、ドライエツチングの際のラジカルによるエツチン
グ速度が高くなる。In this method, by implanting ions into the surface of the material to be etched at a high dose, ion bombardment and the concentration distribution of the implanted impurities from the surface cause etching near the surface by radicals during dry etching. The speed will be higher.
その結果、エツチング断面はテーパ（傾斜）状となる。As a result, the etched cross section becomes tapered.
この際、エネルギー量により注入イオンの深さと濃度を
コントロールすることにより、この傾斜角をコントロー
ルできる。At this time, this tilt angle can be controlled by controlling the depth and concentration of the implanted ions depending on the amount of energy.
実施例の説明
第１図、第２図は本発明の実施例を工程の前後で示す断
面図である。半導体基板１上に絶縁膜２を介して、たと
えばＭＯ３半導体装置のゲートおよび配線となるポリシ
リコン膜３を厚さｓｏｏ。DESCRIPTION OF EMBODIMENTS FIGS. 1 and 2 are sectional views showing an embodiment of the present invention before and after the process. A polysilicon film 3, which will become, for example, a gate and wiring of an MO3 semiconductor device, is formed on a semiconductor substrate 1 via an insulating film 2 to a thickness of about 10 oz.
人形成し、この後、エネルギー１６０ ＫｅＶ 、ドー
ズ量６×１０ α でひ素イオンを、既存のイオン注入
装置でこのポリシリコン膜３に注入する。Thereafter, arsenic ions are implanted into this polysilicon film 3 using an existing ion implantation device at an energy of 160 KeV and a dose of 6×10 α.
次いで、エツチングマスクとなるレジストパターン４を
形成し、その後、ＣＦ４および０２の混合ガスを用いて
、圧力２００ ｎｔ Ｔｏｒｒ 、電力５００Ｗで、こ
のポリシリコン膜３をエツチングする。この場合、深さ
方向に対して、ポリシリコン膜３の表面近傍の横方向へ
のエツチング速度は約１．７倍となり、垂直方向に対し
て約６０’の傾斜面が得られた。Next, a resist pattern 4 serving as an etching mask is formed, and then this polysilicon film 3 is etched using a mixed gas of CF4 and 02 at a pressure of 200 nt Torr and power of 500 W. In this case, the etching rate in the lateral direction near the surface of the polysilicon film 3 was about 1.7 times that in the depth direction, and a slope of about 60' with respect to the vertical direction was obtained.
発明の効果
本発明によれば、イオン注入のドース量を制御すること
によりエツチング断面３０〜６０°の傾斜角を任意にコ
ントロールでき、被エツチング材料を被覆する絶縁膜や
、配線材料膜の被覆度も良く、ピンホールや、段切れの
発生が著しく抑制できる。Effects of the Invention According to the present invention, by controlling the dose of ion implantation, the angle of inclination of the etched cross section of 30 to 60 degrees can be arbitrarily controlled, and the degree of coverage of the insulating film covering the material to be etched and the wiring material film can be adjusted. It is possible to significantly suppress the occurrence of pinholes and breakage.
なお、この方法は実施例のポリシリコン膜に限らず、Ｓ
ｔ、２．ＰＳＧ、５ｔ３Ｎ４．Ａｔｆｘど、半導体プロ
セスにおける、どの被エツチング材料にも使用でき、注
入するイオンも、アルゴンなどの不活性ガスイオンや、
通常の半導体プロセスに用いられる、ホウ素やリンも用
いることが可能である。Note that this method is applicable not only to the polysilicon film in the example but also to S
t, 2. PSG, 5t3N4. Atfx can be used for any material to be etched in the semiconductor process, and the ions to be implanted can be inert gas ions such as argon,
It is also possible to use boron and phosphorus, which are used in normal semiconductor processes.
第１図、第２図は本発明実施例の工程前後の状態を示す
断面図である。
１・・・・・・半導体基板、２・・・・・・絶縁膜、３
・・・・・・ポリシリコン（被エツチング材料）膜、４
・・・・・・エツチングマスク。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図
第２図FIGS. 1 and 2 are cross-sectional views showing the state before and after the process of the embodiment of the present invention. 1... Semiconductor substrate, 2... Insulating film, 3
...Polysilicon (material to be etched) film, 4
...Etching mask. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2
Claims (1)
ングによりパターン形成するに際し、あらかじめ前記被
エツチング材料表面に１Ｘ１ｏ１５α−２以上の高ドー
ズ量にイオン注入し、しかる後に、圧力１００ｍＴｏｒ
ｒ以上で、前記被エツチング材料を選択的にドライエツ
チングして、テーバ形状エツチング断面を得ることを特
徴とするドライエツチング方法。When patterning a material to be etched formed on the surface of a substrate by dry etching, ions are implanted into the surface of the material to be etched in advance at a high dose of 1X1o15α-2 or more, and then a pressure of 100 mTorr is applied.
A dry etching method characterized in that the material to be etched is selectively dry etched at an etching depth of r or more to obtain a tapered etched cross section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13349282A JPS5923522A (en) | 1982-07-29 | 1982-07-29 | Dry etching method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13349282A JPS5923522A (en) | 1982-07-29 | 1982-07-29 | Dry etching method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5923522A true JPS5923522A (en) | 1984-02-07 |
Family
ID=15106028
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13349282A Pending JPS5923522A (en) | 1982-07-29 | 1982-07-29 | Dry etching method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5923522A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59141232A (en) * | 1983-02-02 | 1984-08-13 | Seiko Instr & Electronics Ltd | Manufacture of semiconductor device |
| US4718973A (en) * | 1986-01-28 | 1988-01-12 | Northern Telecom Limited | Process for plasma etching polysilicon to produce rounded profile islands |
| US5258332A (en) * | 1987-08-28 | 1993-11-02 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor devices including rounding of corner portions by etching |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4880440A (en) * | 1972-02-02 | 1973-10-27 | ||
| JPS5694759A (en) * | 1979-12-28 | 1981-07-31 | Sony Corp | Wiring forming method |
-
1982
- 1982-07-29 JP JP13349282A patent/JPS5923522A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4880440A (en) * | 1972-02-02 | 1973-10-27 | ||
| JPS5694759A (en) * | 1979-12-28 | 1981-07-31 | Sony Corp | Wiring forming method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59141232A (en) * | 1983-02-02 | 1984-08-13 | Seiko Instr & Electronics Ltd | Manufacture of semiconductor device |
| US4718973A (en) * | 1986-01-28 | 1988-01-12 | Northern Telecom Limited | Process for plasma etching polysilicon to produce rounded profile islands |
| US5258332A (en) * | 1987-08-28 | 1993-11-02 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor devices including rounding of corner portions by etching |
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