JPH03297137A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03297137A JPH03297137A JP10095190A JP10095190A JPH03297137A JP H03297137 A JPH03297137 A JP H03297137A JP 10095190 A JP10095190 A JP 10095190A JP 10095190 A JP10095190 A JP 10095190A JP H03297137 A JPH03297137 A JP H03297137A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- interlayer insulating
- resist
- film
- parts
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000011229 interlayer Substances 0.000 claims abstract description 37
- 150000002500 ions Chemical class 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 239000012535 impurity Substances 0.000 claims abstract description 9
- 238000005468 ion implantation Methods 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 206010011732 Cyst Diseases 0.000 description 1
- 238000006364 Duff aldehyde synthesis reaction Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- VYQRBKCKQCRYEE-UHFFFAOYSA-N ctk1a7239 Chemical compound C12=CC=CC=C2N2CC=CC3=NC=CC1=C32 VYQRBKCKQCRYEE-UHFFFAOYSA-N 0.000 description 1
- 208000031513 cyst Diseases 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Drying Of Semiconductors (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置の眉間絶縁膜の平坦化を目的と
した半導体装置の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device for the purpose of planarizing a glabellar insulating film of a semiconductor device.
第２図は従来のこの種の層間絶縁膜の平坦化を示す工程
断面図であり、この図において、１はウェハ基板（配線
形成前までに形成された各種膜を含む） ２は前記ウェ
ハ基板１上に形成された配線パターン、３は前記ウェハ
基板１上全面に形成された層間絶縁膜、４は平坦化のた
めに形成されたレジスト膜である。FIG. 2 is a process cross-sectional view showing the conventional planarization of this type of interlayer insulating film. In this figure, 1 is a wafer substrate (including various films formed before wiring is formed), 2 is the wafer substrate 1 is a wiring pattern formed on the wafer substrate 1, 3 is an interlayer insulating film formed on the entire surface of the wafer substrate 1, and 4 is a resist film formed for planarization.
次に、この平坦化工程について説明する。Next, this planarization process will be explained.
まず、第２図（ａ）に示すように、半導体装置の製造過
程で、配線前までに形成された各種膜パターンを含むウ
ェハ基板１上に、配線パターン２を形成する。さらに、
配線パターン２の上に、層間絶縁膜３を化学的気相成長
法等により形成する。First, as shown in FIG. 2(a), in the process of manufacturing a semiconductor device, a wiring pattern 2 is formed on a wafer substrate 1 including various film patterns formed before wiring. moreover,
An interlayer insulating film 3 is formed on the wiring pattern 2 by chemical vapor deposition or the like.
層間絶縁膜３は、下部配線である配線パターン２の存在
する部分が突出し、逆に配線パターン２のない部分はへ
こんだ状態に、いわゆる凹凸状に形成される（実際には
、配線パターン２を形成前の各種膜の凹凸により複雑な
形状を示すが、ここでは簡略化して示している。）
この状態のまま、層間絶縁膜３の上に次の配線を形成す
ると、配線の段差被覆性が悪くなったり、あるいは写真
製版時のレジスト塗布膜厚がばらついたり、さらにはそ
れによって配線幅がばらつく。すなわち、写真製版時に
は、層間絶縁膜３の凸部はレジストが薄（、凹部は厚く
なっているため、それによって凹部を適正露光条件にす
ると、凸部は露光過剰気味になり、配線幅がばらつく。The interlayer insulating film 3 is formed in a so-called uneven shape, with the part where the wiring pattern 2, which is the lower wiring, is present protruding, and the part where the wiring pattern 2 is not present is concave. Although the shape is complicated due to the unevenness of the various films before formation, it is shown here in a simplified manner.)
If the next wiring is formed on the interlayer insulating film 3 in this state, the step coverage of the wiring will deteriorate, or the thickness of the resist coating during photolithography will vary, and furthermore, the wiring width will vary as a result. . In other words, during photolithography, the resist is thinner in the convex portions of the interlayer insulating film 3 (but thicker in the concave portions), so if the concave portions are subjected to proper exposure conditions, the convex portions will be slightly overexposed and the wiring width will vary. .
また、凸部を適正露光条件にすると、凹部は露光不足と
なり、この場合も配線幅がばらつく。また、配線自身の
凹凸による乱反射により、露光が乱される等の問題が生
じろ。それを解決するため、眉間絶縁膜３を下記のよう
にして平坦化する。Further, when the convex portions are subjected to proper exposure conditions, the concave portions are underexposed, and the wiring width also varies in this case. Further, problems such as exposure disturbance may occur due to diffused reflection due to the unevenness of the wiring itself. In order to solve this problem, the glabellar insulating film 3 is planarized as follows.
すなわち、第２図（ｂ）では、熱処理により、眉間絶縁
膜３をリフローしている。これは熱処理条件、眉間絶縁
膜３の種類、不純物の種類、＃度によって平坦性は異な
るが、第２図（ｂ）では完全に平坦化されていない状態
を示す。That is, in FIG. 2(b), the glabellar insulating film 3 is reflowed by heat treatment. Although the flatness varies depending on the heat treatment conditions, the type of the glabella insulating film 3, the type of impurity, and the #degree, FIG. 2(b) shows a state that is not completely flattened.
これをさらに平坦化するため、従来は第２図（Ｃ）に示
すようにレジスト膜４を厚く塗布しく厚く塗布すると、
レジストの粘性により表面状態は平坦になる。） レジ
スト膜４と層間絶縁膜３のエツチングレートが同じにな
るようなドライエツチング条件で、第２図（ｄ）に示す
ように、層間絶縁膜３の凸部がなくなるまで全面エツチ
ングしていた。In order to further flatten this, conventionally the resist film 4 is coated thickly as shown in FIG. 2(C).
The surface condition becomes flat due to the viscosity of the resist. ) Under dry etching conditions such that the etching rates of the resist film 4 and the interlayer insulating film 3 were the same, the entire surface of the interlayer insulating film 3 was etched until the convex portions disappeared, as shown in FIG. 2(d).
従来の半導体装置の製造方法は、以上のようにして眉間
絶縁膜３の平坦化を行っているので、し・シスト膜４を
厚く塗布しなければならず、また、レジスト膜４を長時
間エツチングすることが必要で、そのため異物等の発生
原因となる等の問題点があった。In the conventional semiconductor device manufacturing method, the glabella insulating film 3 is flattened as described above, so the cyst film 4 must be applied thickly, and the resist film 4 must be etched for a long time. Therefore, there were problems such as the generation of foreign matter and the like.
この発明は、上記のような問題点を解消するためになさ
れたもので、レジス１−膜を薄くできるとともに、ウェ
ットエツチングで短時間で層間絶縁膜の平坦化を図れる
半導体装置の製造方法を得ることを目的とする。This invention has been made to solve the above-mentioned problems, and provides a method for manufacturing a semiconductor device that can thin the resist film and flatten the interlayer insulating film in a short time by wet etching. The purpose is to
この発明に係る半導体装置の製造方法は、層間絶縁膜の
凸部のみにイオン注入できるように、レジストを薄く塗
布するとともに、不純物濃度によるエツチングレートの
差を利用して、層間絶縁膜を平坦化するものである。In the method for manufacturing a semiconductor device according to the present invention, a resist is applied thinly so that ions can be implanted only into the convex portions of the interlayer insulating film, and the interlayer insulating film is flattened by utilizing the difference in etching rate depending on the impurity concentration. It is something to do.
この発明においては、層間絶縁膜の凸部のみに選択的に
イオン注入することから、その不純物濃度の違いにより
、エツチングし・−１・にダが生じ、イオン注入された
層間絶縁膜の凸部のエツチングレートが速くなり、平坦
化される。In this invention, since ions are selectively implanted only into the convex portions of the interlayer insulating film, due to the difference in impurity concentration, duffs occur in the etching process, and the convex portions of the interlayer insulating film into which ions have been implanted are etched. The etching rate becomes faster and the surface becomes flat.
以下、この発明の一実施例を第１図について説明する。 An embodiment of the present invention will be described below with reference to FIG.
第１図において、第２図と同一符号は同じものを示し、
３ａは前記層間絶縁膜３の凸部に選択的にイオン注入さ
れた部分（イオン注入部という）である。In Figure 1, the same symbols as in Figure 2 indicate the same things,
Reference numeral 3a denotes a portion (referred to as an ion implantation portion) where ions are selectively implanted into the convex portion of the interlayer insulating film 3.
次に、平坦化工程について説明する。Next, the planarization process will be explained.
まず、第１図（ａ） （ｂ）に示すように、第２図
（ａ３ （ｂ）と同様にしてウェハ基板１上に配線
パターン２２層間絶Ｒ膜３を形成する。次に、第１図（
ｃ）に示すように、粘性の低いＬ−レス１−膜４を層間
絶縁膜３の凸部がほとんど覆われないように塗布し、そ
の状態でイオン注入する。First, as shown in FIGS. 1(a) and 1(b), a wiring pattern 22 layer interlayer R film 3 is formed on a wafer substrate 1 in the same manner as in FIG. 2(a3(b)). figure(
As shown in c), a low-viscosity L-less 1-film 4 is applied so that the convex portions of the interlayer insulating film 3 are hardly covered, and ions are implanted in this state.
これにより、層間絶縁膜３の凸部に選択的にイオン注入
される。乙のとき、加速電圧は、イオン種が層間絶縁膜
３の凹部にあるレジス１−膜４を突き抜けないように選
ぶ必要がある。As a result, ions are selectively implanted into the convex portions of the interlayer insulating film 3. In case (B), the accelerating voltage must be selected so that the ion species do not penetrate the resist 1-film 4 located in the recessed portion of the interlayer insulating film 3.
次に、第１図（ｄ）に示すように、レジスト膜４を除去
した後、第１図（ｅ）に示すように、層間絶縁膜３をイ
オン注入部３ａとともに全面エツチングする。このとき
、イオン注入で不純物の濃度の高い部分、すなわちイオ
ン注入部３ａは、イオン注入されなかった部分よりエツ
チングレートが速いため、速くエツチングされ、層間絶
縁膜３は平坦化される。平坦化ずろためには、エツチン
グレート比を調整する必要があるが、これはイオン注入
のドーズ量および加速電圧（注入深さ）を適度に選ぶこ
とにより可能となる。また、適度の熱処理による拡散に
より、不純物を深く入れることができる。Next, as shown in FIG. 1(d), after removing the resist film 4, as shown in FIG. 1(e), the entire surface of the interlayer insulating film 3 is etched together with the ion implanted portion 3a. At this time, the portion where the impurity concentration is high due to the ion implantation, that is, the ion implanted portion 3a, has a higher etching rate than the portion where no ions are implanted, and therefore is etched quickly, and the interlayer insulating film 3 is planarized. In order to reduce the planarization shift, it is necessary to adjust the etching rate ratio, which can be achieved by appropriately selecting the ion implantation dose and accelerating voltage (implantation depth). Furthermore, impurities can be introduced deeply by diffusion through appropriate heat treatment.
なお、上記実施例では、層間絶縁膜３を形成した後、熱
処理を加え、リフローしてからレジスト膜４の塗布２イ
オン注入を行っているが、層間絶縁膜３を形成した直後
にレジスト膜４の塗布、イオン注入を行い、熱処理でリ
フローと不純物の拡散を兼ねてもよい。In the above embodiment, after forming the interlayer insulating film 3, heat treatment is applied, and after reflowing, the coating 2 of the resist film 4 is ion implanted. Coating and ion implantation may be performed, and heat treatment may serve both as reflow and impurity diffusion.
以上説明したように、この発明は、ウェハ基板上に配線
パターンを形成した後、全面に層間絶縁膜を形成する工
程２層間絶縁膜の配線パターン上部の凸部となった部分
がほとんど覆われないようにレジスｌ−を塗布し、その
後、シ・シストをマスクにして層間絶縁膜の凸部のみに
選択的にイオン注入する工程、前記レジストを除去した
後、前記イオン注入による不純物濃度の違いによるエラ
チングレー）・の差を利用してエツチングを行う工程に
より、層間絶縁膜を平坦化するようにしたので、異物付
着の要因を除去できるとともに、平坦化の際のエツチン
グに層間絶縁膜の凸部が速くエツチングされ、容易に平
坦化できろ。As explained above, the present invention is a step of forming an interlayer insulating film on the entire surface after forming a wiring pattern on a wafer substrate.The protruding portion of the interlayer insulating film on the upper part of the wiring pattern is hardly covered. After applying a resist l- as shown in FIG. Since the interlayer insulating film is flattened by an etching process that takes advantage of the difference in the etching gray (eratin gray), it is possible to eliminate the cause of foreign matter adhesion, and to prevent convex parts of the interlayer insulating film from being etched during planarization. Etches quickly and flattens easily.
また、イオン注入の不純物濃度の制胛により、さらに精
度よく、平坦化が図れる等の効果がある。In addition, by controlling the impurity concentration during ion implantation, there is an effect that planarization can be achieved with higher accuracy.
第１図はこの発明の一実施例による半導体装置の製造方
法を示す工程断面図、第２図は従来の半導体装置の製造
方法を示す工程断面図である。
図において、１はウェハ基板、２は配線バタン、３は層
間絶縁膜、３ａはイオン注入部、４はレジスｌ−膜であ
る。
なお、各図中の同一符号は同一または相当部分を示す。FIG. 1 is a process sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a process sectional view showing a conventional method for manufacturing a semiconductor device. In the figure, 1 is a wafer substrate, 2 is a wiring button, 3 is an interlayer insulating film, 3a is an ion implantation part, and 4 is a resist l-film. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
間絶縁膜を形成する工程、前記層間絶縁膜の配線パター
ン上部の凸部となった部分がほとんど覆われないように
レジストを塗布し、その後、前記レジストをマスクにし
て前記層間絶縁膜の凸部のみに選択的にイオン注入する
工程、前記レジストを除去した後、前記イオン注入によ
る不純物濃度の違いによるエッチングレートの差を利用
してエッチングを行い、前記層間絶縁膜を平坦化する工
程とからなることを特徴とする半導体装置の製造方法。After forming a wiring pattern on a wafer substrate, a step of forming an interlayer insulating film on the entire surface, applying a resist so that the convex portion of the upper part of the wiring pattern of the interlayer insulating film is hardly covered, and then, A step of selectively implanting ions only into the convex portions of the interlayer insulating film using the resist as a mask, and after removing the resist, etching is performed using a difference in etching rate due to a difference in impurity concentration due to the ion implantation. A method for manufacturing a semiconductor device, comprising the steps of: planarizing the interlayer insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10095190A JPH03297137A (en) | 1990-04-16 | 1990-04-16 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10095190A JPH03297137A (en) | 1990-04-16 | 1990-04-16 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03297137A true JPH03297137A (en) | 1991-12-27 |
Family
ID=14287662
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10095190A Pending JPH03297137A (en) | 1990-04-16 | 1990-04-16 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03297137A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970003651A (en) * | 1995-06-20 | 1997-01-28 | BPS film planarization method of semiconductor device | |
| KR20000017361A (en) * | 1998-08-18 | 2000-03-25 | 칼 하인쯔 호르닝어 | Method for producing semiconductor-insulator layer and semiconductor component having the semiconductor-insulator layer |
| DE10329389A1 (en) * | 2003-06-30 | 2005-02-10 | Advanced Micro Devices, Inc., Sunnyvale | Method for compensating etch rate nonuniformities by ion implantation |
| JP2016225526A (en) * | 2015-06-02 | 2016-12-28 | 株式会社東芝 | Method of manufacturing semiconductor device |
-
1990
- 1990-04-16 JP JP10095190A patent/JPH03297137A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970003651A (en) * | 1995-06-20 | 1997-01-28 | BPS film planarization method of semiconductor device | |
| KR20000017361A (en) * | 1998-08-18 | 2000-03-25 | 칼 하인쯔 호르닝어 | Method for producing semiconductor-insulator layer and semiconductor component having the semiconductor-insulator layer |
| DE10329389A1 (en) * | 2003-06-30 | 2005-02-10 | Advanced Micro Devices, Inc., Sunnyvale | Method for compensating etch rate nonuniformities by ion implantation |
| DE10329389B4 (en) * | 2003-06-30 | 2006-05-04 | Advanced Micro Devices, Inc., Sunnyvale | Method for compensating etch rate nonuniformities by ion implantation |
| US7098140B2 (en) | 2003-06-30 | 2006-08-29 | Advanced Micro Devices, Inc. | Method of compensating for etch rate non-uniformities by ion implantation |
| JP2016225526A (en) * | 2015-06-02 | 2016-12-28 | 株式会社東芝 | Method of manufacturing semiconductor device |
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