JPS5922533U - flip-flop circuit - Google Patents
flip-flop circuitInfo
- Publication number
- JPS5922533U JPS5922533U JP11796282U JP11796282U JPS5922533U JP S5922533 U JPS5922533 U JP S5922533U JP 11796282 U JP11796282 U JP 11796282U JP 11796282 U JP11796282 U JP 11796282U JP S5922533 U JPS5922533 U JP S5922533U
- Authority
- JP
- Japan
- Prior art keywords
- flip
- flop
- flop circuit
- break
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は本考案の一実施例の回路図、第2図はそのタイ
ミング波形図である。
1・・・・・・単安定マルチバイブレーク、2・・・・
・・71Jツブフロツプ、3・・・・・・インバータ、
4・・・・・・フリップフロップ、a、aa・・・・・
・入力信号、b、bb・・・・・・入力クロック信号、
c、CC・・・・・・単安定マルチバイブレーク出力、
d、dd・・・・・・クロック出力、e。
ee・・・・・・データ出力Q、 f・・・・・・デー
タ出力Q1g・・・・・・プリセット入力、h・・・・
・・クリア入力、i、j・・・・・・外部CR端子、B
1〜B4・・・・・・入力クロック信号のエッヂ、C1
〜C4・・・・・・単安定マルチバイブレータ出力信号
のエッヂ、D1〜D2・・・・・・クロック −出力信
号のエッヂ、El・・・・・・データ出力信号の変化点
。FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a timing waveform diagram thereof. 1... Monostable multibibreak, 2...
...71J tube flop, 3...Inverter,
4...Flip-flop, a, aa...
・Input signal, b, bb... Input clock signal,
c, CC... Monostable multi-bi break output,
d, dd... Clock output, e. ee...Data output Q, f...Data output Q1g...Preset input, h...
...Clear input, i, j...External CR terminal, B
1 to B4...Edge of input clock signal, C1
~C4... Edge of monostable multivibrator output signal, D1-D2... Edge of clock -output signal, El... Change point of data output signal.
Claims (1)
と、クロック信号でトリガされる単安定マルチバイブレ
ーク素子と、該単安定マルチバイブレークの出力信号に
よって動作する第2のフリップフロップ素子とを有し、
該第2フリツプフロツプ素子の出力信号により前記第1
のフリップフロップ素子の入力動作を制御するようにし
たことを特徴とするフリップフロップ回路。A first flip-flop element for reading an input signal, a monostable multi-bi break element triggered by a clock signal, and a second flip-flop element operated by an output signal of the monostable multi-bi break,
The output signal of the second flip-flop device causes the first
A flip-flop circuit characterized in that the input operation of a flip-flop element is controlled.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11796282U JPS5922533U (en) | 1982-08-03 | 1982-08-03 | flip-flop circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11796282U JPS5922533U (en) | 1982-08-03 | 1982-08-03 | flip-flop circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5922533U true JPS5922533U (en) | 1984-02-10 |
Family
ID=30271329
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11796282U Pending JPS5922533U (en) | 1982-08-03 | 1982-08-03 | flip-flop circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5922533U (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5085224A (en) * | 1973-11-28 | 1975-07-09 |
-
1982
- 1982-08-03 JP JP11796282U patent/JPS5922533U/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5085224A (en) * | 1973-11-28 | 1975-07-09 |
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