JPH0481327B2 - - Google Patents
Info
- Publication number
- JPH0481327B2 JPH0481327B2 JP57163462A JP16346282A JPH0481327B2 JP H0481327 B2 JPH0481327 B2 JP H0481327B2 JP 57163462 A JP57163462 A JP 57163462A JP 16346282 A JP16346282 A JP 16346282A JP H0481327 B2 JPH0481327 B2 JP H0481327B2
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- polycrystalline silicon
- mask
- impurity
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000012535 impurity Substances 0.000 claims description 28
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 18
- 239000004065 semiconductor Substances 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 238000009792 diffusion process Methods 0.000 description 10
- 238000002513 implantation Methods 0.000 description 8
- 238000005468 ion implantation Methods 0.000 description 7
- 238000000137 annealing Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 230000004913 activation Effects 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- -1 arsenic ions Chemical class 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000010128 melt processing Methods 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Description
【発明の詳細な説明】
ａ 発明の技術分野
微細寸法長のゲート電極に於けるホツトキヤリ
ア効果を防止するに有効な浅いドレイン領域を形
成するLDD（Lightly Doped Drain）構造体をな
す半導体装置の製造方法に関する。[Detailed Description of the Invention] a. Technical Field of the Invention A method for manufacturing a semiconductor device having an LDD (Lightly Doped Drain) structure that forms a shallow drain region that is effective in preventing hot carrier effects in gate electrodes with minute dimensions. Regarding.
ｂ 技術の背景
MOS型集積回路はメモリ、マイクロプロセツ
サへの応用が広がると共に多結晶シリコンをゲー
ト電極とするｎチヤンネル型OSIC、LSIが多く
用いられる。近年イオン打込技術、選択酸化技
術、多結晶シリコン電極形成技術の発展に伴い、
MOS型デバイスがLSIの主流となつている。例
えばイオン打込技術が広く使用されるのは低濃度
領域での制御性の良さを利用して、ゲート領域に
不純物を打込み、不純物濃度を変えることによる
しきい値（Vth）の制御である。一方選択酸化技
術の基本は窒化シリコン膜（Si3N4）が酸化され
にくいことを利用して、MOSIC、LSIのフイー
ルド部に厚い二酸化シリコン膜（SiO2）を形成
させることにありこの利点は二酸化シリコン膜が
厚くても平坦になると共にフイールド部分の酸化
前に基板のSi部分に不純物をドープすることによ
り選択的にフイールド部分の濃度が制御できる。
即ち寄生MOS素子の防止が可能となる。また多
結晶シリコンをゲート電極するMOSプロセスの
特徴はゲート電極となる多結晶シリコンを拡散マ
スクにしてソース、ドレインを形成することにあ
る。このためゲート電極とソース、ドレインとの
重なりは拡散層の横方向への広がりによつて決ま
るため重なり部分を1μｍ以下にすることができ
ゲートドレイン間容量が小さくなる。又配線とし
て拡散層、多結晶シリコン、アルミ電極の三層が
利用できる利点がある。b. Background of the Technology MOS type integrated circuits are increasingly being applied to memories and microprocessors, and n-channel type OSICs and LSIs with polycrystalline silicon gate electrodes are often used. In recent years, with the development of ion implantation technology, selective oxidation technology, and polycrystalline silicon electrode formation technology,
MOS type devices have become the mainstream of LSI. For example, ion implantation technology is widely used to control the threshold value (Vth) by implanting impurities into the gate region and changing the impurity concentration, taking advantage of its good controllability in low concentration regions. On the other hand, the basis of selective oxidation technology is to utilize the fact that silicon nitride film (Si 3 N 4 ) is difficult to oxidize to form a thick silicon dioxide film (SiO 2 ) in the field part of MOSIC and LSI. Even if the silicon dioxide film is thick, it becomes flat, and the concentration in the field portion can be selectively controlled by doping the Si portion of the substrate with impurities before oxidizing the field portion.
That is, parasitic MOS elements can be prevented. A feature of the MOS process using polycrystalline silicon as a gate electrode is that the source and drain are formed using polycrystalline silicon, which will serve as the gate electrode, as a diffusion mask. Therefore, since the overlap between the gate electrode, source, and drain is determined by the lateral spread of the diffusion layer, the overlap can be reduced to 1 μm or less, and the capacitance between the gate and drain can be reduced. Another advantage is that three layers, the diffusion layer, polycrystalline silicon, and aluminum electrode, can be used as wiring.
ｃ 従来技術と問題点
第１図は従来のｎチヤンネル型シリコンゲート
構造のMOSトランジスタの製造プロセスを示す
工程図である。c. Prior Art and Problems FIG. 1 is a process diagram showing the manufacturing process of a conventional n-channel silicon gate structure MOS transistor.
図中Ａに示すようなＰ型シリコン基板１の表面
を1.5μｍ程度高温酸化させて酸化膜（SiO2）２を
形成し、次いで活性領域全体の酸化膜２を除去す
る。次いでＢに示すようにい酸化膜２を除去した
活性領域にゲート酸化膜３を形成する。この場合
ドライ（H2Oを含まない）酸素中での高温熱酸
化法が用いられるがＡの場合はウエツト酸素中で
の厚い酸化膜形成を行なう。次いでＣに示すよう
にCVD法によつて多結晶シリコン４をゲート酸
化膜３上に形成する。次いでＤに示すようにゲー
ト電極５となる部分以外の多結晶シリコン４を除
去したあと更にソースドレイン領域の酸化膜３を
除去する。次いでＥに示すように多結晶シリコン
でなるゲート電極５を拡散マスクとしてイオン打
込によりソース６、ドレイン７拡散を行う。打込
まれる不純物はｎ型の場合りん（Ｐ）或はひ素
（AS）が拡散されてｎ型領域となる。次いでＦに
示すように最終保護膜としてりんシリケートガラ
ス膜（PSG）で被膜し、メルト処理し、更にア
ルミ電極９を蒸着させる。 The surface of a P-type silicon substrate 1 as shown at A in the figure is oxidized at a high temperature of about 1.5 μm to form an oxide film (SiO 2 ) 2, and then the oxide film 2 over the entire active region is removed. Next, as shown in B, a gate oxide film 3 is formed in the active region from which the oxide film 2 has been removed. In this case, a high temperature thermal oxidation method in dry (not containing H 2 O) oxygen is used, but in case A, a thick oxide film is formed in wet oxygen. Next, as shown in C, polycrystalline silicon 4 is formed on gate oxide film 3 by the CVD method. Next, as shown in D, after removing the polycrystalline silicon 4 other than the portion that will become the gate electrode 5, the oxide film 3 in the source and drain regions is further removed. Next, as shown in E, the source 6 and drain 7 are diffused by ion implantation using the gate electrode 5 made of polycrystalline silicon as a diffusion mask. If the implanted impurity is n-type, phosphorus (P) or arsenic (AS) is diffused to form an n-type region. Next, as shown in F, a phosphorus silicate glass film (PSG) is coated as a final protective film, melt processing is performed, and an aluminum electrode 9 is further vapor-deposited.
このようなプロセスによつて構成されるMOS
型半導体装置において１〜2μｍ程度の微細寸法
のゲート長では、ゲート電極とドレイン領域の界
面に電界集中し、動作中にホツトキヤリア効果に
よりしきい値電圧（Vth）、コンダクタンス（β）
が変動し易く信頼性が得られない。このためドレ
イン領域としてゲート電極近傍には浅い不純物拡
散層、隣接する領域に深い不純物拡散層を備えた
LDD（Lightly Doped Drain）構造とすることに
よつてホツトキヤリア効果を防止することに着目
したものである。LDD構造とするための構造プ
ロセスにサイドエツチングがあるその具体例を第
２図によつて示す。 MOS constructed by such a process
In a semiconductor device with a microscopic gate length of about 1 to 2 μm, the electric field concentrates at the interface between the gate electrode and the drain region, and the hot carrier effect causes the threshold voltage (Vth) and conductance (β) to decrease during operation.
tends to fluctuate and reliability cannot be obtained. Therefore, as a drain region, a shallow impurity diffusion layer is provided near the gate electrode, and a deep impurity diffusion layer is provided in the adjacent region.
The focus is on preventing the hot carrier effect by using an LDD (Lightly Doped Drain) structure. A specific example in which side etching is used in the structural process to form an LDD structure is shown in FIG.
(イ)に示すようにゲート電極をなす多結晶シリコ
ン１１上に窒化シリコン（Si3N4）１２及び二酸
化シリコン（SiO2）をパターニング形成し、こ
れをマスクとしてイオン打込を行う。次いで(ロ)に
示すように不純物層のソースドレイン領域１４，
１５を形成し、更に多結晶シリコン１１を円筒型
プラズマエツチング装置によりサイドエツチング
して図のように形成する。次いで(ハ)に示すように
平行平板型プラズマエツチングにより酸化シリコ
ン、窒化シリコン膜をエツチング除去し、更に多
結晶シリコン１１をマスクとしてイオン打込を行
いソースドレイン領域の活性化アニールを行う。
このようなプロセスによつて次の(ニ)に示すように
ソースドレイン領域１４，１５の形状はゲート電
極近傍で浅くなるLDD構造のMOS型半導体装置
が得られる。 As shown in (a), silicon nitride (Si 3 N 4 ) 12 and silicon dioxide (SiO 2 ) are patterned on polycrystalline silicon 11 forming the gate electrode, and ions are implanted using this as a mask. Next, as shown in (b), the source and drain regions 14 of the impurity layer,
15 is formed, and then the polycrystalline silicon 11 is side-etched using a cylindrical plasma etching device to form the shape shown in the figure. Next, as shown in (c), the silicon oxide and silicon nitride films are etched away by parallel plate plasma etching, and ions are implanted using the polycrystalline silicon 11 as a mask to perform activation annealing of the source and drain regions.
Through such a process, as shown in (d) below, a MOS type semiconductor device having an LDD structure in which the shape of the source/drain regions 14 and 15 becomes shallow near the gate electrode can be obtained.
しかしこのプロセスではゲート電極をなす多結
晶シリコン１１を円筒型エツチング装置を用い等
方性エツチングするもので、そのエツチング装置
は反応性ガス例えばCF4（フレオンガス）のグロ
ー放電によつて活性なフツ素（フツォラジカル）
を発生させてこれが多結晶シリコンと反応してエ
ツチングされる時間制御がむづかしく、半導体ウ
エハ間のバラツキが大きい。このため再現性が得
られにくい。また安定性に欠ける憾がある。 However, in this process, the polycrystalline silicon 11 forming the gate electrode is isotropically etched using a cylindrical etching device. (Futso radical)
It is difficult to control the time during which the polycrystalline silicon is generated, reacts with the polycrystalline silicon, and is etched, and there is large variation between semiconductor wafers. For this reason, it is difficult to obtain reproducibility. There is also a problem with the lack of stability.
ｄ 発明の目的
本発明は上記の点に鑑み、LDD構造の半導体
装置の低ドープドレイン領域を再現性よく正確に
形成することを目的とする。d. Object of the Invention In view of the above points, an object of the present invention is to accurately form a lightly doped drain region of a semiconductor device having an LDD structure with good reproducibility.
ｅ 発明の構成
上記目的は本発明によれば、半導体基板上に形
成されたゲート電極に隣接する多結晶シリコンの
マスク体を設けて、該マスク体および該ゲート電
極をマスクとて該半導体基板に不純物を導入する
工程と、前記工程の後に該マスク体を除去して、
該ゲート電極をマスクとして該半導体基板に不純
物を導入する工程を含む製造方法によつて達せら
れる。e Structure of the Invention According to the present invention, the above object is achieved by providing a polycrystalline silicon mask body adjacent to a gate electrode formed on a semiconductor substrate, and applying the polycrystalline silicon mask body and the gate electrode to the semiconductor substrate using the mask body and the gate electrode as a mask. a step of introducing impurities, and removing the mask body after the step,
This is achieved by a manufacturing method including a step of introducing impurities into the semiconductor substrate using the gate electrode as a mask.
ｆ 発明の実施例 以下本発明の実施例を図面により詳述する。f Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.
第３図は本発明の一実施例であるLDD構造の
製造プロセスを示す工程図である。 FIG. 3 is a process diagram showing a manufacturing process of an LDD structure according to an embodiment of the present invention.
(a)に示すようにＰ型シリコン基板２１に形成し
たゲート酸化膜２２上にCVD法により形成した
多結晶シリコン２３を図のようにパターン形成す
ることによりゲート電極２４が得られる。次いで
(b)に示すようにゲート電極２４を含む活性領域内
にCVD法によりシリコン酸化膜（SiO2）２５を
形成し、更に多結晶シリコン２６を被膜形成させ
る。次いで(c)に示すように平行平板型プラズマエ
ツチングで多結晶シリコン２６をパターニング形
成し、図のようなマスク体２７をゲート電極２４
に隣接して形成する。しかる後にゲート電極２４
及ひ第２の多結晶シリコン層２７をマスクとして
第１のイオン打込により高濃度の不純物をドープ
し、ソースドレイン領域の深い不純物注入領域２
８を形成させる。次いで(d)に示すようにマスク体
２７を円筒型プラズマエツチングにより、エツチ
ング除去する。次いでゲート電極２４をマスクと
して第２のイオン打込により低濃度の不純物をド
ープし、ソースドレイン領域の浅い不純物注入領
域２９を形成させる。しかる後に不純物注入領域
２８，２９の活性化アニールを行つて、不純物注
入領域２８及び２９がそれぞれ深い不純物拡散層
及び浅い不純物拡散層となるソースドレイン領域
を形成する。なお、活性化アニールは不純物注入
領域２８または２９を形成した都度行つても良
く、その場合は両アニールの間でアニール条件を
異ならせるもとが可能となる。 As shown in (a), a gate electrode 24 is obtained by patterning polycrystalline silicon 23 formed by CVD on a gate oxide film 22 formed on a P-type silicon substrate 21 as shown in the figure. then
As shown in (b), a silicon oxide film (SiO 2 ) 25 is formed in the active region including the gate electrode 24 by the CVD method, and a polycrystalline silicon 26 is further formed as a film. Next, as shown in (c), the polycrystalline silicon 26 is patterned by parallel plate plasma etching, and the mask body 27 as shown in the figure is formed on the gate electrode 24.
Form adjacent to. After that, the gate electrode 24
Then, using the second polycrystalline silicon layer 27 as a mask, the deep impurity implantation region 2 of the source/drain region is doped with a high concentration impurity by first ion implantation.
Form 8. Next, as shown in (d), the mask body 27 is etched away by cylindrical plasma etching. Next, using the gate electrode 24 as a mask, a second ion implantation is performed to dope impurities at a low concentration to form shallow impurity implanted regions 29 of the source and drain regions. Thereafter, activation annealing is performed on the impurity implanted regions 28 and 29 to form source/drain regions in which the impurity implanted regions 28 and 29 serve as a deep impurity diffusion layer and a shallow impurity diffusion layer, respectively. Note that the activation annealing may be performed each time the impurity implantation region 28 or 29 is formed, and in that case, it is possible to make the annealing conditions different between both annealings.
第１のイオン打込はひ素イオン（As+）を120k
eVのエネルギ、打込ドーズ量４×1015cm-2とする
のに対し弟２のイオン打込では50keV、１×1012cm
-2でドープするとのにより好ましいドレイン領域
が得られる。 The first ion implantation is arsenic ions (As + ) at 120 k
eV energy and implantation dose was 4×10 15 cm -2 , whereas younger brother 2's ion implantation was 50 keV and 1×10 12 cm
A more favorable drain region is obtained by doping with -2 .
次いで(e)に示すようにシリコン酸化膜２５をエ
ツチング除去し、りんシリケートガラス膜３１で
最終的保護膜を行い更にアルミ電極３０を蒸着形
成することによりLDD構造のMOS型半導体装置
が得られる。 Next, as shown in (e), the silicon oxide film 25 is removed by etching, a final protective film is formed with a phosphorus silicate glass film 31, and an aluminum electrode 30 is formed by vapor deposition, thereby obtaining a MOS type semiconductor device with an LDD structure.
このように構造することにより従来構造の半導
体装置に比し安定した特性が得られまたサイドエ
ツチング法に比して本発明は再現性に優れる大き
な利点がある。 With this structure, stable characteristics can be obtained compared to semiconductor devices with conventional structures, and the present invention has the great advantage of superior reproducibility compared to side etching methods.
また、不純物注入領域２９は、不純物注入領域
２８よりも後の工程で形成されて、拡散の進行が
当該活性化アニール以前の工程に伴う加熱の影響
を受けないものとなるので、ソースドレイン領域
の浅い不純物拡散層は、過剰な拡がりを起こすこ
とがなく、ゲート電極２４に対する関係寸法が正
確に形成される。このことから上述の製造手順
は、LDD構造MOS型半導体装置のゲート長を微
細寸法化するのに適している。更にひ素（As）
又はりん（Ｐ）等の不純物を深い不純物領域或は
浅い不純物注入領域に組合せて用いることにより
更に特性の異なる各種のトランジスタが得られ
る。 In addition, since the impurity implantation region 29 is formed in a later step than the impurity implantation region 28, the progress of diffusion is not affected by the heating that accompanies the step before the activation annealing. The shallow impurity diffusion layer does not overextend, and the dimensions relative to the gate electrode 24 are accurately formed. For this reason, the above manufacturing procedure is suitable for miniaturizing the gate length of an LDD structure MOS type semiconductor device. Furthermore, arsenic (As)
Alternatively, by combining an impurity such as phosphorus (P) in a deep impurity region or a shallow impurity implantation region, various transistors with further different characteristics can be obtained.
ｇ 発明の効果
以上詳細に説明したように本発明の構造は、ホ
ツトキヤリア効果を防止するLDD構造のMOS型
半導体装置の製造方法において、ゲート長の微細
寸法化に適するようにしながら、LDD構造を従
来のサイドエツチング処理法よりも再現性よく正
確に形成することを可能にさせる大きな効果があ
る。g. Effects of the Invention As explained in detail above, the structure of the present invention is suitable for manufacturing a MOS semiconductor device with an LDD structure that prevents hot carrier effects, while making it suitable for miniaturization of the gate length. This method has the great effect of enabling accurate formation with better reproducibility than the side etching method described above.
第１図は従来のｎチヤンネル型シリコンゲート
構造のMOSトランジスタの構造プロセスの示す
工程図、第２図はサイドエツチングによるLDD
構造をなすMOSトランジスタの構造プロセスを
示す工程図、第３図は本発明の一実施例である
LDD構造MOS型半導体装置の製造プロセスを示
す工程図である。図中、２１はＰ型シリコン基
板、２２はゲート酸化膜、２３は多結晶シリコ
ン、２４はゲート電極、２５はシリコン酸化膜、
２６は多結晶シリコン、２７は多結晶シリコンの
マスク体、２８は深い不純物注入領域、２９は浅
い不純物注入領域を示す。
Figure 1 is a process diagram showing the structure process of a conventional n-channel type silicon gate structure MOS transistor, and Figure 2 is an LDD using side etching.
Figure 3 is a process diagram showing the structural process of a MOS transistor, which is an embodiment of the present invention.
FIG. 3 is a process diagram showing a manufacturing process of an LDD structure MOS type semiconductor device. In the figure, 21 is a P-type silicon substrate, 22 is a gate oxide film, 23 is polycrystalline silicon, 24 is a gate electrode, 25 is a silicon oxide film,
26 is a polycrystalline silicon mask, 27 is a polycrystalline silicon mask body, 28 is a deep impurity implantation region, and 29 is a shallow impurity implantation region.
Claims (1)
する多結晶シリコンのマスク体を設けて、該マス
ク体および該ゲート電極をマスクとして該半導体
基板に不純物を導入する工程と、 前記工程の後に該マスク体を除去して、該ゲー
ト電極をマスクとして該半導体基板に不純物を導
入する工程を含むことを特徴とする半導体装置の
製造方法。[Claims] 1. A step of providing a polycrystalline silicon mask body adjacent to a gate electrode formed on a semiconductor substrate, and introducing impurities into the semiconductor substrate using the mask body and the gate electrode as a mask; A method for manufacturing a semiconductor device, comprising the step of removing the mask body after the step and introducing impurities into the semiconductor substrate using the gate electrode as a mask.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16346282A JPS5952878A (en) | 1982-09-20 | 1982-09-20 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16346282A JPS5952878A (en) | 1982-09-20 | 1982-09-20 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5952878A JPS5952878A (en) | 1984-03-27 |
| JPH0481327B2 true JPH0481327B2 (en) | 1992-12-22 |
Family
ID=15774333
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16346282A Granted JPS5952878A (en) | 1982-09-20 | 1982-09-20 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5952878A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60245176A (en) * | 1984-05-18 | 1985-12-04 | Matsushita Electric Ind Co Ltd | Manufacture of mis type field effect transistor |
| JPS60244074A (en) * | 1984-05-18 | 1985-12-03 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
| JPH0740604B2 (en) * | 1985-07-30 | 1995-05-01 | ソニー株式会社 | Method for manufacturing MOS semiconductor device |
| JPS6342161A (en) * | 1986-08-07 | 1988-02-23 | Toshiba Corp | Manufacture of cmos type semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5283073A (en) * | 1975-12-29 | 1977-07-11 | Matsushita Electric Ind Co Ltd | Production of semiconductor device |
| JPS5444482A (en) * | 1977-09-14 | 1979-04-07 | Matsushita Electric Ind Co Ltd | Mos type semiconductor device and its manufacture |
| JPS57106169A (en) * | 1980-12-24 | 1982-07-01 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1982
- 1982-09-20 JP JP16346282A patent/JPS5952878A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5283073A (en) * | 1975-12-29 | 1977-07-11 | Matsushita Electric Ind Co Ltd | Production of semiconductor device |
| JPS5444482A (en) * | 1977-09-14 | 1979-04-07 | Matsushita Electric Ind Co Ltd | Mos type semiconductor device and its manufacture |
| JPS57106169A (en) * | 1980-12-24 | 1982-07-01 | Fujitsu Ltd | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5952878A (en) | 1984-03-27 |
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