JPS5920773U - Clock phase control circuit - Google Patents
Clock phase control circuitInfo
- Publication number
- JPS5920773U JPS5920773U JP11331482U JP11331482U JPS5920773U JP S5920773 U JPS5920773 U JP S5920773U JP 11331482 U JP11331482 U JP 11331482U JP 11331482 U JP11331482 U JP 11331482U JP S5920773 U JPS5920773 U JP S5920773U
- Authority
- JP
- Japan
- Prior art keywords
- phase
- clock
- signal
- adaptive
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Television Systems (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は文字放送信号の構成を示す線図、第2図は従来
のクロック位相制御回路の構成を示すブロック線図、第
3図は本考案クロック位相制御回路の全体構成の例を示
すブロック線図、第4図は同じくその各部信号波形を示
す波形図、第5図は同じくその検出開始判定器の構成例
を示すブロック線図、第6図は同じくその検出終了判定
器の構成例を示すブロック線図、第7図は同じくそのク
ロック位相演算器の構成例を示すブロック線図、第8図
は同じくそのフレーミングコード検出器の構成例を示す
ブロック線図である。
1・・・クロック発生器、2・・・タップ付遅延線、3
・・・位相選択器、5・・・フレーミングコード判定部
、6・・・制御部、7・・・カラー副搬送波、8・・・
クロック信号、9・・・遅延クロック信号、10・・・
選択クロック信号、11・・・文字情報信号、12・・
・フレーミングコード検出パルス、13・・・位相選択
信号、14゜30・・・フリップフロップ、15・・・
フレーミングコ ・−ド検出器、16・・・検
出開始判定器、17・・・検出終了判定器、18・・・
クロック位相演算器、19・・・判定開始パルス、20
・・・検出開始位相アドレス、21・・・検出終了位相
アドレス、22・・・サンプルクロック、23・・・検
出終了信号、24・・・検出開始信号、25・・・フレ
ーミングコード検出ゲートパルス、26・・・アンドゲ
ート、27・・・オアゲート、28・・・バイナリ変換
器、29・・・レジスタ、31・・・減算器、32・・
・半減器、33・・・加算器、34・・・フレーミング
コード一致検出器、35・・・シフトレジスタ。Fig. 1 is a diagram showing the structure of a teletext signal, Fig. 2 is a block diagram showing the structure of a conventional clock phase control circuit, and Fig. 3 is a block diagram showing an example of the overall structure of the clock phase control circuit of the present invention. 4 is a waveform diagram showing signal waveforms of each part, FIG. 5 is a block diagram showing an example of the configuration of the detection start determiner, and FIG. 6 is a block diagram showing an example of the configuration of the detection end determiner. FIG. 7 is a block diagram showing an example of the configuration of the clock phase calculator, and FIG. 8 is a block diagram showing an example of the configuration of the framing code detector. 1... Clock generator, 2... Delay line with tap, 3
... Phase selector, 5... Framing code determination section, 6... Control section, 7... Color subcarrier, 8...
Clock signal, 9...Delayed clock signal, 10...
Selected clock signal, 11...Character information signal, 12...
・Framing code detection pulse, 13... Phase selection signal, 14°30... Flip-flop, 15...
Framing code - code detector, 16... detection start determiner, 17... detection end determiner, 18...
Clock phase calculator, 19...judgment start pulse, 20
...Detection start phase address, 21...Detection end phase address, 22...Sample clock, 23...Detection end signal, 24...Detection start signal, 25...Framing code detection gate pulse, 26...AND gate, 27...OR gate, 28...Binary converter, 29...Register, 31...Subtractor, 32...
-Half reducer, 33... Adder, 34... Framing code match detector, 35... Shift register.
Claims (1)
周波数の多相クロック信号を形成する多相クロック形成
手段と、前記多相クロック信号が有する順次の位相のう
ち、所望の符号化情報信号に含まれる基準クロック位相
の信号成分を検出し得る適応位相の範囲を判別する位相
範囲判別手段と、前記適応位相の範囲の始端および終端
をなす適応限界の位相をそれぞれ抽出する限界位相抽出
手段と、前記始端および終端をなす適応限界の位相相互
間の中央値をなす適正位相を算定する適正位相算定手段
と、前記多相クロック信号から前記適正位相を有する久
ロック信号を選択して前記基準クロック位相に対応した
適正なりロック位相を有する制御出力クロック信号とす
るクロック選択手段とを備えたことを特徴とするクロッ
ク位相制御回路。a multiphase clock forming means for forming multiphase clock signals of predetermined clock frequencies having sequentially different phases with equal phase differences; and a reference included in a desired encoded information signal among the sequential phases of the multiphase clock signals. a phase range determining means for determining an adaptive phase range in which a signal component of a clock phase can be detected; a limit phase extracting means for extracting adaptive limit phases forming a starting point and a terminal end of the adaptive phase range; an appropriate phase calculating means for calculating an appropriate phase that is a median value between the phases of the adaptive limits forming the termination, and selecting a long-lock signal having the appropriate phase from the multiphase clock signal to correspond to the reference clock phase. 1. A clock phase control circuit comprising: clock selection means for selecting a control output clock signal having an appropriate lock phase.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11331482U JPS5920773U (en) | 1982-07-28 | 1982-07-28 | Clock phase control circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11331482U JPS5920773U (en) | 1982-07-28 | 1982-07-28 | Clock phase control circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5920773U true JPS5920773U (en) | 1984-02-08 |
JPS635327Y2 JPS635327Y2 (en) | 1988-02-13 |
Family
ID=30262353
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11331482U Granted JPS5920773U (en) | 1982-07-28 | 1982-07-28 | Clock phase control circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5920773U (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57133782A (en) * | 1981-02-10 | 1982-08-18 | Matsushita Electric Ind Co Ltd | Clock reproducing device |
-
1982
- 1982-07-28 JP JP11331482U patent/JPS5920773U/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57133782A (en) * | 1981-02-10 | 1982-08-18 | Matsushita Electric Ind Co Ltd | Clock reproducing device |
Also Published As
Publication number | Publication date |
---|---|
JPS635327Y2 (en) | 1988-02-13 |
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