JPS6124860U - MFM signal demodulator - Google Patents
MFM signal demodulatorInfo
- Publication number
- JPS6124860U JPS6124860U JP10880284U JP10880284U JPS6124860U JP S6124860 U JPS6124860 U JP S6124860U JP 10880284 U JP10880284 U JP 10880284U JP 10880284 U JP10880284 U JP 10880284U JP S6124860 U JPS6124860 U JP S6124860U
- Authority
- JP
- Japan
- Prior art keywords
- mfm
- signal
- mfm signal
- signal demodulator
- pulses
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
- Dc Digital Transmission (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案による好ましい一具体例の電気回路図、
第２図は第１図に示す具体例のタイムチャートである。
１・・・・・・Ｄタイプフリップフロップ、３・・曲遅
延線、１１・・・・・・ナンドゲート。FIG. 1 is an electrical circuit diagram of a preferred embodiment of the present invention;
FIG. 2 is a time chart of the specific example shown in FIG. 1...D type flip-flop, 3...curved delay line, 11...Nand gate.
Claims (1)
最小周期の１７２１！下のパルス巾を有した一連のパル
スからなるＭＦＭ信号に変換する変換回路と、この変換
回路によって変換されたＭＦＭ信号から、順次最小周期
の１ｎ時間遅延した関係を有する４組のＭＦＭ信号を生
成し、この４組のＭＦＭ信号を重ね合わせて前記最小周
期の１／２の周期を有したクロツク信号を生成する生成
回路と、この生成回路で生成されたクロツク信号によリ
前記ＭＦＭ信号をＮＲＺ信号に復調する復調回路とから
なるＭＦＭ信号復調装置。An MFM signal consisting of a series of pulses has a minimum period of 1721! A conversion circuit converts the MFM signal into an MFM signal consisting of a series of pulses having a pulse width as shown below, and from the MFM signal converted by this conversion circuit, four sets of MFM signals are sequentially delayed by 1n time of the minimum period. Then, there is a generation circuit that superimposes these four sets of MFM signals to generate a clock signal having a cycle that is 1/2 of the minimum cycle, and the clock signal generated by this generation circuit converts the MFM signal into NRZ. An MFM signal demodulation device comprising a demodulation circuit that demodulates the signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10880284U JPS6124860U (en) | 1984-07-18 | 1984-07-18 | MFM signal demodulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10880284U JPS6124860U (en) | 1984-07-18 | 1984-07-18 | MFM signal demodulator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6124860U true JPS6124860U (en) | 1986-02-14 |
Family
ID=30667974
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10880284U Pending JPS6124860U (en) | 1984-07-18 | 1984-07-18 | MFM signal demodulator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6124860U (en) |
-
1984
- 1984-07-18 JP JP10880284U patent/JPS6124860U/en active Pending
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