JPS5918659A - Formation of multilayer wiring - Google Patents
Formation of multilayer wiringInfo
- Publication number
- JPS5918659A JPS5918659A JP12751082A JP12751082A JPS5918659A JP S5918659 A JPS5918659 A JP S5918659A JP 12751082 A JP12751082 A JP 12751082A JP 12751082 A JP12751082 A JP 12751082A JP S5918659 A JPS5918659 A JP S5918659A
- Authority
- JP
- Japan
- Prior art keywords
- film
- wiring
- metal
- alloy
- multilayer wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【発明の詳細な説明】
本発明は多層配線の形成方法に係り、第１層配線と第２
層配線を接続する工程において、接続部に選択性を有す
る金属の化学気相蒸着法を用いた金属で接続する多層配
線の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming multilayer wiring, and includes a method for forming a first layer wiring and a second layer wiring.
The present invention relates to a method for forming a multilayer wiring in which metal is connected using a chemical vapor deposition method of a metal having selectivity at the connection portion in a step of connecting layer wiring.
従来の多層配線は第１図に示すように第１層配線３の金
属上に絶縁膜４を形成し、ホトエツチングによシ接続穴
（スルーホール）をあけた後、第２層配線６の金属を真
空蒸着法やスパッタリング法で形成する。これらの方法
で金属を形成すると第２図に示すように段差部７で金属
膜の膜厚の薄くなる現象、いわゆるステップカバレージ
が悪くなることが知られている。このステップカバレー
ジが悪くても穴の径が大きい場合にはほとんど問題が生
じない。しかし、半導体素子では性能向上のため微細化
が進みスルーホールの径が２μｍφより小さくなる傾向
がある。このようにスルーホール径が小さくなった場合
、ステップカバレージが悪いと第３図に示すように空洞
８が発生して下地と接続しない欠点があった。In the conventional multilayer wiring, as shown in FIG. 1, an insulating film 4 is formed on the metal of the first layer wiring 3, a connection hole (through hole) is made by photo-etching, and then the metal of the second layer wiring 6 is formed. is formed by vacuum evaporation or sputtering. It is known that when metal is formed by these methods, the thickness of the metal film becomes thinner at the stepped portion 7, as shown in FIG. 2, and so-called step coverage deteriorates. Even if this step coverage is poor, it hardly causes any problems if the diameter of the hole is large. However, in order to improve the performance of semiconductor devices, as miniaturization progresses, the diameter of through holes tends to become smaller than 2 μmφ. When the diameter of the through hole is reduced in this manner, there is a drawback that if the step coverage is poor, a cavity 8 is generated as shown in FIG. 3, and the hole 8 is not connected to the base.
本発明の目的は多層配線の形成方法によシて第１層配線
と２層配線を接続する金属を選択性のある化学気相蒸着
法で形成して接続する多層配線の形成方法を提供するも
のである。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a multilayer interconnection in which a metal connecting a first layer interconnection and a second layer interconnection is formed by a selective chemical vapor deposition method. It is something.
半導体素子の多層配線は微細化が進みスルーホールの径
が２μｍφ以下のものが必要となっている。このような
小さなスルーホールで配線を接続する場合、現在用いら
れている真空蒸着法やスパッタリング法で形成した金属
膜は段差部のステップカバレージが悪く、スルーホール
に空洞ができ配線と配線が接続できない。本発明は上記
の問題点を解決するもので、選択性を持つ化学気相蒸着
法ｔ−用いてヌル−ホール部のみに金属を堆積させて下
地配線との接続を完全にした後、第２層配線を形成して
多層配線を形成する方法である。As the multilayer interconnections of semiconductor devices become increasingly finer, through-holes with a diameter of 2 μm or less are required. When connecting wiring through such small through-holes, the currently used metal films formed by vacuum evaporation and sputtering methods have poor step coverage in stepped areas, creating cavities in the through-holes and making it impossible to connect the wiring. . The present invention solves the above-mentioned problems, and uses a selective chemical vapor deposition method to deposit metal only in the null-hole area to complete the connection with the underlying wiring, and then This is a method of forming multilayer wiring by forming layered wiring.
以下、本発明の一実施例を第４図、第５図、第６図によ
り説明する。An embodiment of the present invention will be described below with reference to FIGS. 4, 5, and 6.
素子を形成したシリコン基板１に酸化膜２をｓｏｏｎｍ
形成した後、ホトエツチングにより穴をあけ、スパッタ
リング法により全面に３００Ｃ温度で１μｍのアルミニ
ウムーシリコン合金（シリコンの含有量約１．５％）膜
３を形成してホトエツチングによシ第１層のアルミニウ
ムーシリコン合金の配線を形成する（第４図）。次に、
化学気相蒸着法に、１）４２０Ｃの温度で６００ｎｍの
リンガラス膜４を形成した後、ホトエツチングにより１
．５μｍφのスルーホールをあけ、減圧化学気相蒸着法
によシ水素１ ｓ ｔ／＝、六弗化タングステｙ３ Ｑ
ｃ ｃ ７ｍ１ｔｔ、、基板温度４００Ｃ，堆積圧力
４０Ｐａ％堆積速１ｉ１５ｎｍの条件で第１層配線のア
ルミニウム−７リコン合金３に６ＱＱｎｍのタングステ
ン膜５を形成する。このような堆積条件ではリンガラス
膜４上には堆積せずに、アルミニウムーシリコン合金膜
３上にのみ選択的に堆積する（第５図）。次に、スパッ
タリング法により全面に３００Ｃで２μｍのアルミニウ
ム膜６を形成した後、ホトエツチングにより第２層配線
を形成する（第６図）。An oxide film 2 is soon formed on a silicon substrate 1 on which elements are formed.
After forming, holes are made by photo-etching, and a 1 μm aluminum-silicon alloy (silicon content: approximately 1.5%) film 3 is formed on the entire surface by sputtering at a temperature of 300 C, and the first layer of aluminum is removed by photo-etching. Wiring of mu-silicon alloy is formed (FIG. 4). next,
1) After forming a 600 nm thick phosphor glass film 4 at a temperature of 420 C using a chemical vapor deposition method, 1)
．． A through hole with a diameter of 5 μm is drilled, and hydrogen 1 s t/=, tungsten hexafluoride 3 Q
c c 7mltt, a tungsten film 5 of 6QQnm is formed on the aluminum-7 silicon alloy 3 of the first layer wiring under the conditions of a substrate temperature of 400C, a deposition pressure of 40Pa%, and a deposition rate of 1i15nm. Under such deposition conditions, the film is not deposited on the phosphorus glass film 4, but is selectively deposited only on the aluminum-silicon alloy film 3 (FIG. 5). Next, a 2 μm thick aluminum film 6 is formed at 300 C over the entire surface by sputtering, and then a second layer wiring is formed by photoetching (FIG. 6).
本発明によれば多層配線の形成方法において、配線と配
線を接続するスルーホール径が２μｍ以下の微細なもの
でも接続が完全にでき、断線不良がない微細構造の半導
体素子の多層配線が容易にできる効果がある。According to the present invention, in the method for forming multilayer wiring, even if the diameter of the through hole connecting the wiring is minute, the connection can be made perfectly, and the multilayer wiring of semiconductor elements with a fine structure without disconnection defects can be easily formed. There is an effect that can be achieved.
以上の実施例は配線と配線を接続する金属をタングステ
ンについて説明したが、これ以外の金属、たとえばモリ
ブデン、クンタルおよびこれらの合金についても同様な
取扱いができる。また、下地金属にアルミニウムーシリ
コン合金で説明したが、白金シリサイド、パラジウムシ
リサイド、ニッケルシリサイド、アルミニウムーシリコ
ン−銅合金なとを用いてもよい。In the above embodiments, tungsten was used as the metal for connecting the wirings, but other metals such as molybdenum, Kuntal, and alloys thereof can be treated in the same way. Furthermore, although the explanation has been made using an aluminum-silicon alloy as the base metal, platinum silicide, palladium silicide, nickel silicide, aluminum-silicon-copper alloy, etc. may also be used.
第１図は従来の多層配線の断面図、第２図および第３図
は従来の金属膜の形成状態を示す断面図、第４図〜第６
図は本発明の一実施例を説明する多層配線の断面図であ
る。
ｌ・・・素子を形成したシリコン基板、２・・・酸化膜
、３・・・アルミニウムーシリコン合金膜、４・・・リ
ンガジス膜、５・・・タングステン膜、６・・・アルミ
ニウム膜
χ １ 図
第 ２ 図
爾３図Figure 1 is a cross-sectional view of a conventional multilayer wiring, Figures 2 and 3 are cross-sectional views showing the state of formation of a conventional metal film, and Figures 4 to 6.
The figure is a cross-sectional view of a multilayer interconnection explaining one embodiment of the present invention. 1... Silicon substrate on which an element is formed, 2... Oxide film, 3... Aluminum-silicon alloy film, 4... Ring gas film, 5... Tungsten film, 6... Aluminum film χ 1 Figure 2 Figure 3
Claims (1)
て、選択性を有する金属の化学気相蒸着法を用い、第１
層配線の露出している部分の金属上にのみ選択的に金属
を堆積させて、第２層配線の金属を接続することを特徴
とする多層配線の形成方法。1. In the wiring process for connecting the first layer wiring and the second layer wiring, a selective metal chemical vapor deposition method is used to
A method for forming a multilayer interconnection comprising selectively depositing metal only on exposed metal parts of the layer interconnection to connect the metal of the second layer interconnection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12751082A JPS5918659A (en) | 1982-07-23 | 1982-07-23 | Formation of multilayer wiring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12751082A JPS5918659A (en) | 1982-07-23 | 1982-07-23 | Formation of multilayer wiring |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5918659A true JPS5918659A (en) | 1984-01-31 |
Family
ID=14961778
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12751082A Pending JPS5918659A (en) | 1982-07-23 | 1982-07-23 | Formation of multilayer wiring |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5918659A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01308050A (en) * | 1987-06-01 | 1989-12-12 | General Electric Co <Ge> | Method of forming contact having low resistance with aluminum material and low resistance contact and integrated circuit multilayer structure provided by the method |
| US5110762A (en) * | 1988-07-07 | 1992-05-05 | Kabushiki Kaisha Toshiba | Manufacturing a wiring formed inside a semiconductor device |
| US7114598B2 (en) | 2002-08-28 | 2006-10-03 | Kawasaki Jukogyo Kabushiki Kaisha | Brake cooling mechanism of four-wheeled vehicle |
-
1982
- 1982-07-23 JP JP12751082A patent/JPS5918659A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01308050A (en) * | 1987-06-01 | 1989-12-12 | General Electric Co <Ge> | Method of forming contact having low resistance with aluminum material and low resistance contact and integrated circuit multilayer structure provided by the method |
| US5110762A (en) * | 1988-07-07 | 1992-05-05 | Kabushiki Kaisha Toshiba | Manufacturing a wiring formed inside a semiconductor device |
| US7114598B2 (en) | 2002-08-28 | 2006-10-03 | Kawasaki Jukogyo Kabushiki Kaisha | Brake cooling mechanism of four-wheeled vehicle |
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