JPH0212859A - Formation of multilayer interconnection - Google Patents
Formation of multilayer interconnectionInfo
- Publication number
- JPH0212859A JPH0212859A JP16320988A JP16320988A JPH0212859A JP H0212859 A JPH0212859 A JP H0212859A JP 16320988 A JP16320988 A JP 16320988A JP 16320988 A JP16320988 A JP 16320988A JP H0212859 A JPH0212859 A JP H0212859A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- melting point
- wiring
- aluminum alloy
- high melting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015572 biosynthetic process Effects 0.000 title description 4
- 239000010410 layer Substances 0.000 claims abstract description 73
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 47
- 238000002844 melting Methods 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 22
- 230000008018 melting Effects 0.000 claims abstract description 20
- 239000011229 interlayer Substances 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 8
- 229910052751 metal Inorganic materials 0.000 claims description 45
- 239000002184 metal Substances 0.000 claims description 45
- 150000002736 metal compounds Chemical class 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 7
- 239000003870 refractory metal Substances 0.000 claims description 7
- 238000004544 sputter deposition Methods 0.000 abstract description 15
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 abstract description 12
- 229910052786 argon Inorganic materials 0.000 abstract description 6
- 229910000765 intermetallic Inorganic materials 0.000 abstract 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 18
- 229910052814 silicon oxide Inorganic materials 0.000 description 18
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 7
- 238000001459 lithography Methods 0.000 description 7
- 239000000758 substrate Substances 0.000 description 7
- 229910021341 titanium silicide Inorganic materials 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 2
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 description 2
- 238000004026 adhesive bonding Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は多層配線の形成方法に関し、特にアルミニウム
合金と高融点金属或いは高融点金属化合物とを積層した
構成の金属配線からなる多層配線の形成方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for forming multilayer wiring, and particularly to the formation of multilayer wiring consisting of metal wiring in which an aluminum alloy and a refractory metal or a refractory metal compound are laminated. Regarding the method.
従来、半導体集積回路における金属配線層としてアルミ
ニウム合金が主に用いられているが、このアルミニウム
合金では、耐エレクトロマイグレーション性や、熱処理
により発生されるアルミニウム合金の突起物、いわゆる
ヒロック等が問題とされている。このため、アルミニウ
ム合金を高融点金属或いは高融点金属化合物に積層積層
させた金属配線構造とすることで、この問題点を解決す
ることが行われており、特に形成が容易で効果が大きい
方法として、アルミニウム合金層の上層に高融点金属層
或いは高融点金属化合物層を被着した２層構造の金属配
線が多用されている。Conventionally, aluminum alloys have been mainly used as metal wiring layers in semiconductor integrated circuits, but this aluminum alloy has problems with electromigration resistance and protrusions of the aluminum alloy, so-called hillocks, that occur during heat treatment. ing. Therefore, this problem has been solved by creating a metal wiring structure in which aluminum alloy is laminated on a high-melting point metal or a high-melting point metal compound, and this method is particularly easy to form and highly effective. , metal wiring having a two-layer structure in which a refractory metal layer or a refractory metal compound layer is deposited on top of an aluminum alloy layer is often used.
このような２層の金属配線による多層配線の形成方法の
一例を、第３図（ａ）乃至第３図（ｃ）に示す断面図で
説明する。なお、この例ではアルミニウム合金上にチタ
ンシリサイドを積層した２層配線の例を示している。An example of a method for forming a multilayer wiring using two layers of metal wiring will be described with reference to cross-sectional views shown in FIGS. 3(a) to 3(c). Note that this example shows an example of a two-layer wiring in which titanium silicide is laminated on an aluminum alloy.
先ず、第３図（ａ）のように、表面がシリコン酸化膜２
２で覆われ、所定の位置に開口部を設けたシリコン基板
２１上にアルミニウム合金２３とチタンシリサイド２４
を順次被着した後、通常のりソグラフィ技術を用いて所
要のパターンに形成し、１層目金属配線を形成する。First, as shown in FIG. 3(a), the surface is covered with a silicon oxide film 2.
Aluminum alloy 23 and titanium silicide 24 are placed on a silicon substrate 21 covered with 2 and provided with openings at predetermined positions.
After sequentially depositing the layers, a desired pattern is formed using ordinary lithography technology to form the first layer metal wiring.
次に、第３図（ｂ）のように、ＣＶＤ法を用いて全面に
シリコン酸化膜２５を形成した後、このシリコン酸化膜
２５に１層目金属配線に達する開口部をリソグラフィ技
術を用いて形成する。Next, as shown in FIG. 3(b), after forming a silicon oxide film 25 on the entire surface using the CVD method, an opening reaching the first layer metal wiring is formed in this silicon oxide film 25 using lithography technology. Form.
更に、第３図（ｃ）のように、前記開口部を含むシリコ
ン酸化膜２５上にアルミニウム合金２６を被着した後、
これをリソグラフィ技術を用いて所要パターンに形成し
、２層目金属配線を形成する。Furthermore, as shown in FIG. 3(c), after depositing an aluminum alloy 26 on the silicon oxide film 25 including the opening,
This is formed into a required pattern using lithography technology to form a second layer metal wiring.
上述した従来の形成方法で形成される多層配線は、１層
目のアルミニウム合金２３と２層目のアルミニウム合金
２６とは、チタンシリサイド２４を介在させて接続され
ることになる。通常、このチタンシリサイド等のような
高融点金属や高融点金属化合物はアルミニウム合金に比
較して抵抗が大きいため、１層目と２層目の各アルミニ
ウム合金間の接続抵抗が、このチタンシリサイド２４に
よって増大されるという問題が生じる。In the multilayer wiring formed by the conventional formation method described above, the first layer of aluminum alloy 23 and the second layer of aluminum alloy 26 are connected with titanium silicide 24 interposed therebetween. Normally, high-melting point metals and high-melting point metal compounds such as titanium silicide have higher resistance than aluminum alloys, so the connection resistance between each aluminum alloy in the first and second layers is the titanium silicide 24. The problem arises that it is increased by
また、１層目と２層目の金属配線を相互に絶縁している
シリコン酸化膜２５に開口部を設ける際、微細化のため
にドライエツチングが用いられているが、シリコン酸化
膜の場合は等方性エツチングが困難なため、異方性エツ
チングが用いられる。Furthermore, when forming an opening in the silicon oxide film 25 that insulates the first and second layer metal wiring from each other, dry etching is used for miniaturization, but in the case of a silicon oxide film, Since isotropic etching is difficult, anisotropic etching is used.
このため、図示のように開口部の断面は象、峻な形状と
なり２層目金属配線が開口部で断線しやすくなるという
問題も有している。For this reason, as shown in the figure, the cross section of the opening has a steep shape, and there is also the problem that the second layer metal wiring is likely to be disconnected at the opening.
本発明は１層目と２層目の金属配線の接続抵抗を低減し
、かつ２層目配線の断線を防止した多層配線を容易に得
ることが可能な多層配線の形成方法を提供することを目
的としている。It is an object of the present invention to provide a method for forming a multilayer wiring that can easily obtain a multilayer wiring that reduces the connection resistance between the first and second layer metal wiring and prevents disconnection of the second layer wiring. The purpose is
（課題を解決するための手段〕
本発明の多層配線の形成方法は、アルミニウム合金上に
高融点金属層或いは高融点金属化合物層を形成して積層
構造の１層目金属配線を形成する工程と、この１層目金
属配線上に層間絶縁膜を形成する工程と、この層間絶縁
膜に前記１層目の金属配線の一部を露呈させる開口部を
異方性エツチング法により選択的に形成する工程と、ア
ルゴンを用いた逆スパッタ法により前記開口部に露呈さ
れる高融点金属層或いは高融点金属化合物層を除去する
工程と、前記層間絶縁膜上にアルミニウム合金を堆積し
、開口部を通して前記１層目の金属配線のアルミニウム
合金に直接接続させる２層目の金属配線を形成する工程
とを含んでいる。(Means for Solving the Problems) The method for forming a multilayer wiring according to the present invention includes the steps of forming a high melting point metal layer or a high melting point metal compound layer on an aluminum alloy to form a first layer metal wiring in a laminated structure. , a step of forming an interlayer insulating film on this first layer metal wiring, and selectively forming an opening in this interlayer insulating film to expose a part of the first layer metal wiring by an anisotropic etching method. step, removing the refractory metal layer or refractory metal compound layer exposed in the opening by reverse sputtering using argon, depositing an aluminum alloy on the interlayer insulating film, and depositing the aluminum alloy on the interlayer insulating film, The method includes a step of forming a second layer of metal wiring to be directly connected to the aluminum alloy of the first layer of metal wiring.
上述した形成方法では、逆スパッタ法により開口部内の
高融点金属層或いは高融点金属化合物層が除去され、Ｉ
Ｎ目の金属配線と２層目の金属配線の各アルミニウム合
金が直接接続され、両者間での接続抵抗を低減する。ま
た、逆スパッタ法により、層間絶縁膜の段部が傾斜状態
でエツチングされ、段部の段差を緩和して２Ｎ目金属配
線の断線を防止する。In the above-described formation method, the high melting point metal layer or high melting point metal compound layer within the opening is removed by reverse sputtering, and the I
The aluminum alloys of the N-th metal wiring and the second-layer metal wiring are directly connected to reduce the connection resistance between them. Further, by the reverse sputtering method, the stepped portion of the interlayer insulating film is etched in an inclined state, and the difference in level of the stepped portion is alleviated to prevent disconnection of the 2Nth metal wiring.
次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）乃至第１図（ｄ）は本発明の第１実施例の
主要工程を工程順に示す断面図である。FIGS. 1(a) to 1(d) are cross-sectional views showing the main steps of the first embodiment of the present invention in order of process.
先ず、第１図（ａ）のように、表面がシリコン酸化膜２
で覆われ所定の位置に開口部を設けたシリコン基板１上
にアルミニウム合金３を０．５μｍ、窒化チタン４を０
．１μｍの厚さに順次スパッタリング法により被着した
後、通常のりソグラフィ技術を用いて所要パターンに形
成し、１層目金属配線を形成する。First, as shown in FIG. 1(a), the surface is covered with a silicon oxide film 2.
0.5 μm of aluminum alloy 3 and 0.5 μm of titanium nitride 4 on a silicon substrate 1 covered with
．． After sequentially depositing the film to a thickness of 1 μm by sputtering, it is formed into a desired pattern using normal gluing lithography to form the first layer metal wiring.
次に、第１図（ｂ）のように、プラズマＣＶＤ法により
形成したシリコン酸化膜、つまりプラズマシリコン酸化
膜５を全面に１．０μｍの厚さに被着した後、このプラ
ズマシリコン酸化膜５に前記１層目金属配線に達する開
口部をリソグラフィ技術及び異方性のドライエツチング
技術を用いて形成する。Next, as shown in FIG. 1(b), a silicon oxide film formed by plasma CVD, that is, a plasma silicon oxide film 5, is deposited on the entire surface to a thickness of 1.0 μm. Then, an opening reaching the first layer metal wiring is formed using lithography technology and anisotropic dry etching technology.
次に、第１図（Ｃ）のように、アルゴンガスを真空中に
導入し、かつシリコン基板に高周波電圧を印加してアル
ゴンの高周波プラズマを発生させ、このプラズマにより
エツチングする方法、換言すればアルゴンを用いた逆ス
パッタ法により開口部内に露呈されている窒化チタン４
を除去する。このとき、プラズマシリコン酸化膜５も０
．２〜０．３μｍ程度エツチングされ、特に開口縁５ａ
或いは１層目金属配線の段部のエツチング速度は大きく
、これらの部分では基板に対して４０〜５０６の傾斜を
持つ断面形状となる。Next, as shown in FIG. 1(C), argon gas is introduced into a vacuum and a high frequency voltage is applied to the silicon substrate to generate high frequency plasma of argon, and etching is performed using this plasma. Titanium nitride 4 exposed in the opening by reverse sputtering using argon
remove. At this time, the plasma silicon oxide film 5 is also zero.
．． It is etched by about 2 to 0.3 μm, especially the opening edge 5a.
Alternatively, the etching rate of the stepped portions of the first layer metal wiring is high, and these portions have a cross-sectional shape having an inclination of 40 to 506 degrees with respect to the substrate.
しかる上で、第１図（ｄ）のように、プラズマシリコン
酸化膜５上にアルミニウム合金６と窒化チタン７を順次
スパッタリング法により被着した後、これをリソグラフ
ィ技術を用いて所要パターンに形成し、開口部において
前記１層目金属配線に接続される２Ｎ目金属配線を形成
する。Then, as shown in FIG. 1(d), aluminum alloy 6 and titanium nitride 7 are sequentially deposited on plasma silicon oxide film 5 by sputtering, and then formed into a desired pattern using lithography. , forming a 2Nth metal wiring connected to the first layer metal wiring in the opening.
このようにして形成された多層配線は、１層目のアルミ
ニウム合金３上の窒化チタン４を開口部において逆スパ
ッタ法により除去しているので、１層目のアルミニウム
合金３と２Ｎ目のアルミニウム合金６の間に窒化チタン
４が存在することはなく、両アルミニウム合金３．６の
接続抵抗を十分低いものにできる。また、プラズマシリ
コン酸化膜５は、逆スパッタ法によりエツチングされる
ので、開口部の開口縁５ａは基板に対して５０°程度の
傾斜となり、開口部における２Ｎ目のアルミニウム合金
６の被覆性は良好となり、断線を防止できる。In the multilayer wiring formed in this way, since the titanium nitride 4 on the first layer aluminum alloy 3 is removed by reverse sputtering at the opening, the first layer aluminum alloy 3 and the 2N-th aluminum alloy Since titanium nitride 4 does not exist between aluminum alloys 3 and 6, the connection resistance between both aluminum alloys 3 and 6 can be made sufficiently low. Furthermore, since the plasma silicon oxide film 5 is etched by reverse sputtering, the opening edge 5a of the opening is inclined at an angle of about 50° with respect to the substrate, and the coverage of the 2N-th aluminum alloy 6 in the opening is good. This prevents wire breakage.
これにより、アルミニウム合金と窒化チタンの２層構造
で耐エレクトロマイグレーション性や耐ヒロック性を向
上するとともに、低抵抗化を図り、かつ開口部や段部で
の断線を防止した高信頼度の多層配線を得ることができ
る。As a result, the two-layer structure of aluminum alloy and titanium nitride improves electromigration resistance and hillock resistance, while also achieving low resistance and highly reliable multilayer wiring that prevents disconnection at openings and steps. can be obtained.
第２図（ａ）乃至第２図（ｅ）は本発明の第２実施例の
主要工程を工程順に示す断面図である。FIGS. 2(a) to 2(e) are cross-sectional views showing the main steps of the second embodiment of the present invention in order of process.
先ず、第２図（ａ）のように、表面がシリコン酸化膜１
２で覆われ所定の位置に開口部を設けたシリコン基板１
１上にアルミニウム合金１３を堆積し、かつこれをリソ
グラフィ技術で所要のパターンに形成し、１層目金属配
線を形成する。First, as shown in FIG. 2(a), the surface is covered with a silicon oxide film 1.
A silicon substrate 1 covered with 2 and having an opening at a predetermined position.
An aluminum alloy 13 is deposited on top of the aluminum alloy 13 and formed into a desired pattern using lithography technology to form a first layer metal wiring.
次に、第２図（ｂ）のように、六弗化タングステンを用
いたＣＶＤ法によりアルミニウム合金配線１３の表面に
選択的にタングステン１４を０．１μｍ被着する。Next, as shown in FIG. 2(b), tungsten 14 is selectively deposited to a thickness of 0.1 μm on the surface of the aluminum alloy wiring 13 by CVD using tungsten hexafluoride.
その後の工程は第１実施例と同様であり、第２図（Ｃ）
のように、全面にプラズマシリコン酸化膜１５を被着し
た後、異方性ドライエツチングにより開口部を形成する
。The subsequent steps are the same as those in the first embodiment, and are shown in FIG. 2(C).
After a plasma silicon oxide film 15 is deposited on the entire surface, openings are formed by anisotropic dry etching.
更に、第２図（ｄ）のようにアルゴンを用いた逆スパッ
タリングにより、開口部内のタングステン１４を除去す
ると同時にプラズマシリコン酸化膜１５を０．２〜０．
３μｍエツチングし、開口部の開口縁１５ａが傾斜を持
った断面形状とする。Furthermore, as shown in FIG. 2(d), by reverse sputtering using argon, the tungsten 14 in the opening is removed and at the same time the plasma silicon oxide film 15 is sputtered by 0.2 to 0.2 mm.
Etching is performed by 3 μm, and the opening edge 15a of the opening has a sloped cross-sectional shape.
その後、第２図（ｅ）のように、アルミニウム合金１６
を全面に堆積し、これを所要パターンに形成することに
より２層目金属配線を形成する。After that, as shown in FIG. 2(e), the aluminum alloy 16
A second layer of metal wiring is formed by depositing this on the entire surface and forming it into a desired pattern.
この第２実施例においても、形成された多層配線は、１
Ｎ目のアルミニウム合金１３上の六弗化タングステン１
４を開口部において逆スパッタ法により除去しているの
で、１層目のアルミニウム合金１３と２層目のアルミニ
ウム合金１６を直接接続させてその接続抵抗を十分低い
ものにできる。In this second embodiment as well, the formed multilayer wiring has 1
Tungsten hexafluoride 1 on N-th aluminum alloy 13
4 is removed at the opening by reverse sputtering, the first layer of aluminum alloy 13 and the second layer of aluminum alloy 16 can be directly connected and the connection resistance can be made sufficiently low.
また、プラズマシリコン酸化膜１５の開口部の開口縁を
傾斜させ、開口部における２層目のアルミニウム合金１
６の被覆性は良好となり、断線を防止できる。In addition, the opening edge of the opening of the plasma silicon oxide film 15 is inclined, and the second layer of aluminum alloy 1 in the opening is
The coverage of No. 6 is good, and disconnection can be prevented.
なお、上述した以外の高融点金属や高融点化合物を用い
た金属配線においても本発明を同様に適用することがで
きる。Note that the present invention can be similarly applied to metal wiring using high-melting point metals and high-melting point compounds other than those described above.
以上説明したように本発明は、層間絶縁膜に開口部を開
設した後に、逆スパッタ法により開口部内の高融点金属
層或いは高融点金属化合物層を除去しているので、１層
目の金属配線と２層目の金属配線の各アルミニウム合金
が直接接続され、両者間での接続抵抗を低減することが
できる。また、この際の逆スパッタ法により層間絶縁膜
の段部が傾斜状態でエツチングされて段部の段差を緩和
するので、この上に形成する２層目金属配線の断線を防
止することができる。これにより、本発明方法で形成さ
れる多層配線は、アルミニウム合金に高融点金属層や高
融点金属化合物層を重ねた構成とすることにより耐エレ
クトロマイグレーション性や耐ヒロック性を向上する一
方で、低抵抗化しかつ開口部や段部での断線を無くした
高信頼性の微細多層配線を形成することができる効果が
ある。As explained above, in the present invention, after an opening is formed in an interlayer insulating film, the high melting point metal layer or high melting point metal compound layer inside the opening is removed by reverse sputtering, so that the first layer of metal wiring is removed. and each aluminum alloy of the second layer metal wiring are directly connected, and connection resistance between the two can be reduced. Furthermore, by the reverse sputtering method at this time, the stepped portion of the interlayer insulating film is etched in an inclined manner, thereby reducing the level difference in the stepped portion, so that disconnection of the second layer metal wiring formed thereon can be prevented. As a result, the multilayer wiring formed by the method of the present invention has a structure in which a high melting point metal layer or a high melting point metal compound layer is stacked on an aluminum alloy, which improves electromigration resistance and hillock resistance, while reducing This has the effect of forming highly reliable fine multilayer wiring that is resistive and free from disconnections at openings and step portions.
第１図（ａ）乃至第１図（ｄ）は本発明の第１実施例を
工程順に示す断面図、第２図（ａ）乃至第２図（ｅ）は
本発明の第２実施例を工程順に示す断面図、第３図（ａ
）乃至第３図（Ｃ）は従来の形成方法を工程順に示す断
面図である。
１．１１．２１・・・シリコン基板、２，１２．２２・
・・シリコン酸化膜、３，１３．２３・・・アルミニウ
ム合金（１層目）、４．７・・・窒化チタン（高融点金
属化合物）、１４・・・タングステン（高融点金属）２
４・・・チタンシリサイド（高融点金属化合物）、５．
１５．２５・・・プラズマシリコン酸化膜、６゜１６．
２６・・・アルミニウム合金（２層目）。
第２
図
第
図FIGS. 1(a) to 1(d) are sectional views showing the first embodiment of the present invention in the order of steps, and FIGS. 2(a) to 2(e) are sectional views showing the second embodiment of the present invention. Cross-sectional diagrams shown in the order of steps, Figure 3 (a
) to FIG. 3(C) are cross-sectional views showing the conventional forming method in the order of steps. 1.11.21...Silicon substrate, 2,12.22.
... Silicon oxide film, 3, 13.23 ... Aluminum alloy (first layer), 4.7 ... Titanium nitride (high melting point metal compound), 14 ... Tungsten (high melting point metal) 2
4...Titanium silicide (high melting point metal compound), 5.
15.25...Plasma silicon oxide film, 6°16.
26...Aluminum alloy (second layer). Figure 2
Claims (1)
属化合物層を形成して積層構造の１層目金属配線を形成
する工程と、この１層目金属配線上に層間絶縁膜を形成
する工程と、この層間絶縁膜に前記１層目の金属配線の
一部を露呈させる開口部を異方性エッチング法により選
択的に形成する工程と、アルゴンを用いた逆スパッタ法
により前記開口部に露呈される高融点金属層或いは高融
点金属化合物層を除去する工程と、前記層間絶縁膜上に
アルミニウム合金を堆積し、開口部を通して前記１層目
の金属配線のアルミニウム合金に直接接続させる２層目
の金属配線を形成する工程とを含むことを特徴とする多
層配線の形成方法。1. A step of forming a high melting point metal layer or a refractory metal compound layer on an aluminum alloy to form a first layer metal wiring of a laminated structure, and a step of forming an interlayer insulating film on this first layer metal wiring. , a step of selectively forming an opening in this interlayer insulating film to expose a part of the first layer metal wiring by an anisotropic etching method; a step of removing a high melting point metal layer or a high melting point metal compound layer; and a step of depositing an aluminum alloy on the interlayer insulating film and directly connecting the aluminum alloy of the first layer metal wiring through the opening. 1. A method for forming a multilayer wiring, the method comprising the step of forming a metal wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16320988A JPH0212859A (en) | 1988-06-30 | 1988-06-30 | Formation of multilayer interconnection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16320988A JPH0212859A (en) | 1988-06-30 | 1988-06-30 | Formation of multilayer interconnection |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0212859A true JPH0212859A (en) | 1990-01-17 |
Family
ID=15769365
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16320988A Pending JPH0212859A (en) | 1988-06-30 | 1988-06-30 | Formation of multilayer interconnection |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0212859A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5084404A (en) * | 1988-03-31 | 1992-01-28 | Advanced Micro Devices | Gate array structure and process to allow optioning at second metal mask only |
| US5162261A (en) * | 1990-12-05 | 1992-11-10 | Texas Instruments Incorporated | Method of forming a via having sloped sidewalls |
| US5313100A (en) * | 1991-04-26 | 1994-05-17 | Mitsubishi Denki Kabushiki Kaisha | Multilayer interconnection structure for a semiconductor device |
| US5627345A (en) * | 1991-10-24 | 1997-05-06 | Kawasaki Steel Corporation | Multilevel interconnect structure |
| JP2006135359A (en) * | 1998-12-18 | 2006-05-25 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
| US7312515B2 (en) | 2003-06-11 | 2007-12-25 | Ricoh Company, Ltd. | Semiconductor apparatus including a thin-metal-film resistor element and a method of manufacturing the same |
| US7358592B2 (en) | 2004-03-02 | 2008-04-15 | Ricoh Company, Ltd. | Semiconductor device |
| JP2008147233A (en) * | 2006-12-06 | 2008-06-26 | Seiko Epson Corp | Manufacturing method of actuator device and liquid jetting head |
| US7420211B2 (en) | 1998-12-18 | 2008-09-02 | Semiconductor Energy Laboratory Co., Ltd. | Wiring line and manufacture process thereof, and semiconductor device and manufacturing process thereof |
-
1988
- 1988-06-30 JP JP16320988A patent/JPH0212859A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5084404A (en) * | 1988-03-31 | 1992-01-28 | Advanced Micro Devices | Gate array structure and process to allow optioning at second metal mask only |
| US5162261A (en) * | 1990-12-05 | 1992-11-10 | Texas Instruments Incorporated | Method of forming a via having sloped sidewalls |
| US5712140A (en) * | 1991-04-19 | 1998-01-27 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing interconnection structure of a semiconductor device |
| US5313100A (en) * | 1991-04-26 | 1994-05-17 | Mitsubishi Denki Kabushiki Kaisha | Multilayer interconnection structure for a semiconductor device |
| US5475267A (en) * | 1991-04-26 | 1995-12-12 | Mitsubishi Denki Kabushiki Kaisha | Multilayer interconnection structure for a semiconductor device |
| US5946799A (en) * | 1991-10-24 | 1999-09-07 | Kawasaki Steel Corporation | Multilevel interconnect method of manufacturing |
| US5627345A (en) * | 1991-10-24 | 1997-05-06 | Kawasaki Steel Corporation | Multilevel interconnect structure |
| JP2006135359A (en) * | 1998-12-18 | 2006-05-25 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
| US7420211B2 (en) | 1998-12-18 | 2008-09-02 | Semiconductor Energy Laboratory Co., Ltd. | Wiring line and manufacture process thereof, and semiconductor device and manufacturing process thereof |
| US7312515B2 (en) | 2003-06-11 | 2007-12-25 | Ricoh Company, Ltd. | Semiconductor apparatus including a thin-metal-film resistor element and a method of manufacturing the same |
| US7718502B2 (en) | 2003-06-11 | 2010-05-18 | Ricoh Company, Ltd. | Semiconductor apparatus including a thin-metal-film resistor element and a method of manufacturing the same |
| US7358592B2 (en) | 2004-03-02 | 2008-04-15 | Ricoh Company, Ltd. | Semiconductor device |
| JP2008147233A (en) * | 2006-12-06 | 2008-06-26 | Seiko Epson Corp | Manufacturing method of actuator device and liquid jetting head |
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