JPS5918629A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5918629A
JPS5918629A JP57129474A JP12947482A JPS5918629A JP S5918629 A JPS5918629 A JP S5918629A JP 57129474 A JP57129474 A JP 57129474A JP 12947482 A JP12947482 A JP 12947482A JP S5918629 A JPS5918629 A JP S5918629A
Authority
JP
Japan
Prior art keywords
island
layer
periphery
polycrystalline
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57129474A
Other languages
Japanese (ja)
Inventor
Kazuyuki Sugahara
和之 須賀原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP57129474A priority Critical patent/JPS5918629A/en
Publication of JPS5918629A publication Critical patent/JPS5918629A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/0242—Crystalline insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To obtain a device providing a less leak current by removing the peripheral part after crystallization or changing its nature by oxidation on the occasion of obtaining a semiconductor substrate through formation of polycrystalline or amorphous semiconductor layers like islands surrounded by insulating material on an insulator and through crystallization after it is melted by local heating. CONSTITUTION:A polycrystalline or amorphous recrystallized Si layer 2 is formed like an island on a quartz substrate while it is surrounded by an oxide film 5 consisting of a polycrystalline Si oxide and photo resist film 6 is applied to the area located inside from the periphery of island by the width of 2um. With such resist film 6 used as the mask, the periphery of layer 2 is removed with the width of 2um by the etching. Thereafter, elements such as transistor are formed within the remaining layer 2. Here, the periphery is removed by the etching but it may be removed after it is changed in nature by oxidation by the selective oxidation method. As described above, the periphery wherein fine crystal particles are still remaining is perfectly removed.

Description

【発明の詳細な説明】 この発明は半導体装置の製造方法、特に絶縁体ｔに半導
体結晶層を形成する方法に関するものでそる。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming a semiconductor crystal layer on an insulator t.

動するものとして、透明基板ｔにトランジスタを形成す
る試みがなされており、そのため絶縁物。Attempts have been made to form a transistor on a transparent substrate t, which requires an insulator.

たとえば石英基板ｔに半導体の単結晶層または大結晶粒
の結晶層を形成する方法が考えられている。For example, a method of forming a semiconductor single crystal layer or a large crystal grain crystal layer on a quartz substrate t has been considered.

この方法として１石英基板上に多結晶または非晶質の半
導体を堆積し、その表面にレーザー光、電子線などのエ
ネルギー線を照射することにより表面層のみを加熱し、
半導体の単結晶層または大結晶粒の結晶層を形成する方
法がある。In this method, a polycrystalline or amorphous semiconductor is deposited on a quartz substrate, and only the surface layer is heated by irradiating the surface with an energy beam such as a laser beam or an electron beam.
There is a method of forming a semiconductor single crystal layer or a large crystal grain crystal layer.

従来の半導体装置の製造方法の一例を工程順に示す図を
もとに説明する。第１図（ａ）においで、（１）は基板
となるべき石英基板（８ｉ０．　）である。この基板（
１）　Ｌに＠１図（ｂ）に示すように減圧０ＶＩＪ法で
ポリシリコン層（２）を７００ＯＡ堆積する。次に第１
図（Ｃ）に示すように９５０″Ｃで酸化して酸化膜（３
）を形成した後、減圧０ＶＩ）法による窒化膜（４）を
堆積し、写真製版による窒化膜（４）のパター冊ングを
行なう、さらに９５０″Ｃ酸化雰囲気に長時間さらした
後、パターニングされた窒化膜（４）及び酸化膜（３）
を除去するたは非晶質の半導体、この場合はポリシリコ
ン。An example of a conventional method for manufacturing a semiconductor device will be described with reference to figures showing the order of steps. In FIG. 1(a), (1) is a quartz substrate (8i0.) which is to be a substrate. This board (
1) As shown in Figure 1 (b), a polysilicon layer (2) of 700 OA is deposited on L using the reduced pressure 0 VIJ method. Then the first
As shown in Figure (C), the oxide film (3
) is formed, a nitride film (4) is deposited by a reduced pressure 0VI) method, and the nitride film (4) is patterned by photolithography. Nitride film (4) and oxide film (3)
or removing an amorphous semiconductor, in this case polysilicon.

が形成されでいる。（５）は酸化されたポリシリコン層
である。第１図（ｅ）は第１図（ｄ）の平面図を示す。has been formed. (5) is an oxidized polysilicon layer. FIG. 1(e) shows a plan view of FIG. 1(d).

次に＠１図（ｅ）の島状のポリシリコン層（２）に、短
辺の１倍から２倍程度のスポットに絞ったレーザー光を
パターンの長手方向に走査しながら照射する。Next, the island-shaped polysilicon layer (2) shown in Figure 1 (e) is irradiated with a laser beam focused on a spot about 1 to 2 times the width of the short side while scanning in the longitudinal direction of the pattern.

この時、ポリシリコン層（２）は溶融し、照射後固化す
ると同時にポリシリコン層の結晶粒は増大するかまたは
単結晶化する。さらにこの単結晶または結晶粒が大きく
なったポリシリコンの再結晶層に。At this time, the polysilicon layer (2) is melted and solidified after irradiation, and at the same time the crystal grains of the polysilicon layer increase or become monocrystalline. Furthermore, this monocrystalline or polysilicon recrystallized layer with enlarged crystal grains.

ＭＯＳ　）ランジスタを公知のプロセスで形成するつと
ころが従来の方法において、下地が絶縁物。In the conventional method, a transistor (MOS) is formed using a known process, but the base is an insulator.

たとえば石英基板（１）であるため、絶縁体で囲まれた
島状半導体層（２）の周辺部の温度がレーザー光照射時
にＬがらず、溶融を起こさないので９周辺部の半導体層
は（周辺から幅約２μｍにわたって）細かい結晶粒のま
まで残ってしまう。したがってこの半導体層にＭＯＳ　
）ランジスタなどの素子を形成する場合にリーク電流が
多いなど、螺気的特性が悪いという欠点があった。For example, since it is a quartz substrate (1), the temperature of the peripheral part of the island-shaped semiconductor layer (2) surrounded by an insulator does not decrease when irradiated with laser light and does not cause melting, so the semiconductor layer in the peripheral part (9) is ( Fine crystal grains (over a width of about 2 μm from the periphery) remain as they are. Therefore, this semiconductor layer has MOS
) When forming elements such as transistors, there were drawbacks such as poor spiral characteristics, such as a large amount of leakage current.

この発明はＬ記のような従来のものの欠点を除去するた
めになされたもので、島状半導体層の周辺部を除去する
ことによって電気特性の良好な素子を形成することを可
能にする半導体装置の製造方法を提供することを目的と
している。This invention was made in order to eliminate the drawbacks of the conventional devices as described in L, and is a semiconductor device that makes it possible to form an element with good electrical characteristics by removing the peripheral part of an island-shaped semiconductor layer. The purpose is to provide a manufacturing method for.

以丁、この発明の一実施例を図をもとに説明するっ従来
と同じ方法で５石英基板ｔに島状再結晶シリコン層（２
）を形成した後、第２図（ａ）に示すように再結晶シリ
コン層（２）　Ｊ：、に島の周辺より幅２μｍずつ内側
に、レジスト（６）を塗布し、島状再結晶シリコノ層（
２）の周辺部をエツチングする５次に第２図（ｂ）に示
すようにレジスト（６）を取り除くと、島状再結晶シリ
コノ層（２〕の周辺部が除去された半導体装置を得る。Hereinafter, one embodiment of the present invention will be explained based on the drawings. An island-like recrystallized silicon layer (2
), as shown in FIG. 2(a), a resist (6) is applied to the recrystallized silicon layer (2) J:, 2 μm in width from the periphery of the island, forming an island-shaped recrystallized silicon layer. layer(
2) Etching the peripheral portion of the resist (6) Next, as shown in FIG. 2(b), the resist (6) is removed to obtain a semiconductor device in which the peripheral portion of the island-shaped recrystallized silicon layer (2) has been removed.

しかるのちＬ記の島状再結晶シリコレ層（２）の中にト
ランジスタなどの素子を作成する。Thereafter, elements such as transistors are formed in the island-shaped recrystallized silicone layer (2) of letter L.

第２図（Ｃ）は＠２図（ａ）の平面図および第２図（ｄ
）は第２図（ｂ）の平面図を示す。Figure 2 (C) is the plan view of Figure 2 (a) and Figure 2 (d).
) shows a plan view of FIG. 2(b).

なお９．ｌ：記実施例では島状半導体層（２）の周辺部
をエツチングによって除去したが１選択酸化法によって
禍状半導体層（２）の周辺部を酸化し変質させ除去して
も同様の効果を得ることができる。すなわち第８図にお
いて（７）はレーザー光照射後の島状半導体ｍ　（２）
に、島の周辺より幅２Ｉｔｍ内側に堆積した窒化膜を示
す。この窒化膜（７）堆積後、　９５０”Ｃの酸化雰囲
気中に長時間さらして島の周辺部を酸化し、窒化膜（７
）を除去した後の断面図を第８図（ｂ）に示す。第８図
（Ｃ）は第８図（ａ）の平面図および第８図（ｄ）は第
８図（ｂ）の平面図でゐろ。Note 9. l: In the above embodiment, the peripheral part of the island-shaped semiconductor layer (2) was removed by etching, but the same effect can be obtained even if the peripheral part of the insular semiconductor layer (2) is oxidized, altered, and removed by one-selective oxidation method. Obtainable. That is, in FIG. 8, (7) is the island-shaped semiconductor m (2) after laser beam irradiation.
2 shows a nitride film deposited 2 Itm in width from the periphery of the island. After depositing this nitride film (7), the surrounding area of the island is oxidized by exposing it to an oxidizing atmosphere of 950"C for a long time, and the nitride film (7) is deposited.
) is shown in FIG. 8(b). FIG. 8(C) is a plan view of FIG. 8(a), and FIG. 8(d) is a plan view of FIG. 8(b).

以ｔのように、この発明によれば島状半導体の再結晶層
の周辺部を除去することにより、リーク縦疵の少ない電
気的特性の良好な回路素子を作成可能な半導体装置の製
造方法が得られる。As described below, according to the present invention, there is provided a method for manufacturing a semiconductor device that can produce a circuit element with less vertical leakage and good electrical characteristics by removing the peripheral portion of the recrystallized layer of an island-shaped semiconductor. can get.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（ａ）〜（ｄ）は従来の島状半導体装置の製造方
法を工程順に示す断面図であり、第１図（ｅ）は第１図
（ｄ）の平面図である。第２図（ａ）、（ｂ）はこの発
明の一実施例でゐろエツチングによるものを工程順に示
す断面図であり、第２図（Ｃ）は第２図（ａ）の平面図
。 第２図（ｄ）は第２図（ｂ）の平面図である。さらに第
８図（ａ）、（ｂ）は他の実施例である選択酸化法によ
るものを工程順に示す断面図であり、第８図（Ｃ）は第
８図（ａ）の平面図、第８図（ｄ）は第８図（ｂ）の平
面図である。 図において（１）は石英基板、（２）はポリシリコン層
。 （５）はポリシリコン層の酸化膜である。 なお１図中、同一符号は同一、又は相当部分を示す。 代　理　人　　葛　　野　　信　　− 第１図 第２図 第３図FIGS. 1(a) to 1(d) are cross-sectional views showing a conventional method for manufacturing an island-shaped semiconductor device in the order of steps, and FIG. 1(e) is a plan view of FIG. 1(d). FIGS. 2(a) and 2(b) are cross-sectional views illustrating an embodiment of the present invention using white etching in the order of steps, and FIG. 2(C) is a plan view of FIG. 2(a). FIG. 2(d) is a plan view of FIG. 2(b). Further, FIGS. 8(a) and 8(b) are cross-sectional views showing the process order of another embodiment using a selective oxidation method, and FIG. 8(C) is a plan view of FIG. 8(a), and FIG. FIG. 8(d) is a plan view of FIG. 8(b). In the figure, (1) is a quartz substrate, and (2) is a polysilicon layer. (5) is an oxide film of the polysilicon layer. In addition, in FIG. 1, the same reference numerals indicate the same or equivalent parts. Agent Shin Kuzuno - Figure 1 Figure 2 Figure 3

Claims (3)

【特許請求の範囲】[Claims] （１）絶縁体りに形成され９周囲を絶縁物によって取り
囲まれた島状の多結晶または非晶質の半導体層を局部加
熱により浴融し結晶化するものにおいて、島状半導体層
の周辺部を除去することを特徴とする半導体装置の製造
方法。(1) In a device in which an island-shaped polycrystalline or amorphous semiconductor layer formed of an insulator and surrounded by an insulator is crystallized by bath melting by local heating, the peripheral area of the island-shaped semiconductor layer 1. A method of manufacturing a semiconductor device, comprising: removing. （２）島状半導体層の周辺部をエツチングにより除去す
る仁とを特徴とする特許請求の範囲第１項記載の半導体
装置の製造方法。(2) A method for manufacturing a semiconductor device according to claim 1, characterized in that the peripheral portion of the island-shaped semiconductor layer is removed by etching. （３）島状半導体Ｊｔ４の周辺部を酸化して変質させろ
ことを特徴とする特許請求の範囲第１項記載の半導体装
置の製造方法。(3) The method for manufacturing a semiconductor device according to claim 1, characterized in that the peripheral portion of the island-shaped semiconductor Jt4 is oxidized and altered in quality.
JP57129474A 1982-07-22 1982-07-22 Manufacture of semiconductor device Pending JPS5918629A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57129474A JPS5918629A (en) 1982-07-22 1982-07-22 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57129474A JPS5918629A (en) 1982-07-22 1982-07-22 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5918629A true JPS5918629A (en) 1984-01-31

Family

ID=15010374

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57129474A Pending JPS5918629A (en) 1982-07-22 1982-07-22 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5918629A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60256764A (en) * 1984-06-01 1985-12-18 株式会社東芝 Cooling device
JPS6277571A (en) * 1985-09-28 1987-04-09 新明和工業株式会社 Refrigerator

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60256764A (en) * 1984-06-01 1985-12-18 株式会社東芝 Cooling device
JPS6277571A (en) * 1985-09-28 1987-04-09 新明和工業株式会社 Refrigerator

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