JPS5814525A - Manufacturing semiconductor device - Google Patents
Manufacturing semiconductor deviceInfo
- Publication number
- JPS5814525A JPS5814525A JP11186781A JP11186781A JPS5814525A JP S5814525 A JPS5814525 A JP S5814525A JP 11186781 A JP11186781 A JP 11186781A JP 11186781 A JP11186781 A JP 11186781A JP S5814525 A JPS5814525 A JP S5814525A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- region
- single crystal
- temperature
- semiconductor region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 239000013078 crystal Substances 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 5
- 239000000835 fiber Substances 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 25
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract description 18
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 12
- 239000000377 silicon dioxide Substances 0.000 abstract description 12
- 238000001953 recrystallisation Methods 0.000 abstract description 9
- 238000002425 crystallisation Methods 0.000 abstract description 7
- 230000008025 crystallization Effects 0.000 abstract description 7
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 4
- 229910052681 coesite Inorganic materials 0.000 abstract 4
- 229910052906 cristobalite Inorganic materials 0.000 abstract 4
- 229910052682 stishovite Inorganic materials 0.000 abstract 4
- 229910052905 tridymite Inorganic materials 0.000 abstract 4
- 230000004927 fusion Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 239000004020 conductor Substances 0.000 description 5
- 239000010410 layer Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000002245 particle Substances 0.000 description 4
- 230000001678 irradiating effect Effects 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- -1 that is Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 210000000744 eyelid Anatomy 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- High Energy & Nuclear Physics (AREA)
- Optics & Photonics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法、特に絶縁基板面上の分
離さｔ１次非単結晶半導体額斌ｔエネ゛ルギ線の照射に
より単結晶化する方法に関す。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of monocrystallizing a separated t1-order non-single crystal semiconductor on an insulating substrate surface by irradiating it with a t energy beam.
表面妙ＩＰ＃物よりなる基板上に島状に分離され次午導
体素子全形成するＳｏｌ（ｆ３１１１ｅｏｎａｎＩｎａ
ｕｔ１０ｎｇ ５ｕｂｓｔｒａｔ＠）構造の半導体装
置の製造工ｓにおいて、絶縁基板面上の非単結晶シリコ
ンすなわち多結晶シリコン或い扛非結晶シリコンにより
形成された島状に分離された薄膜状牛導体領竣會単結晶
化する熱処理に実施する場合に、特に対策を講じない＠
す、各牛導体領絨の端部がその中央部分に比較して低温
となり、再結晶化は周辺部分より始する穴めに多結晶と
なり易く、単結晶化の目的を達成するためＫは各半導体
領域の中央附近の一個所に温度の最低点を設けて、再結
晶化ｔこの位置より開始させることが必要とされている
。Sol (f3111eonanIna
In a manufacturing process for a semiconductor device having a ut10ng 5ubstrat@) structure, thin film conductor regions separated into islands formed by non-single crystal silicon, that is, polycrystalline silicon or amorphous silicon on an insulating substrate surface are completed. No special measures are taken when performing heat treatment to form a single crystal.
The ends of each conductor area are lower in temperature than the center, and recrystallization tends to form polycrystals in the holes starting from the peripheral areas.In order to achieve the purpose of single crystallization, K is It is necessary to provide a lowest temperature point at a location near the center of the semiconductor region and to initiate recrystallization from this location.
本発明は、勅記の単結晶化のためのエネルギ線すなわち
波動或い扛粒子ビーム照射による熱処理において、再結
晶化【−個所より開始せしめる具体的でかつ確実な方法
を得ること上目的とする。The purpose of the present invention is to obtain a specific and reliable method for starting recrystallization from a point in heat treatment using an energy beam, that is, wave or particle beam irradiation for single crystallization according to the Imperial Rescript. .
本発明は、非単結晶半導体領域の一部分と基板下面との
間の熱抵抗を、非単結晶半導体領域の他の部分と基板下
面との間の熱抵抗より小ならしめて、エネルギ線の照射
後結晶化温度に最初に到達する位置を各半導体領域内ｋ
、通常は中央附近に設定することＫより達成される。The present invention makes the thermal resistance between a part of the non-single crystal semiconductor region and the lower surface of the substrate smaller than the thermal resistance between the other part of the non-single crystal semiconductor region and the lower surface of the substrate, and The position where the crystallization temperature first is reached is determined by k within each semiconductor region.
, is usually achieved by setting K near the center.
９下本発明を実施例により図面を用いて詳細に説明する
。第１図（ａ）及び（ｂ）は第一の実施例を示す平面図
及び断面図である０本実施例においてにシリコン基板１
のＲｍＫ二酸化シリ”７（Ｓ ｉ Ｏ，）よｐなる絶縁
膜２ｔ−熱酸化法により形成するＫあ７’ｌ、予め基板
ｌ上に窒化シリコン（８１１Ｎ４）等より々るマスクを
配設することくより、％牛導体領琥形成位置に一個所づ
つ、２４ｍＸ２μｍ程駅の面積食前する酸化を阻止され
た部分３を設けて厚さ約１μｍの二酸化シリコン膜を形
成し、次いで前記マスクを除去して更に酸化を行ない、
先の酸化を阻止された部分３にシいて厚さ約５０ｎｍの
二酸化シリコン膜４管形成した・これが本発明の特徴と
する給線基板の一例である。なお二酸化シリコンｌｉ４
に代えて、窒化シリコン膜等を形成してもよい。9, the present invention will be explained in detail by way of examples with reference to the drawings. FIGS. 1(a) and 1(b) are a plan view and a cross-sectional view showing a first embodiment.
An insulating film 2t made of RmK silicon dioxide (S i O,) is formed by a thermal oxidation method, and a mask made of silicon nitride (811N4) or the like is placed on the substrate l in advance. Specifically, a silicon dioxide film with a thickness of about 1 μm was formed by forming a silicon dioxide film with a thickness of about 1 μm by providing a portion 3 of about 24 m x 2 μm in area where the area of the conductor was to be formed, and which was prevented from oxidation, and then removing the mask. and further oxidize,
Four tubes of silicon dioxide film with a thickness of about 50 nm were formed on the portion 3 where the oxidation was previously prevented.This is an example of a feed line substrate that is a feature of the present invention. Furthermore, silicon dioxide li4
Instead, a silicon nitride film or the like may be formed.
以上の如き絶縁基板上に化学蒸着法等により非単結晶シ
リコン層を厚さ約４００ ｎｍＫ形成し、島状に分離さ
れた非単結晶シリコン領域５を形成すべき部分に窒化シ
リコンよｊｌにるマスクを用い１熱酸化処理を行なう、
この熱酸化処Ｍは隣接する領域との中間の部分の非単結
晶シリコン層が完全に酸化されるまで行ない、分離され
九非単結晶シリコン領琥５を形成する。A non-single crystal silicon layer with a thickness of about 400 nm is formed on the insulating substrate as described above by chemical vapor deposition or the like, and a layer of silicon nitride is deposited on the portion where the island-shaped non-single crystal silicon region 5 is to be formed. 1. Perform thermal oxidation treatment using a mask.
This thermal oxidation treatment M is carried out until the non-single crystal silicon layer in the intermediate portion between adjacent regions is completely oxidized, and is separated to form nine non-single crystal silicon regions 5.
この基板上レーザ光等の波動或いは電子その他の粒子ビ
ームを照射することＫよシ加熱して非単結晶シリコン領
域５ｔ−融解温度以上とし、主として基板側より冷却す
る。このとき、非単結晶シリコン領域５より基板１への
熱伝導は二酸化シリコン膜２及び４を介して行なわれる
が、二酸化シリコンの熱比抵抗にシリコンに比較して大
略ｌＯ倍程度であるためにに酸化シリコン膜厚の薄い第
一の酸化管阻止された部分３に対応する位置が非単結晶
シリコン領域５内で最も低温となり、この位置が最初に
再結晶温度に到達して再結晶化はこの位置より始ｔり次
第に周囲に拡がるために単結晶を得る。The substrate is heated by irradiating waves such as laser light or beams of electrons or other particles to a temperature higher than the melting temperature of the non-single crystal silicon region 5t, and is cooled primarily from the substrate side. At this time, heat conduction from the non-single crystal silicon region 5 to the substrate 1 is carried out via the silicon dioxide films 2 and 4, but since the thermal specific resistance of silicon dioxide is approximately 1O times that of silicon, The position corresponding to the first oxidation tube blocked portion 3 where the silicon oxide film is thin becomes the lowest temperature in the non-single crystal silicon region 5, and this position first reaches the recrystallization temperature and recrystallization does not occur. Starting from this position, a single crystal is obtained by gradually expanding to the periphery.
以上の如く形成された島状に分離された単結晶シリコン
領域が配設されたｆ！板面上ＫＮ−ＭＯ８電界効果トラ
ンジスタ（Ｎ−ＭＯＳ ＦＥＴ）ｋ形成した実施例を
第１１１０（ｃ）及び（ｄ）Ｋ示す、第１図（ｃ）は平
面図であって、ゲート電極６、ソース領域７、ドレイン
領域８、及びゲート電極６への配線９、ソース領ｊ１１
７への配＠１０、ドレイン領域８への配置１１１及び各
配線のコンタクトのための層間絶縁膜の開口及び第一の
酸化管阻止され′ｆｃｓ分３のみを示し、第１図（ｄ）
Ｈ＃！１図（ｃ）ＯＡ−Ａ断面図である。The f! 1110(c) and (d)K show an embodiment in which a KN-MO8 field effect transistor (N-MOS FET) was formed on a plate surface. FIG. 1(c) is a plan view, in which the gate electrode 6, Source region 7, drain region 8, wiring 9 to gate electrode 6, source region j11
7, the arrangement 111 to the drain region 8, the openings in the interlayer insulating film for the contacts of each wiring, and only the first oxidized tube blocked 'fcs part 3 are shown, as shown in FIG. 1(d).
H#! FIG. 1(c) is a sectional view taken along OA-A.
第１図−）乃至（ｄ） Ｋ示した実施例においては第一
の酸化ｔ−阻止された部分３はＮ−ＭＯＳＦＥＴのソ・
−ス領域７の下に位置したが、苧導体素子の形成に際し
て、絶縁膜の薄い第一の酸化ｔ−阻止されり部分３０直
上を避けることも゛可能である・即ち第２１１（ａ）Ｋ
示す如く、第１図（ｂ）［示した第一の実施例と同様に
基板２１の表面に絶縁膜２２及び絶縁膜の薄い部分２３
に形成後、非単結晶シリコン層を形成し、パターニング
を行って島状に分離された非単結晶シリコン領域を得、
次いでレーザ光等の波動或いは電子その他の粒子ビーム
ｖｍ射することにより加熱［７丁卯単結晶シリコン領緘
會融解し、これを冷却するとき絶縁膜の薄い部分２３の
効果により単結晶シリコン領域２４ｔ−得る。こン等に
よるマスク２５ｔ−形成して熱酸化することにより、前
記単結晶シリコン領堵２４のうち、絶縁膜の薄い部分２
３１に含むマスク２５の被覆しな・い部分に酸化さ名、
新たな単結晶シリコン領域２６を得る。或いに、前記マ
スク２５に：代ってホトリソグラフィ用マスク２５′を
形成し、絶縁膜の薄い部分２３の真土部等ｔ″選択的に
除去して新たな単結晶シリコン９Ａ斌を得る。1-) to (d) K In the embodiment shown, the first oxidation-blocked portion 3 is the
However, when forming the conductor element, it is also possible to avoid directly above the thin first oxidation-blocking portion 30 of the insulating film.
As shown in FIG. 1(b) [similar to the first embodiment shown, an insulating film 22 and a thin part 23 of the insulating film are formed on the surface of the substrate 21.
After forming a non-single crystal silicon layer, patterning is performed to obtain non-single crystal silicon regions separated into islands.
Next, the single crystal silicon region 24t is heated by irradiating waves such as laser light or electron or other particle beams to melt the single crystal silicon region 24t, and when it is cooled, the single crystal silicon region 24t is - get. By forming a mask 25t using the above and thermally oxidizing the thin portion 2 of the insulating film in the single crystal silicon region 24,
Oxidized portions of the mask 25 included in 31 that are not covered,
A new single crystal silicon region 26 is obtained. Alternatively, a photolithography mask 25' is formed in place of the mask 25, and the base part etc. of the thin part 23 of the insulating film is selectively removed to obtain a new single crystal silicon 9A. .
ｖ上の実施例においてに、基板をシリコン、基板上の絶
縁膜を二酸化シリコンとしたが、基板及び絶縁膜？形成
する物質は前記例に限定されるものでになく、μ・板を
形成する物質の熱比抵抗が絶縁膜を形成する物質の熱比
抵抗より／Ｊ１となる組合せ倉選択し、単結晶化する領
域のうち、再結晶化を開始した１１点の下部においτＰ
＃Ｈｔ簿〈すればよい。v In the above embodiment, the substrate was silicon and the insulating film on the substrate was silicon dioxide, but what about the substrate and the insulating film? The material to be formed is not limited to the above example, but a combination in which the thermal resistivity of the material forming the μ plate is /J1 than that of the material forming the insulating film is selected, and a single crystal is formed. τP at the bottom of the 11 points where recrystallization started in the region where
#Ht book〈Just do it.
更に熱抵抗の小なる部分を形成する他の方法として框、
基板より熱比抵抗が小である瞼質、例えばモリブデン（
Ｍｏ）による点状パターンをシリコン基板上に配設し、
しかる後に化学蒸着法等により絶縁膜を形成すれば、点
状パターンが埋設された位置は熱抵抗が低くなる。Another way to create a part with even lower thermal resistance is to use a frame,
Eyelid materials with lower thermal resistivity than the substrate, such as molybdenum (
A dot pattern made of Mo) is arranged on a silicon substrate,
If an insulating film is then formed by chemical vapor deposition or the like, the thermal resistance will be lowered at the position where the dotted pattern is embedded.
また、基板が半導体、例えばシリコンよりなりその比抵
抗が２０ｏｈｍ−ａｍであるとき、放熱路を配設する位
置Ｏみに選択的に多量のイオン注入を行ない、例えば砒
素イオン（Ａｓ”ｌ濃ｆ會４ ｘ ｌＧ”／−程度とす
る。このとき電気抵抗とともにこの位置の熱抵抗もイオ
ン注入しない領域に比験して相対的に低下する。Further, when the substrate is made of a semiconductor, for example, silicon and its resistivity is 20 ohm-am, a large amount of ions are selectively implanted only at the position O where the heat dissipation path is provided, for example, arsenic ions (As) 4.times.1G"/-. At this time, the thermal resistance at this position as well as the electrical resistance is relatively reduced compared to the region where ions are not implanted.
本発明は以上説明した如く、ＳＯＩ構造の半導体装置の
製造工程において、ｌ！緑基板上の非単結晶シリコンに
より形成された半導体領域會エネルギ線すなわち波動或
いは粒子ビーム照射によ９糎熱融解し再結晶せしめて単
結晶化するに際し、序導体領域の一部分と基板下面との
間の熱抵抗を、半導体領域の他の部分と基板下面との間
Ｏ熱ａ仇より小とすることＫより１半導体領櫨内に設定
された一点が最初に再結晶温［Ｋ到達して仁の点より再
結晶化が開始さ名ることにより単結晶化を確実ならしめ
る効果を有する。As explained above, the present invention provides l! When a semiconductor region formed of non-single-crystal silicon on a green substrate is thermally melted and recrystallized into a single crystal by irradiation with an energy beam, that is, a wave or a particle beam, a part of the conductor region and the bottom surface of the substrate are The thermal resistance between the other parts of the semiconductor region and the bottom surface of the substrate should be smaller than the thermal resistance between the other part of the semiconductor region and the lower surface of the substrate. Since recrystallization starts from the core point, it has the effect of ensuring single crystallization.
第１図（ａ）及び（ｃ）は本発明の実施例を示す１ｌＩ
ｓ平面図、第１図（ｂ）及び（ｄ）はそれヤれ第１１侃
）或いは（ｅ） Ｋ対応する断面図で＃り、第２ＷＪ（
ａ）及び（ｂ）＊他の実施例管示す断面＠でＩｈゐ・
図において、１は基板、２ね終縁膜、３は第一の酸化を
阻止された部分、４はＰ縁膜、５はシリコン領域、６は
ゲート電極、７はソース領域、８にドレイン領域、９灯
配曽、１０は配線、１１は配線、２１は基板、２２ＦＸ
？縁膜、２３は終縁膜の薄い部分、２４はシリコン領域
、２５はｉスフ、２６はシリコン領域を示す。
：Ｐ１図（（Ｌ）
（レノ
フ
（Ｑ）
（ｄ）
Ｐ２図（勾
２
（し）FIGS. 1(a) and (c) show an embodiment of the present invention.
s plan view, Figures 1 (b) and (d) are the 11th section) or (e) K is the corresponding sectional view, and the 2nd WJ (
a) and (b) *Cross section showing other embodiments @Ihゐ In the figure, 1 is the substrate, 2 is the terminating film, 3 is the first oxidation-blocked part, 4 is the P rim film, 5 is a silicon region, 6 is a gate electrode, 7 is a source region, 8 is a drain region, 9 is a light source, 10 is a wiring, 11 is a wiring, 21 is a substrate, 22FX
? 23 is a thin portion of the terminating film, 24 is a silicon region, 25 is an i-splash, and 26 is a silicon region. : P1 figure ((L) (Lenov (Q) (d) P2 figure (gradient 2 (shi)
Claims (1)
設し、エネルギ繊の照射により＃非単結晶半導体領域を
単結晶半導体領域に変換し、該単結晶半導体領域に半導
体素子を形成する半導体装置の製造方法において、該非
単結晶半導体領域の一部分と骸基板下面との間の熱抵抗
を、該非単結晶半導体領域の他の部分と該基板下面との
間の熱抵抗より小ならしめて、腋エネルギ線照射を行な
うことに特徴とする半導体装置の製造方法。A non-single-crystal semiconductor region is provided on an insulating film formed on a substrate, the non-single-crystal semiconductor region is converted into a single-crystal semiconductor region by irradiation with an energy fiber, and a semiconductor element is formed in the single-crystal semiconductor region. In the method of manufacturing a semiconductor device, the thermal resistance between a part of the non-single crystal semiconductor region and the bottom surface of the skeleton substrate is made smaller than the thermal resistance between the other part of the non-single crystal semiconductor region and the bottom surface of the substrate. , a method for manufacturing a semiconductor device characterized by performing armpit energy ray irradiation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11186781A JPS5814525A (en) | 1981-07-17 | 1981-07-17 | Manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11186781A JPS5814525A (en) | 1981-07-17 | 1981-07-17 | Manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5814525A true JPS5814525A (en) | 1983-01-27 |
| JPH0376017B2 JPH0376017B2 (en) | 1991-12-04 |
Family
ID=14572149
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11186781A Granted JPS5814525A (en) | 1981-07-17 | 1981-07-17 | Manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5814525A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59147425A (en) * | 1983-02-10 | 1984-08-23 | Seiko Instr & Electronics Ltd | Formation of semiconductor crystal film |
| JPS6017911A (en) * | 1983-07-11 | 1985-01-29 | Agency Of Ind Science & Technol | Manufacture of semiconductor device |
| JPS60210833A (en) * | 1984-04-05 | 1985-10-23 | Agency Of Ind Science & Technol | Manufacture of semiconductor device |
| JPS6178917A (en) * | 1984-09-22 | 1986-04-22 | Teruo Koi | Construction of foundation pile |
-
1981
- 1981-07-17 JP JP11186781A patent/JPS5814525A/en active Granted
Non-Patent Citations (1)
| Title |
|---|
| APPL PHYS LETT * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59147425A (en) * | 1983-02-10 | 1984-08-23 | Seiko Instr & Electronics Ltd | Formation of semiconductor crystal film |
| JPS6017911A (en) * | 1983-07-11 | 1985-01-29 | Agency Of Ind Science & Technol | Manufacture of semiconductor device |
| JPS60210833A (en) * | 1984-04-05 | 1985-10-23 | Agency Of Ind Science & Technol | Manufacture of semiconductor device |
| JPS6178917A (en) * | 1984-09-22 | 1986-04-22 | Teruo Koi | Construction of foundation pile |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0376017B2 (en) | 1991-12-04 |
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