JPS59168673A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS59168673A JPS59168673A JP4281783A JP4281783A JPS59168673A JP S59168673 A JPS59168673 A JP S59168673A JP 4281783 A JP4281783 A JP 4281783A JP 4281783 A JP4281783 A JP 4281783A JP S59168673 A JPS59168673 A JP S59168673A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- deposited
- wiring
- semiconductor device
- moreover
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 239000010409 thin film Substances 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 abstract description 19
- 239000000758 substrate Substances 0.000 abstract description 16
- 229910052751 metal Inorganic materials 0.000 abstract description 12
- 239000002184 metal Substances 0.000 abstract description 12
- 239000011521 glass Substances 0.000 abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 5
- 229910052782 aluminium Inorganic materials 0.000 abstract description 4
- 229910052804 chromium Inorganic materials 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 238000002955 isolation Methods 0.000 abstract description 3
- 229910052750 molybdenum Inorganic materials 0.000 abstract description 2
- 238000001259 photo etching Methods 0.000 abstract description 2
- 239000010453 quartz Substances 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 2
- 238000001039 wet etching Methods 0.000 abstract description 2
- 238000001312 dry etching Methods 0.000 abstract 1
- 230000002349 favourable effect Effects 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 238000000605 extraction Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は、絶縁性基板上に形成した半導体層を用いて作
製され之半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device manufactured using a semiconductor layer formed on an insulating substrate.
従来の絶縁性基板上の半導体（例えばシリコン）を用い
た薄膜半導体装置は、シリコン結晶を基板に用いた装置
に比較してアイソレーション（素子間分離）が容易で且
つ浮遊容量が少ないという利点がある。Conventional thin-film semiconductor devices using semiconductors (e.g. silicon) on insulating substrates have the advantage of easier isolation (separation between elements) and less stray capacitance than devices using silicon crystals as substrates. be.
Ｓ ＯＳ （Ｓｉ、ｘｉｃｏｎ Ｏｎ ５ａｐｐｈｉ、
ｒｅ ） 技術はそれ等利点を充分に満足するもので
はあるが、基板に用いるサファイアが高価な為、製品の
コストが割高になるという問題があった。又、ＳＯ８技
術によるＭ ＯＳ （Ｍｅｔａｌ ０ｘｉｃｌｅ Ｓｅ
ｍ１ｃｏｎａｕｃｔｏｒ ）型トランジスタ等の製作工
程は、従来のシリコン７Ｌ／−ナ一工程を用いるので、
酸化、拡散、イオンインプランテーション、アニール等
の高温の工程を通らないとデバイスの作製が出来ないと
いう問題点も有している。従って、デバイス作製時の電
極の配線は、高温工程を通った後に、絶縁層の上部で全
て行なうことが通常行なわれるＱ
又、従来の方法では、絶縁層にコンタクトホールを開け
、素子の上部で配線を行なっているが、この方法では、
コンタクトホールのための面積が半導体装置の上部にあ
ることが必要であるので、半導体装置の集積度はある程
度限定されてしまうという問題があった。更に、装置上
部に配線が多く施されるということは、配線同士の短絡
を防ぐ為の工程も増加することになる。S OS (Si,xicon On 5apphi,
Although the technology fully satisfies these advantages, the sapphire used for the substrate is expensive, so there is a problem that the cost of the product is relatively high. In addition, MOS (Metal Oxicle Se) using SO8 technology
The manufacturing process for m1conauctor) type transistors uses the conventional silicon 7L/-na process, so
Another problem is that devices cannot be manufactured without going through high-temperature processes such as oxidation, diffusion, ion implantation, and annealing. Therefore, all electrode wiring during device fabrication is normally done on the top of the insulating layer after going through a high-temperature process. I am doing the wiring, but with this method,
Since the area for the contact hole needs to be in the upper part of the semiconductor device, there is a problem in that the degree of integration of the semiconductor device is limited to some extent. Furthermore, the fact that a large number of wiring lines are provided on the upper part of the device means that the number of steps required to prevent short circuits between the wiring lines is also increased.
本発明は上記の諸点に鑑み成されたもので、コンタクト
ホールの数を減らし、且つ、配線の交差を少なくして回
路全体の浮遊容量を減少させることのできる構成を持っ
た半導体装置を提供することを目的とする。又、本発明
の別の目的は、歪みのな（・良好ｂトランジスタ特性を
示す薄膜トランジスタを用いた周波数特性が良好でリー
クのない半導体装置を提供することである。The present invention has been made in view of the above points, and provides a semiconductor device having a structure that can reduce the number of contact holes and the number of interconnections crossing each other, thereby reducing the stray capacitance of the entire circuit. The purpose is to Another object of the present invention is to provide a semiconductor device with good frequency characteristics and no leakage, using a thin film transistor that is free from distortion and exhibits good b-transistor characteristics.
本発明の半導体装置は、薄膜トランジスタのソース領域
又はドレイン領域へ接続される配線の少なくとも一部が
前記ソース領域又は前記ドレイン領域と同じ断面構成を
持つ配線部分から成り、かつ、前記配線部分が前記ソー
ス領域又は前記ドレイン領域から連続して形成されてい
ること１に特徴とする。In the semiconductor device of the present invention, at least a part of the wiring connected to the source region or the drain region of the thin film transistor is composed of a wiring portion having the same cross-sectional configuration as the source region or the drain region, and the wiring portion is connected to the source region or the drain region. It is characterized in that it is formed continuously from the region or the drain region.
上記の様な構成で成る本発明の半導体装置は、前述した
従来技術の多くの問題点を解決するのみならず、再現性
良く簡単に作製することも可能なものである。The semiconductor device of the present invention configured as described above not only solves many of the problems of the prior art described above, but also can be easily manufactured with good reproducibility.
又、本発明の様な構成をもった半導体装置はコンタクト
ホールの数が非常に減少するので、素子の集積化も創る
こともできる。又、本発明によれば、素子全体の浮遊容
量も減少させることが出来る０
以下、本発明の目的を達成する為の方法を説明する。Furthermore, since the number of contact holes in a semiconductor device having the structure of the present invention is greatly reduced, it is also possible to integrate elements. Further, according to the present invention, the stray capacitance of the entire device can be reduced.A method for achieving the object of the present invention will be described below.
不発明の半導体装置は薄膜トランジスタ（ＴＰＴ）を集
積化したものである。即ち、基板上に半導体層が堆積さ
れ、その上にソース領域、ドレイン領域及びそれ等に接
続される配線の少なくとも一部を構成するｎ＋層（半導
体をル型に制御した層）と金属コンタクト層が順に積層
される（以下、１Ｌ″一層と金属フンタクト層を合わせ
てコンタクト層と称す）。更に、絶縁層が積層されてか
らゲート用電極が設けられ、必要な部分に外部との電気
的な接続を果たす為の外部取り出し電極が配置される。The uninvented semiconductor device is an integrated thin film transistor (TPT). That is, a semiconductor layer is deposited on a substrate, and an n+ layer (a layer in which the semiconductor is controlled in a rectangular shape) and a metal contact layer that constitute at least a part of the source region, drain region, and wiring connected to these regions are deposited on the substrate. are laminated in order (hereinafter, the 1L'' layer and the metal contact layer are collectively referred to as the contact layer).Furthermore, after the insulating layer is laminated, gate electrodes are provided, and electrical connections with the outside are provided in necessary parts. External lead-out electrodes are arranged for connection.
本発明の半導体装置は、基本的には上記の様な構成から
成っている。ＴＰＴのソース領域及びドレイン領域に接
続される配線の少なくとも一部（以下配線部分と称す）
は絶縁層と半導体層の間に存在することになる。又、ソ
ース領域、ドレイン領域の構成と、内部の配線部分の構
成とは同じ断面構成となっている。The semiconductor device of the present invention basically has the above structure. At least a part of the wiring connected to the source region and drain region of the TPT (hereinafter referred to as the wiring part)
exists between the insulating layer and the semiconductor layer. Further, the structure of the source region and drain region and the structure of the internal wiring portion have the same cross-sectional structure.
本発明は、絶縁性基板を半導体装置の基板として用いて
〜・るが、例えば、絶縁性基板としてガラスが用いられ
た場合は、熱酸化、拡散、イオンイングランチージョン
、熱処理等の高温工程を用いて半導体装置を作製するこ
とはできない。そこで、ガラス基板を用〜・る場合は、
Ｐ ＣＶ Ｄ （ＰｌａｓｍａＯｈθｍ１ｃａｌ Ｖａ
ｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ ）法やＬＰＣＶＤ（Ｌ
ｏｗＰｒｅｓｅｕｒｅ Ｃｂｅｍｉｃａｌ ’Ｖａｐｏ
ｒ Ｄｅｐｏｓｉｔｉｏｎ）法等を用いて半導体層が形
成される。これ等の方法によれは、基板温度が８００℃
以下の比較的低い温度でも半導体層を形成することがで
きる。又、絶縁層も、低温形成することのできる５ｔ−
Ｎ−Ｈ層、 Ｓ、ｔ０２層。The present invention uses an insulating substrate as a substrate of a semiconductor device. For example, when glass is used as an insulating substrate, high-temperature processes such as thermal oxidation, diffusion, ion implantation, and heat treatment are performed. It is not possible to fabricate a semiconductor device using this method. Therefore, when using a glass substrate,
P CV D (PlasmaOhθm1cal Va
por Deposition) method and LPCVD (L
owPressure Cbemical 'Vapo
A semiconductor layer is formed using a method such as .r Deposition method. With these methods, the substrate temperature is 800℃.
A semiconductor layer can be formed even at a relatively low temperature below. In addition, the insulating layer is also made of 5t-
N-H layer, S, t02 layer.
５ｌ−Ｎ−０層等が好適に用いられる。コンタクト用の
金属層等の配線部紘、金属を蒸着することによって形成
される。A 5l-N-0 layer or the like is preferably used. Wiring portions such as metal layers for contacts are formed by vapor depositing metal.
本発明に用いられる半導体層としては、多結晶シリコン
、結晶化シリコン、非晶質シリコン等を挙げることがで
きる。又、所望の半導体層の特性が得られれば、半導体
層の全てを多結晶シリコン。Examples of the semiconductor layer used in the present invention include polycrystalline silicon, crystallized silicon, amorphous silicon, and the like. Moreover, if the desired characteristics of the semiconductor layer can be obtained, the entire semiconductor layer can be made of polycrystalline silicon.
結晶化シリコン、非晶質シリコンにする必要はなく、そ
れ等が一部分のみに用いられているのでも良い。It is not necessary to use crystallized silicon or amorphous silicon, and they may be used only in part.
〔実施例１〕
以下、本発明を好適な実施例を用いて更に詳しく説明す
る。[Example 1] Hereinafter, the present invention will be explained in more detail using preferred examples.
第１図に示される模式的切断面図である工程（ａ）乃至
工程（ｅ）は本発明の好適な一つの実施例を作成である
。又、各工程図は第１図（ロ）に示される１点鎖線ｘ
−ｘ’で切断した部分に於ける工程を示す。Steps (a) to (e), which are schematic cross-sectional views shown in FIG. 1, are for creating a preferred embodiment of the present invention. In addition, each process diagram is indicated by the dashed-dotted line x shown in Figure 1 (b).
- Shows the process in the section cut at x'.
先ず、ガラス、石英等の絶縁性の基板１ｏｏを研摩洗浄
した後、グロー放電法を用いて多結晶シリコンの半導体
層１０１が約２ｓｏｏＸ堆積された。First, after polishing and cleaning an insulating substrate 1oo made of glass, quartz, etc., a polycrystalline silicon semiconductor layer 101 of about 2 sooX was deposited using a glow discharge method.
次に、バルク抵抗０．１Ω・ｃｍのｒＬ＋層（本実施例
ではシリコンをＬ型に制御する不純物が含まれに層）１
０２が同じくグロー放電法を用いて約８０ＯＡ堆積され
た。更に、コンタクト用金属層として、例えばアルミニ
ウム、モリブデン、クロム等が蒸着された（工程（ａ）
）。次に、ＴＰＴ部分イと配線部分口等のアイソレーシ
ョンがドフィエッチング又はウェットエツチングによっ
て行なわれ、その後、ソース領域ゝ１０５，１０６とド
レイン領域１０７゜１０８が形成された（工程（ｂ））
ｏこの時、１０９０部分はチャネル領域となる。次に、
絶縁層１１６が約３ｆＪＯＯＡ堆積された（工程（ｃ）
） ｏそれからコンタクトホール１１４が開けられた
（工程（ｄＪ）０更に上部ゲート電極１１５及び取り出
し用電極１１６用のアルミニウム、クロム等の金属が蒸
着され、フォトエツチング法によって成型されて電極が
形成された（工＆８（θ））。Next, an rL+ layer (in this example, a layer containing impurities that controls silicon to be L-type) with a bulk resistance of 0.1 Ω・cm 1
02 was also deposited at about 80 OA using the glow discharge method. Further, as a metal layer for contact, for example, aluminum, molybdenum, chromium, etc. were vapor-deposited (step (a)
). Next, isolation between the TPT portion A and the wiring portion openings was performed by dophy etching or wet etching, and then source regions 105 and 106 and drain regions 107 and 108 were formed (step (b)).
o At this time, the 1090 part becomes a channel region. next,
An insulating layer 116 was deposited about 3f JOOA (step (c)
) Then, a contact hole 114 was opened (Step (dJ)0) Furthermore, metals such as aluminum and chromium for the upper gate electrode 115 and extraction electrode 116 were vapor-deposited, and the electrodes were formed by molding by photo-etching. (Eng & 8(θ)).
以上の工程で本発明の構成を持った一つの実施例は作製
された。One embodiment having the structure of the present invention was manufactured through the above steps.
尚、配線部分口の外部配＆ｌ取出部１１１，１１２はそ
れぞれドレイン領域の１０７，１０８から連続的に形成
されている。配線部分口はこの様にＴＰＴのすぐ横でな
く配線に適当な位置に形成してももちろんかまわない。Note that the external wiring extraction portions 111 and 112 of the wiring portion opening are formed continuously from the drain regions 107 and 108, respectively. It goes without saying that the wiring opening may be formed at an appropriate position for the wiring instead of immediately next to the TPT.
又、外部回路と接続したり、或は信号を入出力する場合
等、必要に応じてコンタクトホールを通じて配線を行な
えば良い。Further, wiring may be performed through contact holes as necessary, such as when connecting to an external circuit or inputting/outputting signals.
〔実施例２〕
本発明の第２の実施例を第２図乃至第５図（Ｃ）を用い
て説明する。第２図は本実施例の１６ビツトシフトレジ
スターの回路図であり、第６図は第２図のシフトレジス
タの１ビット分の模式的配線平面図である。第４図は第
６図に示される１点鎖線で囲まれた領域Ｐを拡大した模
式的拡大図である〇第５図（ａ） 、 （ｂ）及び（ｃ
）は各々順に第４図に示される１点鎖線Ａ−Ａ’、 Ｂ
−Ｂ部、 Ｃ−Ｇ’で切断した場合の模式的切断面図で
ある。[Embodiment 2] A second embodiment of the present invention will be described with reference to FIGS. 2 to 5(C). FIG. 2 is a circuit diagram of the 16-bit shift register of this embodiment, and FIG. 6 is a schematic wiring plan view for one bit of the shift register of FIG. 2. Figure 4 is a schematic enlarged view of the area P surrounded by the dashed line shown in Figure 6. Figures 5 (a), (b) and (c)
) are respectively indicated by the dashed-dotted lines AA' and B shown in FIG.
-B section is a schematic cross-sectional view when cut along CG'.
本実施例はフーニングナ７０５９ （商品名：コーニン
グ社製）ガラス基板上に薄膜多結晶シリコンを堆積し、
第１図に示される工程（ａ）から工程（θ）で示した工
程と同様な工程に従って作製された。In this example, a thin film of polycrystalline silicon was deposited on a glass substrate of Corningna 7059 (product name: manufactured by Corning Incorporated).
It was produced according to the same steps as those shown from step (a) to step (θ) shown in FIG.
第６図に示されるＡ部、即ちドライバーＱ１及びトラン
スファーゲートＱ３のＴＰＴの形状は、チャネルｒｌｒ
をＷ、チャネル長をＬとするとＷ／Ｌ ＝１５００μ／
２０μとされた。又同図に於て、Ｂ部、即ちロードのＴ
ＰＴの形状はＷ／Ｌ＝１５０μ／２０μとされた０バツ
フアーのＴ Ｆ Ｔ Ｑ４．Ｑ５のＷ／Ｌはそれぞれ３
０００μ／２０μ、６００μ７２０μとされた。又、ゲ
ートとソース領域、ゲートとドレイン領域トの重なりは
各々２，５μとされた。The shape of the TPT of part A shown in FIG. 6, that is, the driver Q1 and the transfer gate Q3, is the channel rlr.
When W is the channel length and L is the channel length, W/L = 1500μ/
It was set to 20μ. Also, in the same figure, part B, that is, T of the load
The shape of PT is 0 buffer T F T Q4. with W/L=150μ/20μ. W/L of Q5 is 3 each
000μ/20μ, 600μ720μ. Further, the overlap between the gate and the source region and the overlap between the gate and the drain region was set to 2.5 μm, respectively.
第４図乃至第５図（Ｃ）に於いて、５０１は取り出し用
電極、５０２は半導体層、５０３はｎ＋層、５０４Ｕ金
属コンタクト層、５０５は絶縁層、５０６はゲート電極
、５０７は配線用金属層である。In FIGS. 4 and 5(C), 501 is an extraction electrode, 502 is a semiconductor layer, 503 is an n+ layer, 504U metal contact layer, 505 is an insulating layer, 506 is a gate electrode, and 507 is a wiring metal It is a layer.
第５図（ａｌ及び第５図（１））に示される様に、本実
施例では半導体層と１層からなるソース領域、及び同じ
く半導体層と１層からなるドレイン領域、更に同じく半
導体層と１層からなる配線部分は絶縁層と基板との間に
設けられる。上記の憾に各領域と配線部分は同じ断面構
成を持っているので各領域と配線部分は断差が生じてい
ない。As shown in FIG. 5 (al and FIG. 5 (1)), in this example, there is a source region made up of a semiconductor layer and one layer, a drain region also made of a semiconductor layer and one layer, and a drain region also made of a semiconductor layer and one layer. A wiring portion consisting of one layer is provided between the insulating layer and the substrate. Unfortunately, since each region and the wiring portion have the same cross-sectional configuration, there is no difference between each region and the wiring portion.
又、本実施例に於いて、半導体装置上部に形成される電
極配線はソース領域或はドレイン領域へ接続される外部
配線とゲート電極のみである。Further, in this embodiment, the electrode wiring formed on the upper part of the semiconductor device is only the external wiring connected to the source region or the drain region and the gate electrode.
本実施例では、配線部の交差数が非常に少なく出来たの
で回路全体の浮遊容量も少なくおさえることが出来た。In this embodiment, since the number of intersections in the wiring portions was extremely small, the stray capacitance of the entire circuit could also be kept small.
本実施例のシフトレジスターの動作周波数を測定した結
果、本発明の様な構成のＴＰＴ単体で電子の実効移動度
が５ ｃｍ”／ Ｖ−ｓｅｃの場合に動作周波数を測定
したところ十分に高い値が得られ、本発明によるＴＰＴ
の性能は充分なものであることが確認された。As a result of measuring the operating frequency of the shift register of this example, when the effective mobility of electrons is 5 cm"/V-sec in a single TPT having a structure like the present invention, the operating frequency was found to be a sufficiently high value. is obtained, and TPT according to the present invention
It was confirmed that the performance was sufficient.
第１図は本発明の第１の実施例を作製する為の模式的切
断面工程図である。第２図は第２の実施例の１６ビツト
シフトレジスタの回路図であり、第６図は第２の実施例
の１ビット分の模式的配線平面図である。第４図は第３
図に示される１点鎖線で囲ま八た領域Ｐを拡大した模式
的拡大図である。第５図（（転）乃至第５図（Ｃ）は各
り順に第４図に示される１点鎖線Ａ−Ａ、Ｂ−Ｂ’、Ｃ
−αで切断した場合の模式的切断面図である。
１００・・・基板、 １０１．１０４，１１０．５０
２・・・半導体層１０２．１０５，１０８，１１１，５
０３・・・１層１０３．１０６，１０８，１１２．５０
４−−−金属−ｙンｐクト層１１３．５０５・・・絶縁
層、１１４・・・コンタクトボール１０９・・・チャネ
ル領域、１１５，５０６・・・ゲート電極１１６．５０
１・・・取り出し用電極
５０７・拳・配線用金属層
出願人 キャノン株式会社FIG. 1 is a schematic cross-sectional process diagram for manufacturing the first embodiment of the present invention. FIG. 2 is a circuit diagram of a 16-bit shift register of the second embodiment, and FIG. 6 is a schematic wiring plan view for one bit of the second embodiment. Figure 4 is the third
FIG. 2 is a schematic enlarged view of an area P surrounded by a dashed-dotted line shown in the figure. FIG. 5 ((translation) to FIG. 5(C) are respectively indicated by dashed-dotted lines AA, BB', and C shown in FIG. 4 in order.
FIG. 3 is a schematic cross-sectional view when cut at −α. 100...Substrate, 101.104, 110.50
2... Semiconductor layer 102.105, 108, 111, 5
03...1 layer 103.106, 108, 112.50
4---Metal-impact layer 113.505...Insulating layer, 114...Contact ball 109...Channel region, 115,506...Gate electrode 116.50
1...Electrode 507 for extraction/Fist/Metal layer for wiring Applicant: Canon Co., Ltd.
Claims (1)
される配線の少なくとも一部が前記ソース領域又は箭記
ドレイン領域と同じ断面構成を持つ配線部分から成り、
かつ、前記配線部分が前記ソース領域又は前記ドレイン
領域から連続して形成されていることを特徴とする半導
体装置。At least a part of the wiring connected to the source region or drain region of the thin film top range star consists of a wiring portion having the same cross-sectional configuration as the source region or the drain region,
A semiconductor device further characterized in that the wiring portion is formed continuously from the source region or the drain region.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4281783A JPS59168673A (en) | 1983-03-15 | 1983-03-15 | Semiconductor device |
| GB08406367A GB2140203B (en) | 1983-03-15 | 1984-03-12 | Thin film transistor with wiring layer continuous with the source and drain |
| DE3448573A DE3448573C2 (en) | 1983-03-15 | 1984-03-14 | Mfg. semiconductor component with thin film transistor |
| DE3409387A DE3409387C2 (en) | 1983-03-15 | 1984-03-14 | Semiconductor device |
| US08/286,989 US5485020A (en) | 1983-03-15 | 1994-08-08 | Semiconductor device including a thin film transistor and a wiring portion having the same layered structure as and being integral with a source region or drain region of the transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4281783A JPS59168673A (en) | 1983-03-15 | 1983-03-15 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59168673A true JPS59168673A (en) | 1984-09-22 |
Family
ID=12646497
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4281783A Pending JPS59168673A (en) | 1983-03-15 | 1983-03-15 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59168673A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6151972A (en) * | 1984-08-22 | 1986-03-14 | Matsushita Electric Ind Co Ltd | Thin film transistor array and manufacture thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56135968A (en) * | 1980-03-27 | 1981-10-23 | Canon Inc | Amorphous silicon thin film transistor and manufacture thereof |
| JPS5828870A (en) * | 1981-08-12 | 1983-02-19 | Toshiba Corp | Thin film semiconductor device |
-
1983
- 1983-03-15 JP JP4281783A patent/JPS59168673A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56135968A (en) * | 1980-03-27 | 1981-10-23 | Canon Inc | Amorphous silicon thin film transistor and manufacture thereof |
| JPS5828870A (en) * | 1981-08-12 | 1983-02-19 | Toshiba Corp | Thin film semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6151972A (en) * | 1984-08-22 | 1986-03-14 | Matsushita Electric Ind Co Ltd | Thin film transistor array and manufacture thereof |
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