JPH0417370A - Thin-film transistor - Google Patents
Thin-film transistorInfo
- Publication number
- JPH0417370A JPH0417370A JP12149390A JP12149390A JPH0417370A JP H0417370 A JPH0417370 A JP H0417370A JP 12149390 A JP12149390 A JP 12149390A JP 12149390 A JP12149390 A JP 12149390A JP H0417370 A JPH0417370 A JP H0417370A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- insulating film
- film transistor
- thin film
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 25
- 239000010408 film Substances 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 4
- 229920005591 polysilicon Polymers 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 7
- 230000010354 integration Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Landscapes
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】 以下の順序に従って本発明を説明する。[Detailed description of the invention] The present invention will be described in the following order.
Ａ、産業上の利用分野
Ｂ０発明の概要
Ｃ１従来技術
り１発明が解決しようとする問題点
（Ａ、産業上の利用分野）
本発明は薄膜トランジスタ、特に集積度の向上を図りつ
つ充分な長さのチャンネル長を得ることができる薄膜ト
ランジスタに関する。A. Industrial field of application B0 Summary of the invention C1 Prior art 1 Problems to be solved by the invention (A. Industrial field of application) This invention relates to a thin film transistor that can obtain a channel length of .
（Ｂ、発明の概要）
本発明は、薄膜トランジスタにおいて、サイズの微細化
を図りつつ充分な長さのチャンネル長を得ることができ
るようにするため、ゲート電極を厚くして活性層のゲー
ト絶縁膜垂直部分と接する垂直部分にもチャンネルが生
じるようにしたものである。(B. Summary of the Invention) In order to obtain a sufficiently long channel length while reducing the size of a thin film transistor in a thin film transistor, the present invention aims to increase the thickness of the gate electrode and increase the thickness of the gate insulating layer of the active layer. Channels are also created in vertical portions that are in contact with vertical portions.
（Ｃ，従来技術）
近年、薄膜トランジスタのＬＳＩ等への応用が期待され
、チャンネル長の短かい多結晶シリコンによる薄膜トラ
ンジスタの必要性が高くなっている。ところで、従来の
薄膜トランジスタはゲート電極上にゲート絶縁膜を介し
て活性層のチャンネル領域が位置するようにした単純な
平面構造のものが多かった。(C, Prior Art) In recent years, applications of thin film transistors to LSIs and the like have been expected, and the need for thin film transistors made of polycrystalline silicon with short channel lengths has increased. Incidentally, many conventional thin film transistors have a simple planar structure in which a channel region of an active layer is located on a gate electrode with a gate insulating film interposed therebetween.
（Ｄ、発明が解決しようとする問題点）ＬＳＩの集積度
の向上に伴いチャンネル長は益々短（なる傾向にあるが
、多結晶シリコンにより形成した薄膜トランジスタはチ
ャンネル長が１μｍ以下になるとショートチャンネル効
果が強くなるので、薄膜トランジスタのチャンネル長を
短くすることに限界がある。しかし、従来の薄膜トラン
ジスタは単純な平面構造であったのでチャンネル長を短
くできなければそれ以上集積度を上げることができなか
った。(D. Problem to be solved by the invention) As the degree of integration of LSI increases, the channel length becomes shorter and shorter (it tends to become shorter), but when the channel length of thin film transistors made of polycrystalline silicon becomes 1 μm or less, the short channel effect occurs. As the channel length becomes stronger, there is a limit to how short the channel length of a thin film transistor can be.However, since conventional thin film transistors had a simple planar structure, it was impossible to further increase the degree of integration unless the channel length could be shortened. .
本発明はこのような問題点を解決すべく為されたもので
あり、サイズを小さくしつつ充分な長さのチャンネル長
を得ることができるようにすることを目的とする。The present invention was made to solve these problems, and an object of the present invention is to make it possible to obtain a sufficient channel length while reducing the size.
（Ｅ、問題点を解決するための手段）
本発明薄膜トランジスタは上記問題点を解決するため、
ゲート電極を厚（して活性層のゲート絶縁膜垂直部分と
接する垂直部分にもチャンネルが生じるようにしたこと
を特徴とする。(E. Means for Solving the Problems) In order to solve the above problems, the thin film transistor of the present invention has the following features:
A feature is that the gate electrode is made thick so that a channel is also formed in the vertical portion of the active layer that contacts the vertical portion of the gate insulating film.
（Ｆ、作用）
本発明薄膜トランジスタによれば、ゲート電極を厚くす
ることにより薄膜トランジスタの占有面積を広（するこ
とな（チャンネル長を長くすることができる。従って、
微細化を図りつつ充分な長さのチャンネルを得ることが
でき、延いてはショートチャンネル効果が生じないよう
にすることができる。(F. Effect) According to the thin film transistor of the present invention, by increasing the thickness of the gate electrode, the channel length can be increased without increasing the area occupied by the thin film transistor.
It is possible to obtain a channel of sufficient length while achieving miniaturization, and as a result, it is possible to prevent the short channel effect from occurring.
（Ｇ、実施例）［第１図］
以下、本発明薄膜トランジスタを図示実施例に従って詳
細に説明する。(G. Embodiment) [FIG. 1] The thin film transistor of the present invention will be described in detail below according to the illustrated embodiment.
第１図は本発明薄膜トランジスタの一つの実施例を示す
断面図である。同図において、１はＳｉｎ、からなる絶
縁基板（又は絶縁膜）、２は該絶縁基板（又は絶縁膜）
ｌの表面に形成されたゲート電極で、例えば４０００人
程度０膜厚を有する。３は該ゲート電極２の表面に形成
されたゲート絶縁膜で、３００〜４００人の膜厚を有す
る。該ゲート絶縁膜３はゲート電極２の表面全体を取り
囲むようにフォトリングラフィ工程を用いてバターニン
グすることにより形成されており、３ａ、３ａはゲート
絶縁膜３のゲート電極２側壁にあたる垂直部分であり、
この垂直部分もゲート電極２の上面を覆う部分と略同じ
厚さになるようにすることが好ましい。FIG. 1 is a sectional view showing one embodiment of the thin film transistor of the present invention. In the figure, 1 is an insulating substrate (or insulating film) made of Sin, and 2 is the insulating substrate (or insulating film).
The gate electrode is formed on the surface of the gate electrode and has a film thickness of about 4,000, for example. Reference numeral 3 denotes a gate insulating film formed on the surface of the gate electrode 2, and has a thickness of 300 to 400 nm. The gate insulating film 3 is formed by patterning using a photolithography process so as to surround the entire surface of the gate electrode 2, and 3a, 3a are vertical portions of the gate insulating film 3 corresponding to the side walls of the gate electrode 2. can be,
Preferably, this vertical portion also has approximately the same thickness as the portion covering the upper surface of the gate electrode 2.
４は膜厚が約３００人の多結晶シリコンからなる活性層
で、ゲート絶縁膜３の表面及び絶縁基板１表面を覆うよ
うに形成されている。４ａ、４ａは活性層４の垂直部分
である。５．６は該活性層４にフォトリングラフィ技術
を駆使した不純物の選択的イオン打込み及び活性化アニ
ールにより形成されたソース、ドレインである。Reference numeral 4 denotes an active layer made of polycrystalline silicon having a thickness of approximately 300 nm, and is formed to cover the surface of the gate insulating film 3 and the surface of the insulating substrate 1. 4a, 4a are vertical portions of the active layer 4. Reference numerals 5 and 6 designate a source and a drain formed in the active layer 4 by selective ion implantation of impurities and activation annealing using photolithography technology.
この薄膜トランジスタのソース・ドレイン間の間隔は０
．５〜０．７μｍときわめて短かいが、活性層４のゲー
ト絶縁膜３の垂直部分の側壁にあたる垂直部分４ａ、４
ａもチャンネルとなるので、実効的チャンネル長をショ
ートチャンネル効果の生じる虞れのない１．０μｍ以上
の長さ、例えば１．４μｍにすることができる。The distance between the source and drain of this thin film transistor is 0
．． The vertical portions 4a, 4, which correspond to the side walls of the vertical portion of the gate insulating film 3 of the active layer 4, are extremely short at 5 to 0.7 μm.
Since a also serves as a channel, the effective channel length can be set to 1.0 μm or more, for example 1.4 μm, without causing the short channel effect.
従って、薄膜トランジスタの占有面積を狭（しつつチャ
ンネル長をショートチャンネル効果を生じないような長
さにすることが可能になる。即ち、ショートチャンネル
効果の生じる虞れなく薄膜トランジスタを形成したＬＳ
Ｉの集積度の向上を図ることができる。Therefore, it is possible to reduce the area occupied by the thin film transistor while making the channel length to a length that does not cause the short channel effect. In other words, it is possible to reduce the area occupied by the thin film transistor and to make the channel length such that the short channel effect does not occur.
It is possible to improve the degree of integration of I.
（Ｈ，発明の効果）
以上に述べたように、本発明薄膜トランジスタは、絶縁
基板あるいは絶縁膜上にゲート絶縁膜よりも相当に厚い
ゲート電極を形成し、該ゲート電極の側面を覆う垂直部
分を有するゲート絶縁膜をゲート電極表面に形成し、上
記ゲート絶縁膜の表面にその垂直部分に接する垂直部分
を有する活性層を形成してなることを特徴とするもので
ある。(H, Effect of the Invention) As described above, the thin film transistor of the present invention has a gate electrode formed on an insulating substrate or an insulating film, which is considerably thicker than the gate insulating film, and a vertical portion covering the side surfaces of the gate electrode. A gate insulating film having the above structure is formed on the surface of the gate electrode, and an active layer having a vertical portion in contact with the vertical portion of the gate insulating film is formed on the surface of the gate insulating film.
従って、本発明薄膜トランジスタによれば、ゲート電極
を厚くすることにより薄膜トランジスタの占有面積を広
くすることなくチャンネル長を長くすることができる。Therefore, according to the thin film transistor of the present invention, by increasing the thickness of the gate electrode, the channel length can be increased without increasing the area occupied by the thin film transistor.
従って、サイズを小さ（しつつ充分な長さのチャンネル
長を得ることができる。Therefore, it is possible to obtain a sufficiently long channel length while keeping the size small.
【図面の簡単な説明】
第１図は本発明薄膜トランジスタの一つの実施例を示す
断面図である。
符号の説明
ｌ・・・絶縁基板、２・・・ゲート電極、３・・・ゲー
ト絶縁膜、
３ａ・・・ゲート絶縁膜の垂直部分、
４・・・活性層、４ａ・・・・・・活性層の垂直部分、
５．６・・・ソース、ドレイン。
・絶縁基板
活性層
・ソース
ドレイン
活１（垂直部か
実施有りを示すＦＴ面図
第１図BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view showing one embodiment of the thin film transistor of the present invention. Explanation of symbols 1... Insulating substrate, 2... Gate electrode, 3... Gate insulating film, 3a... Vertical portion of gate insulating film, 4... Active layer, 4a... vertical part of the active layer,
5.6...source, drain.・Insulating substrate active layer ・Source/drain active layer 1 (FT side view showing vertical part or implementation) Figure 1
Claims (1)
相当に厚いゲート電極を形成し、上記ゲート電極の側面
を覆う垂直部分を有するゲート絶縁膜をゲート電極表面
に形成し、上記ゲート絶縁膜の表面にこの垂直部分に接
する垂直部分を有する活性層を形成してなることを特徴
とする薄膜トランジスタ(1) Forming a gate electrode considerably thicker than the gate insulating film on an insulating substrate or insulating film, forming a gate insulating film having a vertical portion covering the side surfaces of the gate electrode on the surface of the gate electrode, and forming the gate insulating film on the surface of the gate electrode. A thin film transistor characterized in that an active layer having a vertical portion in contact with the vertical portion is formed on the surface of the thin film transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12149390A JPH0417370A (en) | 1990-05-11 | 1990-05-11 | Thin-film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12149390A JPH0417370A (en) | 1990-05-11 | 1990-05-11 | Thin-film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0417370A true JPH0417370A (en) | 1992-01-22 |
Family
ID=14812532
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12149390A Pending JPH0417370A (en) | 1990-05-11 | 1990-05-11 | Thin-film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0417370A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5393992A (en) * | 1991-12-28 | 1995-02-28 | Nec Corporation | Semiconductor thin film transistor with gate controlled offset portion |
| JP2012191185A (en) * | 2011-02-24 | 2012-10-04 | Semiconductor Energy Lab Co Ltd | Semiconductor device and manufacturing method for semiconductor device |
| JP2012199534A (en) * | 2011-03-08 | 2012-10-18 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
-
1990
- 1990-05-11 JP JP12149390A patent/JPH0417370A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5393992A (en) * | 1991-12-28 | 1995-02-28 | Nec Corporation | Semiconductor thin film transistor with gate controlled offset portion |
| JP2012191185A (en) * | 2011-02-24 | 2012-10-04 | Semiconductor Energy Lab Co Ltd | Semiconductor device and manufacturing method for semiconductor device |
| JP2012199534A (en) * | 2011-03-08 | 2012-10-18 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
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