JPS59163974U - Abnormal characteristic detection circuit - Google Patents
Abnormal characteristic detection circuitInfo
- Publication number
- JPS59163974U JPS59163974U JP5845883U JP5845883U JPS59163974U JP S59163974 U JPS59163974 U JP S59163974U JP 5845883 U JP5845883 U JP 5845883U JP 5845883 U JP5845883 U JP 5845883U JP S59163974 U JPS59163974 U JP S59163974U
- Authority
- JP
- Japan
- Prior art keywords
- input terminal
- terminal
- circuit
- comparator
- output terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の一実施例。第２図ａ−ｃは被試験物と
その入力信号及び入出力電圧特性の一例。
第３図は入出力特性にゆらぎがある場合の図。第４図は
ゆらぎの許容値を示す図。第５図ａ ”− ｃは本考案
の動作原理を示すタイミングチャートを示す。
なお、図において、１は信号入力端子、２は可変遅延回
路、３は差動増幅器、４は基準電源、５はコンパレータ
、６は２人カアンドゲート、７はトリガ入力端子、８は
第２トリガー検出記憶部、９はフリップフロップである
。Figure 1 shows an embodiment of the present invention. Figures 2a to 2c show examples of the test object, its input signal, and input/output voltage characteristics. Figure 3 is a diagram when there is fluctuation in the input/output characteristics. FIG. 4 is a diagram showing the permissible value of fluctuation. Figures 5a to 5c show timing charts showing the operating principle of the present invention. In the figures, 1 is a signal input terminal, 2 is a variable delay circuit, 3 is a differential amplifier, 4 is a reference power supply, and 5 is a A comparator, 6 a two-man AND gate, 7 a trigger input terminal, 8 a second trigger detection storage section, and 9 a flip-flop.
Claims (1)
パレータと２人カアンド回路とトリガー入力端子と第２
トリガー検出記憶部とフリップフロップとから構成され
、前記信号入力端子を前記差動増幅器の一方の入力端子
及び前記遅延回路の入力端子にそれぞれ接続し、前記遅
延回路の出力端子と前記差動増幅器の他方の入力端子と
を接続し、前記差動増幅器の出力端子を前記コンパレー
タの一方の入力端子へ接続し、他方の入力端子を前記基
準電源と接続し、前記コンパレータの出力端子を、前記
２人カアンド回路の一方のゲートへ接続し、前記トリガ
ー入力端子と前記第２トリガー検出記憶部の入力端子を
接続し、この第２トリガー検出記憶部の出力端子と前記
２人カアンド回路の他方の入力端子とを接続し、前記２
人カアンド回路の出力端子を前記フリップフロップのセ
ット端子と接続した事を特徴とする特許 路。[Claims for Utility Model Registration] A signal input terminal, a delay circuit, a differential amplifier, a reference power supply, a comparator, a two-man AND circuit, a trigger input terminal, and a second
The signal input terminal is connected to one input terminal of the differential amplifier and the input terminal of the delay circuit, and the output terminal of the delay circuit and the input terminal of the differential amplifier are connected to each other. The output terminal of the differential amplifier is connected to one input terminal of the comparator, the other input terminal is connected to the reference power supply, and the output terminal of the comparator is connected to the output terminal of the comparator. the trigger input terminal and the input terminal of the second trigger detection storage section, and the output terminal of the second trigger detection storage section and the other input terminal of the two-person AND circuit. and connect the above 2
The patented circuit is characterized in that the output terminal of the human AND circuit is connected to the set terminal of the flip-flop.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5845883U JPS59163974U (en) | 1983-04-19 | 1983-04-19 | Abnormal characteristic detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5845883U JPS59163974U (en) | 1983-04-19 | 1983-04-19 | Abnormal characteristic detection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59163974U true JPS59163974U (en) | 1984-11-02 |
Family
ID=30188737
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5845883U Pending JPS59163974U (en) | 1983-04-19 | 1983-04-19 | Abnormal characteristic detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59163974U (en) |
-
1983
- 1983-04-19 JP JP5845883U patent/JPS59163974U/en active Pending
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