JPS5915382B2 - Gate oxide film quality evaluation method - Google Patents

Description

【発明の詳細な説明】 この発明はＭＯＳ（Ｍｅｔａｌ−Ｏｘｉｄｅ−Ｓｅｍ−
ｉｃｏｍｌｕｃｔｏｒ型半導体素子に用いられるゲート
酸化膜の膜質評価法に係る。DETAILED DESCRIPTION OF THE INVENTION This invention relates to MOS (Metal-Oxide-Sem-
The present invention relates to a method for evaluating the quality of a gate oxide film used in an icomulctor type semiconductor device.

ＭＯＳ型半導体素子においてゲート酸化膜は最も重要な
構成部分のひとつであつて無欠陥のものが要求される。The gate oxide film is one of the most important constituent parts in a MOS type semiconductor device, and is required to be defect-free.

例えばＮａイオンのごとき不純物がゲート酸化膜中に存
在すれば、ＭＯＳＩ・ランジスタのしきいＩＥ電圧を変
化、変動させる欠陥となク、ピンホールや局所的に膜厚
の薄いところがあれば、漏洩電流の発生や耐圧不良の欠
陥となる。したがつてＭＯＳ型半導体素子を高歩留ク。
高信頼性で製造するためには、ゲート酸化膜中におけ５
るこれら欠陥を絶無としなければならない。そしてこ
れら欠陥の軽減、絶無を図るには、ゲート酸化膜の成膜
技術の向上を必要とするが、そのためには、成膜技術の
現状レベルや改善効果を把握する適切なゲート酸化膜の
膜質評価法を要する。１０こうしたゲート酸化膜の膜質
評価法として、従来つぎのような方法が用いられている
。For example, if impurities such as Na ions exist in the gate oxide film, they can cause defects that change or fluctuate the threshold IE voltage of MOSI/transistors, and if there are pinholes or locally thin areas, leakage current may occur. This can lead to defects such as the occurrence of damage or poor voltage resistance. Therefore, the yield of MOS type semiconductor devices is high.
In order to manufacture with high reliability, it is necessary to
These deficiencies must be eradicated. In order to reduce or eliminate these defects, it is necessary to improve the gate oxide film deposition technology, but in order to do so, it is necessary to understand the current level of the film deposition technology and the effects of improvement, and to determine the appropriate gate oxide film quality. Evaluation method is required. 10 As a method for evaluating the film quality of such a gate oxide film, the following method has been conventionally used.

すなわち、Ｎａイオンのごとき可動性イオンによるしき
、い値電圧変動をもたらす種類の欠陥に対しては、公知
のＣ−Ｖ（Ｃａｐａｃｉｔａｎｃｅ−Ｖｏｌｔａｇｅ評
価法が用１５いられる。この方法は、ゲート酸化膜にＡ
ｔ電極等のゲート電極を設けたＭＯＳ構造のキャパシタ
を高温にして、Ｓｉ基板等の半導体基板とゲート電極の
間に直流電圧を印加、変化させて、その間の静電容２０
量の変化からゲート酸化膜の膜質を評価するものである
。That is, for defects of the type that cause threshold voltage fluctuations due to mobile ions such as Na ions, the well-known C-V (capacitance-voltage evaluation method)15 is used. niA
A MOS structure capacitor equipped with a gate electrode such as a t-electrode is heated to a high temperature, and a DC voltage is applied and varied between a semiconductor substrate such as a Si substrate and the gate electrode to increase the electrostatic capacitance 20 therebetween.
The film quality of the gate oxide film is evaluated based on changes in the amount.

一方ピンホールや局所的薄膜箇所による漏洩電流や耐圧
不良をもたらす種類の欠陥に対しては、液晶の動的散乱
効果を応用する評価法が好適である。２５この方法はＭ
ＯＳキャパシタの上にネマチツク液晶膜、透明導電膜を
順次載置したのち、半導体基板と透明導電膜の間に直流
電圧を印加しながらゲート電極を観祭すれば、漏洩電流
や耐圧不良の欠陥のあるゲート酸化膜上のゲート電極が
液晶の３０動的散乱効果により外部光のもとで白く輝く
ため欠陥を検出できる評価法である。On the other hand, an evaluation method that applies the dynamic scattering effect of liquid crystal is suitable for defects that cause leakage current or breakdown voltage failure due to pinholes or local thin film locations. 25 This method is M
After sequentially placing a nematic liquid crystal film and a transparent conductive film on an OS capacitor, observing the gate electrode while applying a DC voltage between the semiconductor substrate and the transparent conductive film can detect defects such as leakage current and breakdown voltage failure. This is an evaluation method that can detect defects because the gate electrode on a certain gate oxide film shines white under external light due to the dynamic scattering effect of liquid crystal.

従来におけるゲート酸化膜の膜質評価法は、上記の２方
法を用いていたが次のような欠点を有していた。Conventional methods for evaluating the quality of gate oxide films use the above two methods, but they have the following drawbacks.

すなわちＣ−Ｖ評価法は各ゲート電極へあ の探針によ
る電気的接続を要するので微小な寸法のゲート電極を用
いことができないのに対し、液晶法は探針不要のため微
小な寸法のゲート電極を採用できるものの、ピンホール
のような局所的欠陥を検出するためには微小寸法の電極
を用いる必要がある。In other words, the C-V evaluation method requires electrical connection to each gate electrode using a probe, so it cannot use gate electrodes with minute dimensions, whereas the liquid crystal method does not require a probe, so it cannot use gate electrodes with minute dimensions. Although electrodes can be used, it is necessary to use microscopic electrodes to detect local defects such as pinholes.

したがつて、従来は、ゲート電極寸法の異なる２種類の
評価試料を準備しなければならなかつた。そのため、少
なくとも２個の評価原料を必要とし、また同一試料でな
いためＣ−評価法と液晶法の評価結果の相関、関連につ
いて凝義を生じる欠点があつた。本発明によるゲート酸
化膜の膜質評価法は、半導体基板に形成したゲート酸化
膜上に寸法の異なるゲート電極を形成することで従来の
欠点を除去しようとするものである。Therefore, conventionally, it was necessary to prepare two types of evaluation samples with different gate electrode dimensions. Therefore, at least two raw materials for evaluation are required, and since the samples are not the same, there is a drawback that the correlation and relationship between the evaluation results of the C-evaluation method and the liquid crystal method are difficult to define. The method for evaluating the film quality of a gate oxide film according to the present invention attempts to eliminate the drawbacks of the conventional method by forming gate electrodes with different dimensions on a gate oxide film formed on a semiconductor substrate.

以下、図面を参照しながら、本発明について説明するこ
とにする。The present invention will be described below with reference to the drawings.

第１図Ａ，ｂは、本発明の方法を適用した一実施例の評
価試料の平面図と断面図を示す。FIGS. 1A and 1B show a plan view and a sectional view of an evaluation sample of an example to which the method of the present invention is applied.

図に訃いてＳ，ウエハ等の半導体基板ウエハ１の主面１
ａＶＣＳｉ０２膜等のゲート酸化膜２が形成されて卦ジ
、ゲート酸化膜２の上にはＡｔ電極等のＣ−Ｖ評価用ゲ
ート電極３卦よび液晶評価用ゲート電極４が形成されて
いる。Ｃ−Ｖ評価用ゲート電極３の寸法は、液晶評価用
ゲート電極４の寸法よジ大きく、電気的接続のための探
針５を確状に接触させ得る大きさの寸法としている。一
方、液晶評価用ゲート電極４の寸法は、肉眼で見える最
小の寸法としている。また図では、Ｃ−Ｖ評価用ゲート
電極３は半導体基板ウエハ１の中央部卦よび周辺４箇所
に詳落状に散在させてあり、液晶評価用ゲート電極４は
Ｃ−Ｖ評価用ゲート電極３群の間へ稠密に配置させてあ
る。第２図は、第１図に示した評価試料１００に対する
Ｃ−評価法の適用状態を示す断面図である。As shown in the figure, S is the main surface 1 of a semiconductor substrate wafer 1 such as a wafer.
A gate oxide film 2 such as an aVCSi02 film is formed, and on the gate oxide film 2, a gate electrode 3 for CV evaluation such as an At electrode and a gate electrode 4 for liquid crystal evaluation are formed. The dimensions of the gate electrode 3 for CV evaluation are larger than the dimensions of the gate electrode 4 for liquid crystal evaluation, and are large enough to allow a probe 5 for electrical connection to be brought into precise contact with it. On the other hand, the dimensions of the gate electrode 4 for liquid crystal evaluation are the minimum dimensions visible to the naked eye. In addition, in the figure, the gate electrodes 3 for CV evaluation are scattered in a detailed pattern at the center and four locations around the semiconductor substrate wafer 1, and the gate electrodes 4 for liquid crystal evaluation are the gate electrodes 3 for CV evaluation. They are arranged densely between the groups. FIG. 2 is a cross-sectional view showing how the C-evaluation method is applied to the evaluation sample 100 shown in FIG.

図において探針５をＣ−評価用ゲート電極３に接触させ
、半導体基板ウエハ１とＣ−Ｖ評価用ゲート電極３の間
に電圧可変型直流電源６訃よび静電容量計７を接続する
。評価試料１００は加熱器８で所定の温度まで昇温した
のち、電圧可変型直流電源６の電圧を印加、変化させつ
つ、静電容最計７によりＣ−Ｖ評価用ゲート電極３と半
導体基板ウエハ１との間の静電容量Ｃを測定し、Ｃ一Ｖ
の変化関係からゲート酸膜膜２の膜質を評価する。この
Ｃ−Ｖ評価法は従来と同じ方法である。だが本発明の方
法では、このＣ−評価の適用後、その評価試料１００に
対して次に液晶による評価を継続して行う。第３図Ａ，
ｂは第１図に示した評価試料１００に対する液晶法の適
用状態を示す断面図と平面図である。In the figure, the probe 5 is brought into contact with the gate electrode 3 for C-evaluation, and a variable voltage DC power source 6 and a capacitance meter 7 are connected between the semiconductor substrate wafer 1 and the gate electrode 3 for C-V evaluation. After heating the evaluation sample 100 to a predetermined temperature with the heater 8, while applying and changing the voltage of the variable voltage DC power supply 6, the gate electrode 3 for CV evaluation and the semiconductor substrate wafer are heated by the capacitance 7 at maximum. 1 and measure the capacitance C between C and V.
The film quality of the gate oxide film 2 is evaluated based on the relationship of changes in . This CV evaluation method is the same as the conventional method. However, in the method of the present invention, after applying this C-evaluation, the evaluation sample 100 is then continuously evaluated using a liquid crystal. Figure 3A,
b is a sectional view and a plan view showing how the liquid crystal method is applied to the evaluation sample 100 shown in FIG. 1;

図に卦いて少なくとも液晶評価用ゲート電極４の上にネ
マチツク液晶膜９を形成し、さらにネマチツク液晶膜９
の上に透明導電膜１０を載置する。しかるのち透明導電
膜１０と半導体基板ウエハ１の間に可変型直流電源６を
接続して電圧を印加する。もしゲート酸化膜２の中にピ
ンホールや耐圧不良の欠陥１１があれば、その上の液晶
評価用ゲート電極４が白く輝くことは前に述べた通ｖで
ある。第３図は白く輝く光散乱ゲート電極４１が半導体
基板ウエハ１の面上で分布している例を示している。こ
こで印加電圧を変化させることによう半導体基板ウエ・
・１の全面にわたるゲート酸化膜２の膜質分布の電圧依
存性を観測できる。以上詳しく述べた本発明によるゲー
ト酸化膜の膜質評価法は次のような効果を有する。すな
わち、１）Ｃ−Ｖ評価と液晶による評価を同じ評価試料
に適用でき、試料数が少なくてすむうえ、両者の評価結
果の相関、関連に卦ける疑義の生じる余地が極めて少な
い。また２）Ｃ−Ｖ評価と液晶による評価は寸法の異な
るそれぞれのゲート電極に着目するゆえ、たとえＣ−Ｖ
評価のときの印加電圧によつてＣ−Ｖ評価用ゲート電極
３の下のゲート酸化膜２が破壊されたとしても、ゲート
電極の寸法が異なるので液晶による評価と識別でき、両
者の評価を向じ評価試料１００で独立して行うことがで
きる。なお図面で示した実施例に訃いては、ゲート電極
形状を正方形としているが円形でもよい。As shown in the figure, a nematic liquid crystal film 9 is formed at least on the gate electrode 4 for liquid crystal evaluation, and a nematic liquid crystal film 9 is further formed on the gate electrode 4 for liquid crystal evaluation.
A transparent conductive film 10 is placed thereon. Thereafter, a variable DC power source 6 is connected between the transparent conductive film 10 and the semiconductor substrate wafer 1 to apply a voltage. As mentioned above, if there is a defect 11 such as a pinhole or defect 11 due to poor breakdown voltage in the gate oxide film 2, the gate electrode 4 for liquid crystal evaluation above it will shine white. FIG. 3 shows an example in which white light scattering gate electrodes 41 are distributed on the surface of the semiconductor substrate wafer 1. As shown in FIG. Here, by changing the applied voltage, the semiconductor substrate wafer
・The voltage dependence of the film quality distribution of the gate oxide film 2 over the entire surface of the gate oxide film 2 can be observed. The gate oxide film quality evaluation method according to the present invention described in detail above has the following effects. That is, 1) CV evaluation and liquid crystal evaluation can be applied to the same evaluation sample, the number of samples is small, and there is very little room for doubts regarding the correlation or relationship between the two evaluation results. 2) Since C-V evaluation and liquid crystal evaluation focus on gate electrodes with different dimensions, even if C-V
Even if the gate oxide film 2 under the gate electrode 3 for CV evaluation is destroyed by the applied voltage during evaluation, the dimensions of the gate electrode are different, so it can be distinguished from the evaluation using liquid crystal, and it is possible to improve the evaluation of both. It can be performed independently using the same evaluation sample 100. In the embodiment shown in the drawings, the shape of the gate electrode is square, but it may also be circular.

また、Ｃ−Ｖ評価用電極３の配置を第１図ａで示した５
箇所でなく、それと異なつた箇所数、配置・位置に設け
てもよい。Ｃ−Ｖ評価は探針を必要とし、評価所要時間
が比較的長いので、一般にＣ−評価用ゲート電極３の数
は少なく用いられている。したがつて粗に散在させたＣ
−Ｖ評価用ゲート電極３群の間へ、液晶評価用ゲート電
極４を密に形成した評価試料とすればよい。ゲート電極
３，４のゲート酸化膜２上への形成は、ゲート酸化膜２
の全面にＡｔ等のゲート金属を真空蒸着したのち、公知
の写真食刻技術により所望のゲート電極３，４の部分の
みを残す方法によつて行えるが、ゲート電極３，４の形
状寸法、配置の開孔を有する薄い金属板をゲート酸化膜
２と蒸着源（図示せず）との間に介在させて真空蒸着す
ることにより容易にゲート電極３，４を形成することも
できる。In addition, the arrangement of the CV evaluation electrode 3 is as shown in FIG. 1a.
They may be provided in a different number of locations, arrangement, or position instead of at a specific location. Since CV evaluation requires a probe and the time required for evaluation is relatively long, generally a small number of gate electrodes 3 for C-evaluation are used. Therefore, the coarsely scattered C
An evaluation sample may be prepared in which gate electrodes 4 for liquid crystal evaluation are formed densely between three groups of gate electrodes for -V evaluation. The gate electrodes 3 and 4 are formed on the gate oxide film 2.
This can be done by vacuum-depositing a gate metal such as At on the entire surface of the gate electrode, and then leaving only the desired portions of the gate electrodes 3 and 4 using a known photolithography technique. The gate electrodes 3 and 4 can also be easily formed by interposing a thin metal plate having openings between the gate oxide film 2 and a deposition source (not shown) and performing vacuum deposition.

以上詳しく述べたように本発明によるゲート酸化膜の膜
質評価法によれば、ゲート酸化膜の膜質を同じ試料を用
いてＣ−Ｖ評価卦よび液晶による評価を連続して行うこ
とができ、精密かつ豊富な情報が得られ、良質のゲート
酸化膜を形成するため成膜技術の向上に没立ち、ひいて
は高歩留り、高信頼性のＭＯＳ型半導体素子の製造を期
待できる。As described in detail above, according to the film quality evaluation method of the gate oxide film according to the present invention, the film quality of the gate oxide film can be continuously evaluated by C-V evaluation and liquid crystal evaluation using the same sample. Moreover, a wealth of information can be obtained, and it is possible to improve the film-forming technology to form a high-quality gate oxide film, which in turn can be expected to lead to the production of high-yield, highly reliable MOS type semiconductor devices.

【図面の簡単な説明】 第１図Ａ，ｂは本発明を適用した一実施例の評価試料の
平面図と断面図、第２図は第１図実施例の評価試料に対
するＣ−評価の適用状態を説明するため（ハ）新面図、
第３図Ａ，ｂは第１図実施例の評価試料に対する液晶に
よる評価の適用状態を説明するための断面図と平面図で
ある。 １は半導体基板ウエハ、２はゲート酸化膜、３はＣ−Ｖ
評価用ゲート電極、４は液晶評価用ゲート電極、５は探
針、６は可変型直流電源、７は静電容験計、８は加熱器
、９はネマチツク液晶膜、１０は透明導電膜、１００は
評価試料である。[Brief Description of the Drawings] Figures 1A and b are a plan view and a sectional view of an evaluation sample of an embodiment to which the present invention is applied, and Figure 2 is an application of C-rating to the evaluation sample of the embodiment in Figure 1. (c) New view to explain the condition;
FIGS. 3A and 3B are a cross-sectional view and a plan view for explaining how evaluation using a liquid crystal is applied to the evaluation sample of the embodiment shown in FIG. 1 is a semiconductor substrate wafer, 2 is a gate oxide film, 3 is a C-V
Gate electrode for evaluation, 4 is a gate electrode for liquid crystal evaluation, 5 is a probe, 6 is a variable DC power supply, 7 is a capacitance meter, 8 is a heater, 9 is a nematic liquid crystal film, 10 is a transparent conductive film, 100 is the evaluation sample.

Claims (1)

【特許請求の範囲】[Claims] １ ＭＯＳ型半導体素子に用いられるゲート酸化膜の膜
質評価法において、半導体基板ウェハ主面の全面に形成
されたゲート酸化膜の上に、Ｃ−Ｖ評価用ゲート電極を
所定位置に散在せしめ、上記電極より多数で小寸法の液
晶評価用ゲート電極をＣ−Ｖ評価用ゲート電極の群落の
間へ稠密に散在せしめて評価用試料となしたのち、Ｃ−
Ｖ評価用ゲート電極によるＣ−Ｖ評価と、液晶評価用ゲ
ート電極に着目したネマチツク液晶の働的散乱効果を応
用せる液晶評価を、同一評価用試料を用いて順次行うこ
とを特徴とするゲート酸化膜の膜質評価法。1. In a method for evaluating the film quality of a gate oxide film used in a MOS type semiconductor device, gate electrodes for CV evaluation are scattered at predetermined positions on a gate oxide film formed on the entire main surface of a semiconductor substrate wafer, and the method described above is performed. Gate electrodes for liquid crystal evaluation, which are larger in number than the electrodes and smaller in size, are densely scattered between the clusters of gate electrodes for C-V evaluation to form an evaluation sample.
Gate oxidation characterized in that C-V evaluation using a gate electrode for V evaluation and liquid crystal evaluation that applies the active scattering effect of nematic liquid crystal focusing on a gate electrode for liquid crystal evaluation are performed sequentially using the same evaluation sample. Membrane quality evaluation method.