JPS59136931A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS59136931A
JPS59136931A JP1182283A JP1182283A JPS59136931A JP S59136931 A JPS59136931 A JP S59136931A JP 1182283 A JP1182283 A JP 1182283A JP 1182283 A JP1182283 A JP 1182283A JP S59136931 A JPS59136931 A JP S59136931A
Authority
JP
Japan
Prior art keywords
resist
film
etching
thin film
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1182283A
Other languages
Japanese (ja)
Inventor
Noboru Kudo
昇 工藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP1182283A priority Critical patent/JPS59136931A/en
Publication of JPS59136931A publication Critical patent/JPS59136931A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To enable to form easily an etching mask easily removable even after irradiation of plasma by a method wherein a first thin film is formed on a semiconductor substrate, and the first thin film is etched according to plasma etching using a patterned second thin film as a mask. CONSTITUTION:A poly-Si film 1 is thermally oxidized according to high temperature heat treatment in an O2 gas or a steam atmosphere to form an SiO2 film 3 on the poly-Si film 1. Then, a resist 4 is applied on the SiO2 film 3 according to the spin coating method, etc., and the resist 4 is patterned according to the resist patterning method using ultraviolet rays, for example. Then, the SiO2 film 3 is etched according to an HF etching liquid using the patterned resist 4 as an etching mask. The resist 4 is removed according to the resist removing method by the usually used mixed liquid of H2SO4 and H2O2, etc. Then, the poly-Si film 1 is etched using the SiO2 film 3 as an etching mask according to the dry etching method using plasma generated by applying a high-frequency electric field to CF4 gas, etc.

Description

【発明の詳細な説明】 本発明は、半導体装置の製造方法に係り、詳しくは、ド
ライエツチング後に除法が各易な、もしくは除法が不=
なエツチングマスク材料の容易な製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device.
The present invention relates to an easy manufacturing method for an etching mask material.

ドライエツチングは、従来広く一般に微細加工法として
用いられてきたウェットエツチングに比較して、サイド
エッチが少ないためより微細な加工に向いている、ウェ
ットエツチングでは加工が困難だった被加工材料(例え
ばS1〜5N4、Po1ysi )の加工が谷易でめる
、終点検出が谷易なため自動化しやすい、液体に′〈ら
べ気不の方が純度が高いタメよジクリーンなグロヤスに
なるなどの特徴7Mし、近年、半勇坏装置の奥積度が向
上するにつれて盛んに用いられるよりになってきた。し
かし、1だ解決すべき多くの問題点を待っている。
Compared to wet etching, which has traditionally been widely used as a microfabrication method, dry etching involves less side etching, making it suitable for finer machining. ~5N4, Polysi) can be easily processed, the end point detection is easy, so it is easy to automate, and the liquid can be made into a clean gloss with higher purity.7M However, in recent years, as the depth of the half-coat device has improved, it has come into widespread use. However, there are many problems waiting to be solved.

DJ ’F、  ドライエツチングのもつ問題点につい
て説明する。エツチングのマスク材料としては、光照射
による化学反応ヶ起こし、特定の現像液に可溶′fた(
−り不溶になるレジストか王に用いられている。ところ
で、」在、生産工程で実用化されてぃ/、、)レジスト
は′すべて有機物であり、半力坏装置製企「梶め重湯(
200〜500C以上)熱処理で分解し、黙%理装置″
fたは該半4坏装置をlケ染する問題があるため、Af
t記レジストはエツチング後、熱処理を有り前VC除去
しなければならない。ところが、有機物からなるAil
記レジストをエツチングマスクに用い、フラズマ全半導
体装餌に照射するドライエツチング加工を行うと、プラ
ズマ全照射芒れたレジストがf實し、従来、広く用いら
れてきたH2SO4とH20□ の混合溶液からなるレ
ジスト除去液では除去できないといり問題が生じた。
DJ'F explains the problems with dry etching. As an etching mask material, it is possible to cause a chemical reaction by light irradiation, and it is soluble in a specific developer (
- It is used for resists that become insoluble. By the way, the resist that is currently being put into practical use in the production process is entirely organic, and the resist that has been put into practical use in the production process is entirely organic.
200-500C or higher) decomposes by heat treatment, and silently decomposes it with a
Af
After the resist is etched, it must be heat treated and the VC must be removed. However, Ail consisting of organic matter
When the above resist is used as an etching mask and a dry etching process is performed by irradiating the entire plasma semiconductor substrate, the resist completely irradiated with plasma is produced. A problem arose in that the resist removal solution could not be removed.

不発明は、前、・への問題1r解決するためKなされた
ものであり、プラズマを照射した後でも除去が容易なエ
ツチングマスク金容易に形成する方法に関する。以下、
不発明の半導体装置の製造方法を図面に基づいて詳細に
説明する。第1図は(a)〜(g)は、本発明の半導体
装置の製造方法の一実施例を示す胡面図であり、5i0
22上に配したpo17E]i1の薄膜(第1図(a)
参#@)全CF4などのガスに局周波電界?印加してつ
くるプラズマでエツチングする場合のエツチングマスク
形成法に関する。1ず。
The present invention was made to solve the problems 1r and 2 above, and relates to a method for easily forming an etching mask that can be easily removed even after plasma irradiation. below,
An inventive method for manufacturing a semiconductor device will be explained in detail based on the drawings. FIGS. 1(a) to 1(g) are cross-sectional views showing an embodiment of the method for manufacturing a semiconductor device of the present invention, and 5i0
A thin film of po17E]i1 placed on 22 (Fig. 1(a)
Reference #@) Is there a local frequency electric field in all gases such as CF4? This invention relates to a method for forming an etching mask when etching is performed using plasma generated by application. 1s.

po178i1 k、02ガスまたは水蒸気雰囲気中で
900〜1200C1l/)両温熱処理をすることによ
υ熱酸化(7、po lys i I上に81025 
 f形成する(第1図(b)参照)。第2図は、リン全
08VCシて1019〜1020Cn1″3ドーグし7
tpO1ysii水蒸気雰囲気で熱酸化(−1た時の酸
化条件と8102膜厚の関係を表わす特性図である。前
記熱酸化前のpOlys11の膜厚を”pOlys @
記熱酸化後の5iO25の膜厚をtox  とすると、
前記熱酸化後のpolysilの膜厚はtpoly−z
toxとなる。従って、前記熱酸化工程に続く工程で、
polyeil 、 SiO□6 の膜厚全必dな厚さ
とするために、第2図全参照にして。
Thermal oxidation (7, 81025 on po lys i I
f (see FIG. 1(b)). Figure 2 shows all phosphorus 08VC, 1019~1020Cn1''3 Dogue 7
tpOlysii is a characteristic diagram showing the relationship between oxidation conditions and 8102 film thickness when thermally oxidized (-1) in a water vapor atmosphere.The film thickness of pOlys11 before thermal oxidation is "pOlys@
Letting the film thickness of 5iO25 after thermal oxidation be tox,
The film thickness of polysil after the thermal oxidation is tpoly-z
It becomes tox. Therefore, in the step following the thermal oxidation step,
To ensure that the film thicknesses of polyeil and SiO□6 are all the required thicknesses, please refer to FIG.

熱酸化条1/4=及びtpo1y全決足すればよい。次
に、レジスト4 f 5i023  の土に、スビンコ
ー)4すどの方法により塗布し、たとえば紫外線を用A
た公知のレジストバターニング方法によりレジスト4オ
バターニングする(m11図(C)参照)。次に、前N
I2 ハターニングレ1ζレジスト4をエツチングマス
クとして%HF系のエツチング液により5iO23をエ
ツチングする(第1図(a)参照)。?′Kに、レジス
ト4 (5)(2So4とF12o2  の混合液など
の通常用いらすしているレジスト除去方法により取除く
(第1図(e)参11tj )。レジスト4はプラズマ
を照射されていないので、除去は容易Vこ行なわれる。
Thermal oxidation strip 1/4= and tpo1y should be fully resolved. Next, resist 4 f 5i023 is applied to the soil using a method such as Subinko), and exposed to ultraviolet rays, for example.
The resist is patterned four times using a known resist patterning method (see Fig. m11 (C)). Next, the previous N
5iO23 is etched with a HF-based etching solution using the I2 patterning layer 1ζ resist 4 as an etching mask (see FIG. 1(a)). ? 'K, resist 4 (5) is removed by a commonly used resist removal method such as a mixture of 2So4 and F12o2 (see Figure 1(e)).Resist 4 is not irradiated with plasma. Therefore, removal is easily performed.

次に、OF4などのガスVC1u周波′屯界を印加し7
て発生するプラズマを用いるドライエツチング法で、5
i023をエツチングマスクとしてpolyeii  
2エツチングする(第1図(fo)参照)。たとえばバ
レル型エツチング袈直を用いOF4と02を坏槓比19
:1とした混合ガスケ用い、^周波醒カsoow、ガス
流、1i(2jOcc/分、圧力u、6Torrと(7
た時のp)Lysiのエツチング速度は、600017
mm であるので、SiO□3ijpolysi1 の
エツチングマスクとして十分用い得る。たとえば、前記
熱酸化後のpo 11e i 1の厚さが300OAの
場合は、エツチング時間は1分であυ、5iO23の膜
べりは100Aであるので、約5 CI OADI上の
厚さの5iO23全形成してかtすば、前記ドライエツ
チングは容易に行われる。
Next, apply a gas VC1u frequency field such as OF4 and
A dry etching method using plasma generated by
Polyeii using i023 as an etching mask
2 etching (see Figure 1 (fo)). For example, using a barrel-type etching cutter, OF4 and 02 can be combined with an etching ratio of 19.
:Using a mixed gasket with a temperature of
The etching speed of p) Lysi is 600017 when
mm, it can be sufficiently used as an etching mask for SiO□3ijpolysi1. For example, if the thickness of po 11e i 1 after the thermal oxidation is 300OA, the etching time is 1 minute υ, and the film thickness of 5iO23 is 100A, so the entire thickness of 5iO23 of about 5 CI OADI is etched. Once formed, the dry etching can be easily performed.

(第1図(fo)と(ω参照) 1だ、第2図より膜厚
500λ以上の5102全形成するのはきわめて容易で
める。polysiiエツチングする技術は、Siゲー
トM OSの集積度が1す1す向上するにつれ・自1丁
記エツチングのドライ化は今後さらに重曹(でなるト考
工られ、本発明のエツチングマスクの形成方法の応用師
値は高い。
(See Figure 1 (fo) and (ω)) 1. From Figure 2, it is extremely easy to completely form 5102 with a film thickness of 500λ or more. As technology improves, dry etching will be further developed using baking soda, and the application value of the etching mask forming method of the present invention will be high.

S i 025  の形成方法は、CvDを用いてもよ
く。
As a method for forming S i 025 , CvD may be used.

この場合、SiO□3 形成前後のpolyeilの膜
厚が変化しないことeよ明らかである。また、前記po
1ysi  エツチングのマスクとして用いf(5i0
25は、IJ Oi y s iエツチング後、除去せ
ずに中間絶は膜として用いることができる。また、mJ
記polysiエツチング後に、HF系エツチング液に
よりSi026を容易に除去し9ることは言う葦でもな
い。
In this case, it is clear that the film thickness of the polyeil before and after the formation of SiO□3 does not change. In addition, the po
1ysi Used as an etching mask f(5i0
25 can be used as an intermediate film without being removed after IJ Oi y Si etching. Also, mJ
It is needless to say that Si026 can be easily removed with an HF-based etching solution after the polysilicon etching described above.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(g)は1本晃明の半導体装置の製造方
広の一央!#、賃1]の工(呈膓(t/バず田1聞ト0
で4bす、第2図Qよ、polysi の熱酸1ヒ!F
斤iJUユ図である。 1・・・・polysi   2・・・・・・5102
6・・・・・・5102   4・・・・・−レジスト
以上
Figures 1 (a) to (g) are from Komei's method of manufacturing semiconductor devices! #, Rent 1)
So, 4b, Figure 2 Q, polysi hot acid 1! F
This is a diagram of 斤iJUyu. 1...polysi 2...5102
6...5102 4...-Resist or higher

Claims (1)

【特許請求の範囲】 (’11  半導体基板上に配した第1の薄膜を形成す
るエイ呈とsDi1M己帛2の【専膜全バターニングす
る工程と、バターニングされた前記第2の薄膜全マスク
として削ムピ第10薄l戻・tフラズマエッチングする
上程からなる半44犀泗置の製造方法。 (2)前記第10博1良を熱酸化することにより11J
記第2の薄膜ケ形成すること全特徴とする特訂趙求の範
囲第1.[JI記載の半4坏装置の製造方法。 L3)  Rij記第2の薄膜10VDにより形成する
ことを特徴とする特訂拍求の組曲第1項記載の半導体装
置の製造方法。 (4)  前記第10薄jIAがポリシリコンであるこ
とをQ’に徴とする特許請求の範囲第1項記載の半導体
装置の製造方法。 (尋 ti+i配H↓2の薄膜が准化シリコン膜である
こと金%徴とする一fjfF請求の範囲第1項記載の半
導体装置の製造方法。 (6)  前記第2の薄膜パターニング方法がHF系エ
ツチング液によるエツチングであること(i=%徴とす
る特許請求の範囲第1項記載の製造方法。
[Scope of Claims] ('11 A process for forming a first thin film disposed on a semiconductor substrate, and a step of completely patterning the entire second thin film that has been patterned. A method for manufacturing a semi-44-layer plate comprising the steps of removing the 10th thin film as a mask and performing plasma etching. (2) By thermally oxidizing the 10th layer,
The second thin film is formed as a special feature of the scope of the special edition by Zhao Qi. [Method for manufacturing a semi-four-piece device described in JI. L3) A method for manufacturing a semiconductor device according to Item 1 of Suite of Special Requests, characterized in that the second thin film of Rij is formed by 10VD. (4) The method for manufacturing a semiconductor device according to claim 1, wherein Q' is characterized in that the tenth thin JIA is polysilicon. (6) The method for manufacturing a semiconductor device according to claim 1, characterized in that the thin film with the ti+i distribution H↓2 is a parasitic silicon film. (6) The second thin film patterning method is performed using HF The manufacturing method according to claim 1, wherein the etching is performed using a base etching solution (i=%).
JP1182283A 1983-01-27 1983-01-27 Manufacture of semiconductor device Pending JPS59136931A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1182283A JPS59136931A (en) 1983-01-27 1983-01-27 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1182283A JPS59136931A (en) 1983-01-27 1983-01-27 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS59136931A true JPS59136931A (en) 1984-08-06

Family

ID=11788467

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1182283A Pending JPS59136931A (en) 1983-01-27 1983-01-27 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS59136931A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0629311A (en) * 1992-07-10 1994-02-04 Yamaha Corp Manufacture of semiconductor device
JP2002270831A (en) * 2001-03-13 2002-09-20 Fuji Electric Co Ltd Method of manufacturing semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0629311A (en) * 1992-07-10 1994-02-04 Yamaha Corp Manufacture of semiconductor device
JP2002270831A (en) * 2001-03-13 2002-09-20 Fuji Electric Co Ltd Method of manufacturing semiconductor device

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