JPS60254733A - Pattern forming method - Google Patents
Pattern forming methodInfo
- Publication number
- JPS60254733A JPS60254733A JP11132084A JP11132084A JPS60254733A JP S60254733 A JPS60254733 A JP S60254733A JP 11132084 A JP11132084 A JP 11132084A JP 11132084 A JP11132084 A JP 11132084A JP S60254733 A JPS60254733 A JP S60254733A
- Authority
- JP
- Japan
- Prior art keywords
- film
- resist
- semiconductor
- pattern
- polysilicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、半導体装置の製造方法に関し、特にり７トオ
フエ程により所望の電極パターンを形成する方法に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a desired electrode pattern by a seven-off process.
（従来技術）
従来、半導体装置の製造方法において、電極パターンを
リフトオフ工程により形成する方法が採用されている。(Prior Art) Conventionally, in a method of manufacturing a semiconductor device, a method of forming an electrode pattern by a lift-off process has been adopted.
例えば、第１図（ａ）に示すようにＧａＡｓＪｐ８ｉ等
の基板１上にレジスト２を塗布して所定のマスクにより
露光、現像を行ない、所定のパターンの窓３を形成し、
次に同図Φ）に示すように全面にＡｔ。For example, as shown in FIG. 1(a), a resist 2 is applied on a substrate 1 such as GaAsJp8i, exposed and developed using a predetermined mask, and windows 3 in a predetermined pattern are formed.
Next, as shown in Φ) in the same figure, At was applied to the entire surface.
Ａｕ 、 Ｔ Ｉ 等の所要の金属膜４を蒸着またはス
パッタリング等により形成する。その後同図（Ｃ）に示
すように残存するレジスト２を有機溶剤等の剥離剤によ
り溶解除去するとレジスト２上の金属膜４′は基板１か
ら遊離し窓３の部分に形成された金属膜４のみが基板１
上に残存する。その結果同図（ｄ）に示すように所定の
パターンの金属膜４を基板１上に形成することができる
。A required metal film 4 such as Au or T I is formed by vapor deposition, sputtering, or the like. Thereafter, as shown in FIG. 3(C), when the remaining resist 2 is dissolved and removed using a stripping agent such as an organic solvent, the metal film 4' on the resist 2 is released from the substrate 1, and the metal film 4 formed on the window 3 is removed. Only board 1
remain on top. As a result, a metal film 4 having a predetermined pattern can be formed on the substrate 1, as shown in FIG. 1D.
近年、半導体装置の緒特性向上のため、例えばＧａＡｓ
ＭＥ８ＰＥＴ （金属半導体接合をゲート電極として
用いた電界効果トランジスタ）においてはゲート電極の
ゲート長が０．３μｍ以下のものが要求されるなど微細
化が進んできた。しかしながら、従来の紫外線露光方法
では０．３μｍ以下のパターンを形成することは非常に
困難であり、また微細パターンの形成に適しているとい
われている電子ビーム露光方法は量産性が極めて悪いと
いう欠点がある。In recent years, in order to improve the characteristics of semiconductor devices, for example, GaAs
In ME8PET (field effect transistor using a metal-semiconductor junction as a gate electrode), miniaturization has progressed such that the gate length of the gate electrode is required to be 0.3 μm or less. However, it is extremely difficult to form patterns of 0.3 μm or less using conventional ultraviolet exposure methods, and electron beam exposure methods, which are said to be suitable for forming fine patterns, have extremely poor mass productivity. There is.
従って高能率、かつ高歩留りで０．３μｍ以下の金属パ
ターンを形成できる方法が望まれる。Therefore, a method that can form metal patterns of 0.3 μm or less with high efficiency and high yield is desired.
（発明が解決しようとする問題点）
本発明は、以上の点にかんがみなされたもので、その目
的は、上記のような微細構造の金属電極を形成する方法
を提供することにある。(Problems to be Solved by the Invention) The present invention has been made in view of the above points, and its purpose is to provide a method for forming a metal electrode having the above-mentioned microstructure.
（問題点を解決するための手段）
本発明によれば、基板上に絶縁膜を形成し、この絶縁膜
の側面を含む全面に半導体を形成し、半導体を異方性エ
ツチングにより除去して絶縁膜側面の半導体のみ残し、
その後絶縁膜を除去し、残存する半導体以外の領域にレ
ジストを形成し、半導体を除去し、全面に金属層を形成
後レジスト上の金属層をレジストとともに除去するパタ
ーン形成方法を得る。(Means for Solving the Problems) According to the present invention, an insulating film is formed on a substrate, a semiconductor is formed on the entire surface of the insulating film including the side surfaces, and the semiconductor is removed by anisotropic etching to insulate the insulating film. Leaving only the semiconductor on the side of the membrane,
Thereafter, a pattern forming method is obtained in which the insulating film is removed, a resist is formed in a region other than the remaining semiconductor, the semiconductor is removed, a metal layer is formed on the entire surface, and the metal layer on the resist is removed together with the resist.
以下、本発明をその実施例について図面により詳細に説
明する。。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the drawings. .
第２図は本発明の一実施例の工程断面図であり、基板上
に金属膜のパターンを形成する場合についてのものであ
る。FIG. 2 is a process sectional view of an embodiment of the present invention, which is for forming a metal film pattern on a substrate.
まず、第２図（ａ）に示すように、パターニングされた
絶縁膜、例えば５ｉ（ｈ膜５上にＣＶＤ法を用いて半導
体膜例えばポリシリコン膜６を均一に成長する。この８
ｉ０２膜５の側壁へのポリシリコン膜６の成長は後述
する如く所望のレジストパターン形状を得るためのもの
である。例えば、ゲート長０．２μｍのゲート電極を形
成する場合には厚さ０．２μｍのポリシリコン膜６が側
壁に成長するように全面に被着する。First, as shown in FIG. 2(a), a semiconductor film such as a polysilicon film 6 is uniformly grown on a patterned insulating film, such as a 5i (h film 5), using the CVD method.
The polysilicon film 6 is grown on the sidewall of the i02 film 5 in order to obtain a desired resist pattern shape, as will be described later. For example, when forming a gate electrode with a gate length of 0.2 μm, a polysilicon film 6 with a thickness of 0.2 μm is deposited on the entire surface so as to grow on the side walls.
次に、第２図中）に示すようにフレオン（ＣＦ４）ガス
による異方性プラズマエツチングにより８ｉ０ｚ膜５が
露呈するまでポリシリコン膜６をエツチングする。この
時、Ｓｉｎｇ膜５の側壁に成長したポリシリコン膜６は
異方性プラズマエツチングでは横方向のエツチング成分
がないためエツチングされずに残存する。Next, as shown in FIG. 2), the polysilicon film 6 is etched by anisotropic plasma etching using Freon (CF4) gas until the 8i0z film 5 is exposed. At this time, the polysilicon film 6 grown on the side wall of the Sing film 5 remains without being etched because there is no lateral etching component in the anisotropic plasma etching.
その後、第２図（Ｃ）に示すようにＳ ｉ０２膜５をフ
ッ酸等で除去し、５ｉＯｚ膜５の側壁のポリシリコン膜
６のみを残す。Thereafter, as shown in FIG. 2C, the Si02 film 5 is removed using hydrofluoric acid or the like, leaving only the polysilicon film 6 on the sidewalls of the 5iOz film 5.
次に、第２図（ｄ）に示すように、残存するポリシリコ
ン膜６の一部が博出するようにレジスト１２を塗布する
。その後、第２図（ｅ）に示すようにポリシリコン膜６
を混酸（例えばフッ酸、硝酸、氷酢酸の混合液）等で除
去する。Next, as shown in FIG. 2(d), a resist 12 is applied so that a portion of the remaining polysilicon film 6 is exposed. After that, as shown in FIG. 2(e), the polysilicon film 6
is removed with a mixed acid (for example, a mixture of hydrofluoric acid, nitric acid, and glacial acetic acid).
最後に第２図（ｆ）に示すように全面に金属膜１４を蒸
着、スパッタ等により形成し残存するレジスト１２を有
機溶剤等の剥離剤により溶解除去し、レジスト１２上の
金属膜１４を除去する。Finally, as shown in FIG. 2(f), a metal film 14 is formed on the entire surface by vapor deposition, sputtering, etc., and the remaining resist 12 is dissolved and removed using a stripping agent such as an organic solvent, and the metal film 14 on the resist 12 is removed. do.
かかる製法によれば、レジスト１２のパターン形成は８
ｉ０２膜５の側壁に成長されたポリシリコン膜６を利用
してでき、従来用いていた露光、現偉等の工程は必要と
しない。このため、側壁に成長する半導体膜の厚さを適
宜選ぶことにより微細なパターンも確実に形成すること
ができる。According to this manufacturing method, the pattern formation of the resist 12 is 8
It is made by using the polysilicon film 6 grown on the sidewall of the i02 film 5, and does not require the conventional processes such as exposure and lithography. Therefore, fine patterns can be reliably formed by appropriately selecting the thickness of the semiconductor film grown on the sidewalls.
以上説明したように本発明は、絶縁膜パターンの側壁に
成長させた半導体膜を残存させ、その残存する半導体膜
をマスクとしてレジストのパターン形成を行なうもので
あり、従来方法である。露光、現偉等の工程を用いるこ
となしに極めて微細なパターンを歩留りよく形成し得る
という利点がある。As explained above, the present invention is a conventional method in which a semiconductor film grown on the sidewall of an insulating film pattern is left and a resist pattern is formed using the remaining semiconductor film as a mask. This method has the advantage that extremely fine patterns can be formed with high yield without using processes such as exposure and lithography.
第１図（ａ）〜（ｄ）は従来のリフトオフ工程を示す断
面図、第２図（ａ）〜（ｆ）は本発明の一実施例の工程
を示す断面図である。
１．１１・・・・・・半導体基板、２．１２・・・・・
・レジスト、４．１４・・・・・・金属膜、５・・・・
・・絶縁膜、６・・・・・・半導体膜３゜
８２図
第２０FIGS. 1(a) to 1(d) are sectional views showing a conventional lift-off process, and FIGS. 2(a) to 2(f) are sectional views showing a process according to an embodiment of the present invention. 1.11... Semiconductor substrate, 2.12...
・Resist, 4.14...Metal film, 5...
...Insulating film, 6...Semiconductor film 3゜82Figure 20
Claims (1)
で被覆する工程と、該絶縁膜の側壁に成長した半導体膜
のみを残して他の半導体膜を除去する工程と、該残存す
る半導体膜をマスクとしてレジストのパターンを形成す
る工程と、レジストパターン表面に金属膜を形成する工
程と、前記レジスト上の前記金属膜を前記レジストとと
もに除去して前記レジスト間の金属膜を残す工程とを有
することを特徴とするパターン形成法。A step of forming an insulating film pattern on a substrate and covering the insulating film with a semiconductor film, a step of leaving only the semiconductor film grown on the sidewall of the insulating film and removing other semiconductor films, and a step of removing the remaining semiconductor film. A step of forming a resist pattern using a film as a mask, a step of forming a metal film on the surface of the resist pattern, and a step of removing the metal film on the resist together with the resist to leave a metal film between the resists. A pattern forming method characterized by comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11132084A JPS60254733A (en) | 1984-05-31 | 1984-05-31 | Pattern forming method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11132084A JPS60254733A (en) | 1984-05-31 | 1984-05-31 | Pattern forming method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60254733A true JPS60254733A (en) | 1985-12-16 |
Family
ID=14558227
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11132084A Pending JPS60254733A (en) | 1984-05-31 | 1984-05-31 | Pattern forming method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60254733A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62224936A (en) * | 1986-03-27 | 1987-10-02 | Rohm Co Ltd | Manufacture of semiconductor device |
| FR2607600A1 (en) * | 1986-11-28 | 1988-06-03 | Commissariat Energie Atomique | METHOD FOR PRODUCING ON ONE SUBSTRATE ELEMENTS SPACES ONE OF OTHERS |
| US5510286A (en) * | 1994-07-14 | 1996-04-23 | Hyundai Electronics Industries Co., Ltd. | Method for forming narrow contact holes of a semiconductor device |
-
1984
- 1984-05-31 JP JP11132084A patent/JPS60254733A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62224936A (en) * | 1986-03-27 | 1987-10-02 | Rohm Co Ltd | Manufacture of semiconductor device |
| FR2607600A1 (en) * | 1986-11-28 | 1988-06-03 | Commissariat Energie Atomique | METHOD FOR PRODUCING ON ONE SUBSTRATE ELEMENTS SPACES ONE OF OTHERS |
| US4931137A (en) * | 1986-11-28 | 1990-06-05 | Commissariat A L'energie Atomique | Process for producing mutually spaced conductor elements on a substrate |
| US5510286A (en) * | 1994-07-14 | 1996-04-23 | Hyundai Electronics Industries Co., Ltd. | Method for forming narrow contact holes of a semiconductor device |
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