JPS59121858A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS59121858A JPS59121858A JP22761482A JP22761482A JPS59121858A JP S59121858 A JPS59121858 A JP S59121858A JP 22761482 A JP22761482 A JP 22761482A JP 22761482 A JP22761482 A JP 22761482A JP S59121858 A JPS59121858 A JP S59121858A
- Authority
- JP
- Japan
- Prior art keywords
- cap
- base
- package
- glass
- vicinity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（１） 発明の技術分野
本発明は、ガラスで接着封止されるセラミックパッケー
ジを用いる半導体装置に関し、特にパッケージの改良構
造に関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a semiconductor device using a ceramic package adhesively sealed with glass, and particularly to an improved structure of the package.
（２）従来技術と問題点
上記のよう々半導体装置の従来例を第１図から第３図に
示しておる。第１図および第２図は第３図の矢印Ａ方向
へ見たそれぞれパッケージ封止前およびパッケージ封止
後の縦断面図でアシ、第３図は第１図の矢印Ｂ方向へ見
た平面図である。(2) Prior Art and Problems Conventional examples of semiconductor devices as described above are shown in FIGS. 1 to 3. Figures 1 and 2 are longitudinal cross-sectional views before and after package sealing, respectively, viewed in the direction of arrow A in Figure 3, and Figure 3 is a plane view viewed in the direction of arrow B in Figure 1. It is a diagram.
図中、符号１及び２はセラミックパッケージのベース及
びキャップを示し、符号３は半導体集積回路（ＩＣ，Ｌ
ＳＩ）のチップを示し、符号４はリード端子を示す。チ
ップ３はベース１のキャビティ５内に取シ付けられ、リ
ード端子４はベースｌとキャップ２の間に挿入されてワ
イヤ６を介しチップ３に接続される。ベース１およびキ
ャップ２にはそれぞれあらかじめガラス７を溶着し冷却
固化させてあシ、リード端子４をはさむ如くキャップ２
をベースに重ね合わせ、ガラス７を加熱溶融し再び冷却
固化させると、ベース１とキャップ２はリード端子４と
もども接着封止される。In the figure, numerals 1 and 2 indicate the base and cap of the ceramic package, and numeral 3 indicates a semiconductor integrated circuit (IC, L
SI) chip, and reference numeral 4 indicates a lead terminal. The chip 3 is mounted in the cavity 5 of the base 1, and the lead terminals 4 are inserted between the base 1 and the cap 2 and connected to the chip 3 via wires 6. Glass 7 is welded to the base 1 and cap 2 in advance and cooled and solidified.
When the glass 7 is heated and melted and then cooled and solidified again, the base 1 and the cap 2 are adhesively sealed together with the lead terminals 4.
しかるに従来の構造では、パッケージ封止の際、ガラス
７が溶融したときにリード端子４、（中でも笛３図で左
右両端の長いリード端子）の先端が第２図に示すように
上下に変位しやすく、従ってワイヤ６の断線やたるみが
生じやすいという欠点があった。However, in the conventional structure, when the glass 7 melts during package sealing, the tips of the lead terminals 4 (particularly the long lead terminals at both left and right ends in Figure 3) are displaced up and down as shown in Figure 2. Therefore, there is a drawback that the wire 6 is easily broken or slackened.
（３）発明の目的
本発明の目的は上記のような半導体装置における欠点を
解消すること、具体的には接続ワイヤの断線やたるみを
防止するだめのパッケージ改良構造を提供することにあ
る。(3) Purpose of the Invention The purpose of the present invention is to eliminate the above-mentioned drawbacks in semiconductor devices, and specifically to provide an improved package structure that prevents disconnection and sagging of connection wires.
（４）発明の構成
本発明は、概略的には、前述のようなセラミックパッケ
ージを用いた半導体装置において、リード端子のワイヤ
接続部近傍を保持する突起部を° パッケージのベース
およびキャップに設けた構成としたものである。(4) Structure of the Invention The present invention generally provides a semiconductor device using a ceramic package as described above, in which protrusions for holding the vicinity of wire connection portions of lead terminals are provided on the base and cap of the package. It is structured as follows.
（５）発明の実施例
以下、本発明の実施例につき図面を参照して詳細に説明
する。(5) Embodiments of the invention Hereinafter, embodiments of the invention will be described in detail with reference to the drawings.
本発明による半導体装置の一実施例を第４図から第６図
に示しである。この半導体装置の基本的構造は第１図か
ら第３図に示す従来例のものと同じであり、同一部品は
同一符号で示しである。An embodiment of a semiconductor device according to the present invention is shown in FIGS. 4 to 6. The basic structure of this semiconductor device is the same as that of the conventional example shown in FIGS. 1 to 3, and the same parts are designated by the same reference numerals.
本発明の特徴は、パッケージのペース１およびキャップ
２にそれぞれ突起部１ａおよび２ａを形成したことにあ
る。突起部１ａは第６図に示すようにキャピテイ５の周
囲に沿って環状に形成され、一方、突起部２ａは第５図
から明らかな如くワイヤ６を逃げるために突起部１ａよ
りも一同シ大きい環状形としである。突起部１ａ、２ａ
の高さは第４図から明らかなようにガラス７の厚さとほ
ぼ同じ寸法（Ｏ１３〜０．５ ｙａｒｎ ）としである
。A feature of the present invention is that protrusions 1a and 2a are formed on the paste 1 and cap 2 of the package, respectively. The protrusion 1a is formed in an annular shape along the circumference of the cavity 5 as shown in FIG. 6, while the protrusion 2a is larger than the protrusion 1a in order to allow the wire 6 to escape, as is clear from FIG. It has an annular shape. Projections 1a, 2a
As is clear from FIG. 4, the height of the glass 7 is approximately the same as the thickness of the glass 7 (O13~0.5 yarn).
このような構成によれば、第５図に示すようにキャップ
２をペースに重ねたときにリード端子４のワイヤ接続部
近傍が突起部１ａ、２ａ間にはさ捷れる。す々わちガラ
ス７が溶融してもワイヤ接続部近傍は上下変位しないよ
うに保持され、この結果、ワイヤ６の断線やたるみが確
実に防止されることになる。According to such a configuration, when the cap 2 is stacked on the pad as shown in FIG. 5, the vicinity of the wire connection portion of the lead terminal 4 is separated between the protrusions 1a and 2a. In other words, even if the glass 7 melts, the vicinity of the wire connection portion is held so as not to be vertically displaced, and as a result, the wire 6 is reliably prevented from breaking or sagging.
（６）発明の効果
以上のように本発明によれは、前述の如きガラス封止セ
ラミックパッケージを用いる半導体装置におけるパッケ
ージ封止時のリード端子接続ワイヤの断線やたるみを確
実に防止することができ、従って製品の歩留りが向上し
て、コスト低減が可能となるなど、その効果は著大であ
る。(6) Effects of the Invention As described above, according to the present invention, it is possible to reliably prevent disconnection and sagging of lead terminal connecting wires during package sealing in a semiconductor device using a glass-sealed ceramic package as described above. Therefore, the effects are significant, such as improving the yield of products and making it possible to reduce costs.
第１図から第３図は従来の半導体装置を示すもので第１
図および第２図はそれぞれパッケージ封止前およびパッ
ケージ封止後の第３図矢印Ａ方向へ見た縦断面図、第３
図は第１図矢印Ｂ方向へ見た平面図、第４図から第６図
は本発明による半導体装置をそれぞれ第１図から第３図
と対応させて示す図である。
１・・・ベース、 １ａ・・・突起部、２・・
・キャップ、 ２ａ・・・突起部、３・・・半
導体集積回路チップ、
４・・・リード端子、 ５・・・キャビティ、
６・・・ワイヤ、 ７・・・ガラス。
第１図
第２図
第３図
１゜Figures 1 to 3 show conventional semiconductor devices.
Figure 2 and Figure 2 are longitudinal sectional views taken in the direction of arrow A in Figure 3 before and after package sealing, respectively.
This figure is a plan view seen in the direction of arrow B in FIG. 1, and FIGS. 4 to 6 are views showing a semiconductor device according to the present invention in correspondence with FIGS. 1 to 3, respectively. 1...Base, 1a...Protrusion, 2...
- Cap, 2a... Protrusion, 3... Semiconductor integrated circuit chip, 4... Lead terminal, 5... Cavity,
6...Wire, 7...Glass. Figure 1 Figure 2 Figure 3 Figure 1゜
Claims (1)
成るパッケージ内に半導体集積回路のチップを収容し、
且つリード端子をベースとキャップ間に挿入してワイヤ
を介しチップに接続し、ベースとキャップをリード端子
ともどもガラスで接着封止してなる半導体装置において
、前記リード端子のワイヤ接続部近傍を保持する突起部
を前記ベースおよびキャップに設けたことを特徴とする
半導体装置。1. A semiconductor integrated circuit chip is housed in a package consisting of a base and a cap made of ceramic,
Further, in a semiconductor device in which a lead terminal is inserted between a base and a cap and connected to a chip via a wire, and the base and the cap are adhesively sealed together with the lead terminal with glass, the vicinity of the wire connection portion of the lead terminal is held. A semiconductor device characterized in that a protrusion is provided on the base and the cap.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22761482A JPS59121858A (en) | 1982-12-28 | 1982-12-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22761482A JPS59121858A (en) | 1982-12-28 | 1982-12-28 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59121858A true JPS59121858A (en) | 1984-07-14 |
| JPH0340950B2 JPH0340950B2 (en) | 1991-06-20 |
Family
ID=16863691
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22761482A Granted JPS59121858A (en) | 1982-12-28 | 1982-12-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59121858A (en) |
-
1982
- 1982-12-28 JP JP22761482A patent/JPS59121858A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0340950B2 (en) | 1991-06-20 |
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