JP2000012770A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JP2000012770A JP2000012770A JP17078698A JP17078698A JP2000012770A JP 2000012770 A JP2000012770 A JP 2000012770A JP 17078698 A JP17078698 A JP 17078698A JP 17078698 A JP17078698 A JP 17078698A JP 2000012770 A JP2000012770 A JP 2000012770A
- Authority
- JP
- Japan
- Prior art keywords
- connection terminal
- semiconductor element
- surface connection
- wiring board
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
- H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、高密度実装性に優
れた半導体装置およびその製造方法に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device excellent in high-density mounting and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】一般に、半導体装置を用いた電子機器
は、小型軽薄化の要求から、構成部品の高密度実装性が
求められている。これを達成するため、その構成部品の
一つである半導体装置では、半導体素子と略同等の大き
さを有する、いわゆるチップサイズパッケージ（以下、
ＣＳＰと称す）が提案・実用化されている。2. Description of the Related Art In general, electronic equipment using a semiconductor device is required to have high-density mountability of components in order to reduce the size and weight. In order to achieve this, a semiconductor device, which is one of the components, has a so-called chip-size package (hereinafter, referred to as a package) having a size substantially equal to a semiconductor element.
CSP) has been proposed and put into practical use.
【０００３】ＣＳＰとしては、例えば図４に示すように
構成されたものが知られている。詳しくは、このＣＳＰ
では、板状の配線基板５１上に、絶縁性を有する接着材
５２を介して半導体素子５３がダイマウントされてい
る。そして、その半導体素子５３が、配線基板５１の下
面に所定パターンで配列された外部接続用端子５４と、
金線５５を用いたワイヤボンディングによって電気的に
接続されている。また、半導体素子５３および金線５５
は、配線基板５１の上面を覆う封止樹脂５６によって封
止されている。[0003] As a CSP, for example, one configured as shown in FIG. 4 is known. Specifically, this CSP
Here, a semiconductor element 53 is die-mounted on a plate-shaped wiring board 51 via an adhesive 52 having an insulating property. Then, the semiconductor element 53 includes an external connection terminal 54 arranged in a predetermined pattern on the lower surface of the wiring board 51,
They are electrically connected by wire bonding using a gold wire 55. Further, the semiconductor element 53 and the gold wire 55
Are sealed with a sealing resin 56 that covers the upper surface of the wiring board 51.
【０００４】このように構成されたＣＳＰによれば、例
えばＱＦＰ（quad flat package)やＳＯＰ（small out-
line package) といった表面実装型の半導体装置のよう
にリードピン（端子）がパッケージ側面から突出しない
ので、表面実装型の半導体装置に比べて大幅な実装面積
の削減を達成することができる。According to the CSP configured as described above, for example, QFP (quad flat package) or SOP (small out-
Since the lead pins (terminals) do not protrude from the side surface of the package as in a surface-mounted semiconductor device such as a line package, a significant reduction in the mounting area can be achieved as compared with a surface-mounted semiconductor device.
【０００５】[0005]
【発明が解決しようとする課題】ところで、近年、半導
体装置を用いた電子機器では、信号処理系のデジタル化
が主流となっているが、信号処理系をデジタル化する
と、回路構成が複雑化し、構成部品の点数も増加してし
まう傾向にある。そのため、信号処理系をデジタル化し
ても部品点数が増加することなく高機能化に対応できる
ように、一つの半導体装置（１パッケージ）内に複数の
半導体素子を収納したマルチチップＣＳＰの要求が高ま
りつつある。In recent years, in electronic equipment using a semiconductor device, digitization of a signal processing system has become mainstream. However, when the signal processing system is digitized, a circuit configuration becomes complicated. The number of component parts also tends to increase. Therefore, there is an increasing demand for a multi-chip CSP in which a plurality of semiconductor elements are housed in one semiconductor device (one package) so that the number of components can be increased without increasing the number of components even if the signal processing system is digitized. It is getting.
【０００６】そこで、本発明は、１パッケージ内に複数
の半導体素子を備える半導体装置であり、さらには複数
の半導体素子を備えていても実装面積の増加を招くこと
なく高密度実装性に優れ、電子機器の小型軽薄化を容易
に実現することを可能にする半導体装置を提供すること
を目的とする。Accordingly, the present invention is directed to a semiconductor device having a plurality of semiconductor elements in one package. Even if a plurality of semiconductor elements are provided, the semiconductor device is excellent in high-density mounting without increasing the mounting area. It is an object of the present invention to provide a semiconductor device capable of easily realizing a small and light electronic device.
【０００７】また、半導体装置は、通常、その製造工程
において、半導体素子の機能を確認するための検査が行
われる。ところが、１パッケージ内に複数の半導体素子
を備える半導体装置では、これら複数の半導体素子のう
ちの一つに異常があると、他の半導体素子に異常がなく
ても、半導体装置全体としては正常でないとされるた
め、１パッケージ内に一つの半導体素子のみを備える半
導体装置に比べて、製造工程における歩留りが悪化して
しまう可能性が高い。[0007] In a manufacturing process of a semiconductor device, an inspection for confirming the function of the semiconductor element is usually performed. However, in a semiconductor device having a plurality of semiconductor elements in one package, if one of the plurality of semiconductor elements has an abnormality, even if the other semiconductor element does not have an abnormality, the entire semiconductor device is not normal. Therefore, there is a high possibility that the yield in the manufacturing process is deteriorated as compared with a semiconductor device including only one semiconductor element in one package.
【０００８】そこで、本発明は、１パッケージ内に複数
の半導体素子を備える半導体装置を製造する場合であっ
ても、歩留りが悪化してしまうことがなく、高い生産性
を確保することのできる半導体装置の製造方法を提供す
ることを目的とする。Therefore, the present invention provides a semiconductor device which can ensure high productivity without lowering the yield even when manufacturing a semiconductor device having a plurality of semiconductor elements in one package. An object of the present invention is to provide a method for manufacturing a device.
【０００９】[0009]
【課題を解決するための手段】本発明は、上記目的を達
成するために案出された半導体装置で、上面中央近傍に
凹部を有する第一の配線基板と、前記凹部内に搭載され
た第一の半導体素子と、前記第一の配線基板の前記凹部
以外の上面に設けられた上面部接続端子と、前記第一の
配線基板の下面に設けられた外部接続用端子と、を備え
る第一構造体と、板状に形成された第二の配線基板と、
前記第二の配線基板上に搭載された第二の半導体素子
と、前記第二の配線基板の下面で前記上面部接続端子に
対応して配設された下面部接続端子と、を備える第二構
造体とからなり、前記第一構造体および前記第二構造体
は、前記上面部接続端子と前記下面部接続端子とが接合
する状態で互いに重なり合うように一体化され、前記外
部接続用端子は、前記第一の半導体素子並びに前記上面
部接続端子および前記下面部接続端子を介した前記第二
の半導体素子と電気的に接続するものであることを特徴
とする。SUMMARY OF THE INVENTION The present invention is directed to a semiconductor device devised to achieve the above object, wherein a first wiring board having a recess near the center of the upper surface, and a second wiring board mounted in the recess. A first semiconductor element, an upper surface connection terminal provided on an upper surface other than the concave portion of the first wiring substrate, and an external connection terminal provided on a lower surface of the first wiring substrate. A structure, a second wiring board formed in a plate shape,
A second semiconductor element mounted on the second wiring substrate, and a second lower surface connection terminal disposed on the lower surface of the second wiring substrate so as to correspond to the upper surface connection terminal. The first structure and the second structure are integrated so as to overlap each other in a state where the upper surface connection terminal and the lower surface connection terminal are joined, and the external connection terminal is The first semiconductor element is electrically connected to the second semiconductor element via the upper surface connection terminal and the lower surface connection terminal.
【００１０】上記構成の半導体装置によれば、第一構造
体は第一の半導体素子を備え、第二構造体は第二の半導
体素子を備え、しかもこれらは互いに重なり合うように
一体化されている。また、これら第一および第二の半導
体素子と電気的に接続する外部接続用端子は、第一の配
線基板の下面、すなわち第一構造体の下側面に配列され
ている。したがって、この半導体装置では、例えば高機
能化への対応のために第一および第二の半導体素子とい
った複数の半導体素子を備えていても、第一の半導体素
子と第二の半導体素子とが平面的に並んで配置された
り、外部接続用端子が構造体側面から突出してしまうこ
とがないので、実装面積の増加を招いてしまうことがな
い。According to the semiconductor device having the above structure, the first structure has the first semiconductor element, and the second structure has the second semiconductor element, and these are integrated so as to overlap each other. . External connection terminals electrically connected to the first and second semiconductor elements are arranged on the lower surface of the first wiring board, that is, on the lower surface of the first structure. Therefore, in this semiconductor device, even if a plurality of semiconductor elements such as the first and second semiconductor elements are provided in order to cope with higher functionality, the first semiconductor element and the second semiconductor element are planar. Since the external connection terminals do not protrude from the side of the structure, the mounting area does not increase.
【００１１】また、本発明は、上記目的を達成するため
に案出された半導体装置の製造方法で、先ず、上面中央
近傍に設けられた凹部と、その凹部以外の上面に設けら
れた上面部接続端子と、下面に設けられた外部接続用端
子と、を有する第一の配線基板を形成する。そして、そ
の第一の配線基板の前記凹部内に第一の半導体素子を搭
載し、その第一の半導体素子と前記上面部接続端子の
間、前記第一の半導体素子と前記外部接続用端子の間あ
るいは前記上面部接続端子と前記外部接続用端子の間の
うちの少なくとも二つを電気的に接続して第一構造体を
構成する。また、前記第一構造体とは別に、前記上面部
接続端子に対応する下面部接続端子を下面に有した第二
の配線基板を形成し、前記第二の配線基板上に第二の半
導体素子を搭載し、その第二の半導体素子を前記下面部
接続端子と電気的に接続して第二構造体を構成する。そ
の後、前記第一構造体と前記第二構造体とを互いに重ね
合わせて一体化するとともに、その際に前記上面部接続
端子と前記下面部接続端子とを、上下方向にのみ導通が
得られる異方導電接着剤またははんだによって接合し
て、前記第二の半導体素子を前記第一の半導体素子と前
記外部接続用端子との少なくとも一方と電気的に接続す
る。Further, according to the present invention, there is provided a method of manufacturing a semiconductor device devised to achieve the above object, wherein a concave portion provided near the center of the upper surface and an upper surface portion provided on the upper surface other than the concave portion are provided. A first wiring board having connection terminals and external connection terminals provided on the lower surface is formed. Then, a first semiconductor element is mounted in the concave portion of the first wiring board, and the first semiconductor element and the external connection terminal are provided between the first semiconductor element and the upper surface connection terminal. At least two of the terminals or between the upper surface connection terminal and the external connection terminal are electrically connected to form a first structure. In addition, separately from the first structure, a second wiring board having a lower surface connection terminal corresponding to the upper surface connection terminal on a lower surface is formed, and a second semiconductor element is formed on the second wiring substrate. And the second semiconductor element is electrically connected to the lower surface connection terminal to form a second structure. Thereafter, the first structure and the second structure are overlapped with each other to be integrated, and at this time, the upper surface connection terminal and the lower surface connection terminal are electrically connected only in the vertical direction. The second semiconductor element is electrically connected to at least one of the first semiconductor element and the external connection terminal by bonding with a conductive adhesive or solder.
【００１２】上記手順の半導体装置の製造方法によれ
ば、第一の半導体素子を備えた第一構造体と第二の半導
体素子を備えた第二構造体とをそれぞれ別に構成し、そ
の後に、これら第一構造体と第二構造体とを互いに重ね
合わせて一体化する。したがって、この製造方法では、
半導体装置が第一および第二の半導体素子といった複数
の半導体素子を備えるものであっても、第一構造体を構
成した時点で第一の半導体素子の機能を確認し、また第
二構造体を構成した時点で第二の半導体素子の機能を確
認し、それぞれを確認した後に異常のないものだけを互
いに重ね合わせて一体化するといったことができるよう
になる。According to the method of manufacturing a semiconductor device according to the above procedure, a first structure having a first semiconductor element and a second structure having a second semiconductor element are separately formed. The first structure and the second structure are overlapped and integrated. Therefore, in this manufacturing method,
Even if the semiconductor device has a plurality of semiconductor elements such as first and second semiconductor elements, the function of the first semiconductor element is confirmed at the time of forming the first structure, and the second structure is At the time of configuration, the function of the second semiconductor element is confirmed, and after confirming the functions, only those having no abnormality can be overlapped and integrated.
【００１３】[0013]
【発明の実施の形態】以下、図面に基づき本発明に係わ
る半導体装置およびその製造方法について説明する。図
１は、本発明をマルチチップＣＳＰに適用した場合にお
ける一例の概略構成を示す側断面図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to the present invention and a method for manufacturing the same will be described below with reference to the drawings. FIG. 1 is a side sectional view showing a schematic configuration of an example when the present invention is applied to a multi-chip CSP.
【００１４】図例のように、本実施の形態におけるマル
チチップＣＳＰは、大別すると、第一構造体１０と第二
構造体２０とからなるものである。As shown in the figure, the multi-chip CSP according to the present embodiment roughly includes a first structure 10 and a second structure 20.
【００１５】第一構造体１０は、樹脂やセラミックス等
の絶縁部材からなる第一の配線基板１１を基に構成され
ている。第一の配線基板１１は、その上面中央近傍に凹
部１２を有するとともに、その上面周縁近傍、すなわち
凹部１２以外の上面に複数の上面部接続端子１３が設け
られており、さらには下面の所定位置に複数の外部接続
用端子１４が規則的に配列されているものである。The first structure 10 is configured based on a first wiring board 11 made of an insulating member such as resin or ceramic. The first wiring board 11 has a concave portion 12 near the center of the upper surface, and a plurality of upper surface connection terminals 13 provided near the peripheral edge of the upper surface, that is, on the upper surface other than the concave portion 12. A plurality of external connection terminals 14 are regularly arranged.
【００１６】複数の外部接続用端子１４は、その一部が
上面部接続端子１３の一部と電気的に接続しており、他
部が凹部１２内に設けられた図示しない導電パターンと
電気的に接続している。なお、上面部接続端子１３のう
ち、外部接続用端子１４と接続しない他部は、凹部１２
内の導電パターンと電気的に接続しているものとする。Some of the plurality of external connection terminals 14 are electrically connected to a part of the upper surface connection terminals 13, and the other is electrically connected to a conductive pattern (not shown) provided in the recess 12. Connected to The other part of the upper surface connection terminal 13 that is not connected to the external connection terminal 14 is the recess 12
It is assumed that it is electrically connected to the conductive pattern inside.
【００１７】また、第一の配線基板１１の凹部１２内に
は、第一の半導体素子１５がダイマウントされている。
ただし、ここでは、第一の半導体素子１５が一つである
場合を例にあげるが、これは二つ以上であってもよい。In the recess 12 of the first wiring board 11, a first semiconductor element 15 is die-mounted.
Here, the case where the number of the first semiconductor elements 15 is one is described as an example, but the number may be two or more.
【００１８】第一の半導体素子１５は、絶縁性を有する
接着材１６によって第一の配線基板１１に接着されてい
るものとする。また、凹部１２内にダイマウントされた
第一の半導体素子１５は、金線１７を用いたワイヤボン
ディングによって、凹部１２内に設けられた導電パター
ンと電気的に接続している。これにより、第一の半導体
素子１５は、複数の外部接続用端子１４のうちの上述し
た他部と、上面部接続端子１３のうちの外部接続用端子
１４と接続しない他部との両方に、電気的に接続するこ
とになる。さらに、第一の半導体素子１５および金線１
７は、第一の配線基板１１の凹部１２を覆う封止樹脂１
８によって封止されている。The first semiconductor element 15 is bonded to the first wiring board 11 by an adhesive 16 having an insulating property. The first semiconductor element 15 die-mounted in the concave portion 12 is electrically connected to the conductive pattern provided in the concave portion 12 by wire bonding using a gold wire 17. Thereby, the first semiconductor element 15 is connected to both the above-mentioned other part of the plurality of external connection terminals 14 and the other part of the upper surface connection terminal 13 which is not connected to the external connection terminal 14, It will be electrically connected. Further, the first semiconductor element 15 and the gold wire 1
7 is a sealing resin 1 covering the concave portion 12 of the first wiring board 11.
8 sealed.
【００１９】このように、第一構造体１０は、第一の配
線基板１１、上面部接続端子１３、外部接続用端子１４
および第一の半導体素子１５を備えて構成されている。
なお、第一構造体１０は、従来のＣＳＰと同様の手順
（製造工程）を経て製造されるものとする。As described above, the first structure 10 includes the first wiring board 11, the upper surface connection terminals 13, and the external connection terminals 14.
And a first semiconductor element 15.
The first structure 10 is manufactured through the same procedure (manufacturing process) as the conventional CSP.
【００２０】一方、第二構造体２０は、絶縁部材からな
る第二の配線基板２１を基に構成されている。第二の配
線基板２１は、第一の配線基板１１と略同一の平面形状
を有するもので、その下面に下面部接続端子２２が設け
られたものである。下面部接続端子２２は、第一の配線
基板１１の上面部接続端子１３に対応するように配設さ
れたものであり、第二の配線基板２１の上面に設けられ
た図示しない導電パターンと電気的に接続しているもの
である。On the other hand, the second structure 20 is formed based on a second wiring board 21 made of an insulating member. The second wiring board 21 has substantially the same planar shape as the first wiring board 11, and has a lower surface connection terminal 22 provided on the lower surface thereof. The lower surface connection terminals 22 are arranged so as to correspond to the upper surface connection terminals 13 of the first wiring board 11, and are connected to a conductive pattern (not shown) provided on the upper surface of the second wiring board 21. Are connected to each other.
【００２１】また、第二の配線基板２１の上面には、第
二の半導体素子２３ａ，２３ｂがダイマウントされてい
る。なお、ここでは、第二の半導体素子２３ａ，２３ｂ
として、二つの素子がそれぞれ並設されている場合を例
にあげるが、これは単数のものであっても、あるいは三
つ以上のものが並設されていてもよい。この第二の半導
体素子２３ａ，２３ｂも、絶縁性を有する接着材２４に
よって第二の配線基板２１に接着されているものとす
る。On the upper surface of the second wiring board 21, second semiconductor elements 23a and 23b are die-mounted. Here, the second semiconductor elements 23a, 23b
As an example, a case where two elements are arranged side by side will be described as an example, but this may be a single element or three or more elements may be arranged side by side. It is assumed that the second semiconductor elements 23a and 23b are also bonded to the second wiring board 21 by the adhesive 24 having an insulating property.
【００２２】第二の配線基板２１上にダイマウントされ
た第二の半導体素子２３ａ，２３ｂは、それぞれが金線
２５を用いたワイヤボンディングによって、第二の配線
基板２１上の導電パターンを介して下面部接続端子２２
と電気的に接続している。さらに、第二の半導体素子２
３ａ，２３ｂおよび金線２５は、第二の配線基板２１の
上面を覆う封止樹脂２６によって封止されている。The second semiconductor elements 23a and 23b die-mounted on the second wiring board 21 are each bonded by wire bonding using gold wires 25 via the conductive pattern on the second wiring board 21. Lower surface connection terminal 22
Is electrically connected to Further, the second semiconductor element 2
The 3a, 23b and the gold wire 25 are sealed by a sealing resin 26 covering the upper surface of the second wiring board 21.
【００２３】このように、第二構造体２０は、第二の配
線基板２１、下面部接続端子２２、および第二の半導体
素子２３ａ，２３ｂを備えて構成されている。なお、こ
の第二構造体２０も、従来のＣＳＰと同様の手順（製造
工程）を経て製造されるものとする。As described above, the second structure 20 includes the second wiring board 21, the lower surface connection terminals 22, and the second semiconductor elements 23a and 23b. The second structure 20 is also manufactured through the same procedure (manufacturing process) as the conventional CSP.
【００２４】第一構造体１０および第二構造体２０が構
成されると、その後、これらは、第一構造体１０の上方
に第二構造体２０が位置するように、互いに重なり合う
状態で一体化される。After the first structure 10 and the second structure 20 have been constructed, they are then integrated in an overlapping manner so that the second structure 20 is located above the first structure 10. Is done.
【００２５】このとき、第一構造体１０における上面部
接続端子１３と第二構造体２０における下面部接続端子
２２とは、それぞれ対応する位置に配設されているの
で、第一構造体１０と第二構造体２０との重ね合わせに
よって、これらは互いに向き合うこととなる。そこで、
第一構造体１０と第二構造体２０との一体化に際し、こ
れらは、異方導電接着剤３１によって接着される。At this time, the upper surface connection terminals 13 in the first structure 10 and the lower surface connection terminals 22 in the second structure 20 are arranged at corresponding positions, respectively. By overlapping with the second structure 20, they face each other. Therefore,
When the first structure 10 and the second structure 20 are integrated, they are bonded by an anisotropic conductive adhesive 31.
【００２６】異方導電接着剤３１は、上下方向にのみ導
通が得られる異方導電性接続に使用される樹脂接着剤で
あり、図２に示すように、導電粒子３１ａを均一分散さ
せて上下電極間に介在させることにより、電極間方向の
みに導通が得られ、水平方向には絶縁が保たれるように
するためのものである。The anisotropic conductive adhesive 31 is a resin adhesive used for anisotropic conductive connection that can provide conduction only in the vertical direction, and as shown in FIG. By interposing between the electrodes, conduction is obtained only in the direction between the electrodes, and insulation is maintained in the horizontal direction.
【００２７】したがって、異方導電接着剤３１を第一の
配線基板１１の凹部以外の上面と第二の配線基板２１の
下面との間に充填して、第一構造体１０と第二構造体２
０とを接着すれば、これらが重なり合う状態で一体化さ
れるとともに、互いに向き合う上面部接続端子１３と下
面部接続端子２２が接合されてこれらの間が電気的に通
じることとなる。Therefore, the space between the upper surface of the first wiring board 11 other than the concave portion and the lower surface of the second wiring board 21 is filled with the anisotropic conductive adhesive 31 so that the first structure 10 and the second structure 2
By bonding 0 to each other, they are integrated in an overlapping state, and the upper surface connection terminal 13 and the lower surface connection terminal 22 facing each other are joined to electrically communicate between them.
【００２８】その結果、第一構造体１０と第二構造体２
０とを一体化すると、第一の配線基板１１の下面に配列
された複数の外部接続用端子１４は、その一部が上面部
接続端子１３および下面部接続端子２２を介して第二の
半導体素子２３ａ，２３ｂと電気的に接続するととも
に、他部が第一の半導体素子１５と電気的に接続するこ
ととなる。また、第一の半導体素子１５と第二の半導体
素子２３ａ，２３ｂとの間についても、上面部接続端子
１３および下面部接続端子２２を介して互いに電気的に
接続することとなる。As a result, the first structure 10 and the second structure 2
0, the plurality of external connection terminals 14 arranged on the lower surface of the first wiring board 11 are partially connected to the second semiconductor via the upper surface connection terminals 13 and the lower surface connection terminals 22. The other parts are electrically connected to the first semiconductor element 15 while being electrically connected to the elements 23a and 23b. Also, the first semiconductor element 15 and the second semiconductor elements 23a and 23b are electrically connected to each other via the upper surface connection terminal 13 and the lower surface connection terminal 22.
【００２９】以上のように、本実施の形態におけるマル
チチップＣＳＰは、第一の半導体素子１５を備えた第一
構造体１０と、第二の半導体素子２３ａ，２３ｂを備え
た第二構造体２０とが、互いに重なり合うように一体化
されており、しかもこれら第一の半導体素子１５および
第二の半導体素子２３ａ，２３ｂと電気的に接続する外
部接続用端子１４が第一の配線基板１１の下面、すなわ
ち第一構造体１０の下側面に配列されている。そのた
め、このマルチチップＣＳＰでは、例えば高機能化への
対応のために第一の半導体素子１５および第二の半導体
素子２３ａ，２３ｂといった複数の半導体素子を備えて
いても、これらが平面的に並んで配置されたり、外部接
続用端子１４が構造体側面から突出してしまうことがな
いので、実装面積の増加を招いてしまうことがない。As described above, the multi-chip CSP according to the present embodiment includes the first structure 10 having the first semiconductor element 15 and the second structure 20 having the second semiconductor elements 23a and 23b. And external connection terminals 14 electrically connected to the first semiconductor element 15 and the second semiconductor elements 23a and 23b are formed on the lower surface of the first wiring board 11. That is, they are arranged on the lower surface of the first structure 10. For this reason, even if the multi-chip CSP includes a plurality of semiconductor elements such as the first semiconductor element 15 and the second semiconductor elements 23a and 23b in order to cope with higher functions, they are arranged in a plane. And the external connection terminal 14 does not protrude from the side of the structure, so that the mounting area does not increase.
【００３０】したがって、このマルチチップＣＳＰを用
いて電子機器を構成すれば、例えば信号処理系のデジタ
ル化に伴って回路構成が複雑化しても、実装面積の増加
を招くことなく一つのＣＳＰ（１パッケージ）内に複数
の半導体素子を収納されるので、部品点数の増加を極力
抑えて電子機器の小型軽薄化の実現を達成することが可
能となる。Therefore, if an electronic device is configured using this multi-chip CSP, even if the circuit configuration becomes complicated due to, for example, digitization of a signal processing system, one CSP (1) can be mounted without increasing the mounting area. Since a plurality of semiconductor elements are accommodated in the package, the increase in the number of parts can be suppressed as much as possible, and the realization of a small and light electronic device can be achieved.
【００３１】また、本実施の形態におけるマルチチップ
ＣＳＰは、第一の半導体素子１５を備えた第一構造体１
０と、第二の半導体素子２３ａ，２３ｂを備えた第二構
造体２０とを、それぞれ別に構成した後に、これらを互
いに重ね合わせて一体化することで製造されている。そ
のため、この製造方法によれば、マルチチップＣＳＰが
複数の半導体素子１５，２３ａ，２３ｂを備えるもので
あっても、第一構造体１０を構成した時点で第一の半導
体素子１５の機能を確認し、また第二構造体２０を構成
した時点で第二の半導体素子２３ａ，２３ｂの機能を確
認し、それぞれを確認した後に異常のないものだけを互
いに重ね合わせて一体化することができる。Further, the multi-chip CSP according to the present embodiment has a first structure 1 having a first semiconductor element 15.
0 and the second structure 20 including the second semiconductor elements 23a and 23b are separately formed, and then they are overlapped and integrated with each other. Therefore, according to this manufacturing method, even if the multi-chip CSP includes a plurality of semiconductor elements 15, 23a, and 23b, the function of the first semiconductor element 15 is confirmed when the first structure 10 is formed. In addition, when the second structure 20 is formed, the functions of the second semiconductor elements 23a and 23b are confirmed, and after confirming the functions, only those having no abnormality can be overlapped and integrated.
【００３２】したがって、本実施の形態の製造方法によ
りマルチチップＣＳＰを構成すれば、第一構造体１０と
第二構造体２０とをそれぞれ単体で検査することによ
り、複数の半導体素子１５，２３ａ，２３ｂのうちのい
ずれか一つの異常によりマルチチップＣＳＰ全体が異常
となってしまうのを防ぐことができるので、１パッケー
ジ内に一つの半導体素子のみを備える半導体装置に比べ
て歩留りが悪化してしまうことがない。つまり、複数の
半導体素子１５，２３ａ，２３ｂを備えるマルチチップ
ＣＳＰを製造する場合であっても、歩留りが悪化してし
まうのを防ぐことにより高い生産性を確保することがで
き、結果として製造工程の生産効率向上にも繋がる。Therefore, when a multi-chip CSP is formed by the manufacturing method of the present embodiment, the first structure 10 and the second structure 20 are individually tested, so that a plurality of semiconductor elements 15, 23a, Since it is possible to prevent the entire multi-chip CSP from becoming abnormal due to any one of the abnormalities in the semiconductor device 23b, the yield is reduced as compared with a semiconductor device having only one semiconductor element in one package. Nothing. In other words, even when a multi-chip CSP including a plurality of semiconductor elements 15, 23a, and 23b is manufactured, high productivity can be ensured by preventing the yield from deteriorating. Also leads to improved production efficiency.
【００３３】さらに、本実施の形態におけるマルチチッ
プＣＳＰでは、上面部接続端子１３と下面部接続端子２
２との間が、上下方向にのみ導通が得られる異方導電接
着剤３１によって接合されている。すなわち、第一構造
体１０と第二構造体２０とを一体化する際に、異方導電
接着剤３１を充填するだけで、互いに向き合う上面部接
続端子１３と下面部接続端子２２が接合される。したが
って、異方導電接着剤３１を用いて上面部接続端子１３
と下面部接続端子２２とを接合すれば、その接合が、第
一構造体１０と第二構造体２０との一体化に併せて、容
易かつ確実に行われることとなる。しかも、フラックス
汚染等も発生しないので、クリーン化への対応も容易と
なる。Further, in the multi-chip CSP according to the present embodiment, the upper surface connection terminal 13 and the lower surface connection terminal 2
2 are joined by an anisotropic conductive adhesive 31 that can provide conduction only in the vertical direction. That is, when the first structure 10 and the second structure 20 are integrated, the upper surface connection terminal 13 and the lower surface connection terminal 22 facing each other are joined only by filling the anisotropic conductive adhesive 31. . Therefore, the upper surface connection terminal 13 is formed by using the anisotropic conductive adhesive 31.
When the lower surface connection terminal 22 and the lower surface connection terminal 22 are bonded, the bonding is easily and reliably performed along with the integration of the first structure 10 and the second structure 20. Moreover, since no flux contamination or the like occurs, it is easy to cope with the cleanliness.
【００３４】なお、本実施の形態では、上面部接続端子
１３と下面部接続端子２２とを異方導電接着剤３１を用
いて接合した場合を例に挙げて説明したが、本発明はこ
れに限定されるものではない。例えば、図３に示すよう
に、互いに向き合う上面部接続端子１３と下面部接続端
子２２の間を、はんだ３２によって接合した場合であっ
ても、上述したようなマルチチップＣＳＰの実装面積増
加の抑制や生産効率向上といった効果を得ることができ
る。また、はんだ３２を用いて上面部接続端子１３と下
面部接続端子２２とを接合した場合には、一般的に広く
用いられる接合方法によるものなので、接合の信頼性や
作業の容易性を確保できるとともに、自動化への対応も
容易となる。In this embodiment, the case where the upper surface connection terminal 13 and the lower surface connection terminal 22 are joined by using the anisotropic conductive adhesive 31 has been described as an example, but the present invention is not limited to this. It is not limited. For example, as shown in FIG. 3, even when the upper surface connection terminal 13 and the lower surface connection terminal 22 facing each other are joined by the solder 32, the increase in the mounting area of the multi-chip CSP as described above is suppressed. And the effect of improving production efficiency can be obtained. In addition, when the upper surface connection terminal 13 and the lower surface connection terminal 22 are joined using the solder 32, since the joining method is generally used, the reliability of the joining and the easiness of the work can be secured. At the same time, it is easy to respond to automation.
【００３５】また、本実施の形態では、外部接続用端子
１４が第一の半導体素子１５と第二の半導体素子２３
ａ，２３ｂとの両方に接続するとともに、第一の半導体
素子１５と第二の半導体素子２３ａ，２３ｂとの間も互
いに接続している場合を例に挙げて説明したが、本発明
はこれに限定されるものではなく、第二の半導体素子２
３ａ，２３ｂが上面部接続端子１３および下面部接続端
子２２を介して外部接続用端子１４と第一の半導体素子
１５と少なくとも一方と接続していればよい。例えば、
第二の半導体素子２３ａ，２３ｂが第一の半導体素子１
５のみと接続している場合であっても、第一の半導体素
子１５が外部接続用端子１４と接続していれば、第二の
半導体素子２３ａ，２３ｂは第一の半導体素子１５を介
して外部接続用端子１４と電気的に接続していることに
なるので、このような場合であっても高機能化に対応し
つつ高密度実装性および高い生産性を実現することがで
きるようになる。In this embodiment, the external connection terminal 14 is connected to the first semiconductor element 15 and the second semiconductor element 23.
a and 23b, and the first semiconductor element 15 and the second semiconductor elements 23a and 23b are also connected to each other. However, the present invention is not limited to this. Without being limited, the second semiconductor element 2
What is necessary is that 3a and 23b be connected to at least one of the external connection terminal 14 and the first semiconductor element 15 via the upper surface connection terminal 13 and the lower surface connection terminal 22. For example,
The second semiconductor elements 23a and 23b are the first semiconductor elements 1
Even if the first semiconductor element 15 is connected to the external connection terminal 14, the second semiconductor elements 23 a and 23 b are connected via the first semiconductor element 15 even when the first semiconductor element 15 is connected to only the first semiconductor element 15. Since it is electrically connected to the external connection terminal 14, even in such a case, it is possible to realize high-density mounting and high productivity while coping with high functionality. .
【００３６】[0036]
【発明の効果】以上に説明したように、本発明の半導体
装置は、第一の半導体素子を備えた第一構造体と、第二
の半導体素子を備えた第二構造体とが、互いに重なり合
うように一体化されており、しかも第一および第二の半
導体素子と電気的に接続する外部接続用端子が第一構造
体の下側面に配列されている。そのため、この半導体装
置では、複数の半導体素子を備えていても、これらが平
面的に並んで配置されたり、外部接続用端子が構造体側
面から突出してしまうことがない。よって、この半導体
装置は、回路構成の複雑化等に伴う高機能化にも実装面
積の増加を招くことなく対応することができ、電子機器
の小型軽薄化を容易に実現することを可能にする。As described above, in the semiconductor device of the present invention, the first structure having the first semiconductor element and the second structure having the second semiconductor element overlap each other. The external connection terminals electrically integrated with the first and second semiconductor elements are arranged on the lower surface of the first structure. Therefore, in this semiconductor device, even if a plurality of semiconductor elements are provided, they are not arranged side by side in a plane, and external connection terminals do not protrude from the side of the structure. Therefore, this semiconductor device can cope with high functionality accompanying a complicated circuit configuration or the like without increasing the mounting area, and it is possible to easily realize a small and light electronic device. .
【００３７】また、本発明の半導体装置の製造方法で
は、第一の半導体素子を備えた第一構造体と、第二の半
導体素子を備えた第二構造体とを、それぞれ別に構成し
た後に、これらを互いに重ね合わせて一体化するように
なっているので、半導体装置が複数の半導体素子を備え
るものであっても、第一構造体を構成した時点で第一の
半導体素子の機能を確認し、また第二構造体を構成した
時点で第二の半導体素子の機能を確認し、それぞれを確
認した後に異常のないものだけを互いに重ね合わせて一
体化する、といったことができるようになる。したがっ
て、この製造方法を用いれば、複数の半導体素子を備え
る半導体装置を製造する場合であっても、歩留りが悪化
してしまうのを防ぐことにより、高い生産性を確保する
ことができ、結果として製造工程の生産効率向上にも繋
がる。In the method of manufacturing a semiconductor device according to the present invention, after the first structure having the first semiconductor element and the second structure having the second semiconductor element are separately formed, Since these are superimposed on each other and integrated, even if the semiconductor device includes a plurality of semiconductor elements, the function of the first semiconductor element is confirmed when the first structure is formed. In addition, the function of the second semiconductor element can be confirmed at the time when the second structure is formed, and after confirming the functions, only those having no abnormality can be overlapped and integrated. Therefore, by using this manufacturing method, even when a semiconductor device including a plurality of semiconductor elements is manufactured, high productivity can be ensured by preventing the yield from deteriorating. As a result, It also leads to the improvement of production efficiency in the manufacturing process.
【図面の簡単な説明】[Brief description of the drawings]
【図１】本発明に係わる半導体装置の実施の形態の一例
の概略構成を示す側断面図である。FIG. 1 is a side sectional view showing a schematic configuration of an example of an embodiment of a semiconductor device according to the present invention.
【図２】図１に示す半導体装置の第一構造体と第二構造
体の間における上面部接続端子と下面部接続端子との接
続部分の詳細を示す説明図である。FIG. 2 is an explanatory diagram showing details of a connection portion between an upper surface connection terminal and a lower surface connection terminal between a first structure and a second structure of the semiconductor device shown in FIG. 1;
【図３】上面部接続端子と下面部接続端子との接続部分
の他の例を示す説明図である。FIG. 3 is an explanatory diagram showing another example of a connection portion between an upper surface connection terminal and a lower surface connection terminal.
【図４】従来の半導体装置の一例の概略構成を示す側断
面図である。FIG. 4 is a side sectional view showing a schematic configuration of an example of a conventional semiconductor device.
１０…第一構造体、１１…第一の配線基板、１２…凹
部、１３…上面部接続端子、１４…外部接続用端子、１
５…第一の半導体素子、２０…第二構造体、２１…第二
の配線基板、２２…下面部接続端子、２３ａ，２３ｂ…
第二の半導体素子DESCRIPTION OF SYMBOLS 10 ... 1st structure, 11 ... 1st wiring board, 12 ... recessed part, 13 ... Upper surface connection terminal, 14 ... External connection terminal, 1
5 first semiconductor element, 20 second structure, 21 second wiring board, 22 lower surface connection terminals, 23a, 23b
Second semiconductor element
Claims (5)
基板と、前記凹部内に搭載された第一の半導体素子と、
前記第一の配線基板の前記凹部以外の上面に設けられた
上面部接続端子と、前記第一の配線基板の下面に設けら
れた外部接続用端子と、を備える第一構造体と、 板状に形成された第二の配線基板と、前記第二の配線基
板上に搭載された第二の半導体素子と、前記第二の配線
基板の下面で前記上面部接続端子に対応して配設された
下面部接続端子と、を備える第二構造体とからなり、 前記第一構造体および前記第二構造体は、前記上面部接
続端子と前記下面部接続端子とが接合する状態で互いに
重なり合うように一体化され、 前記外部接続用端子は、前記第一の半導体素子並びに前
記上面部接続端子および前記下面部接続端子を介した前
記第二の半導体素子と電気的に接続するものであること
を特徴とする半導体装置。A first wiring board having a recess near the center of the upper surface; a first semiconductor element mounted in the recess;
A first structure including an upper surface connection terminal provided on an upper surface of the first wiring board other than the concave portion, and an external connection terminal provided on a lower surface of the first wiring board; Formed on the second wiring board, a second semiconductor element mounted on the second wiring board, and disposed on the lower surface of the second wiring substrate corresponding to the upper surface connection terminal. And a lower surface connection terminal, wherein the first structure and the second structure overlap each other in a state where the upper surface connection terminal and the lower surface connection terminal are joined to each other. Wherein the external connection terminal is electrically connected to the second semiconductor element via the first semiconductor element and the upper surface connection terminal and the lower surface connection terminal. Characteristic semiconductor device.
続端子は、上下方向にのみ導通が得られる異方導電接着
剤によって接合されていることを特徴とする請求項１記
載の半導体装置。2. The semiconductor device according to claim 1, wherein the upper surface connection terminal and the lower surface connection terminal are joined by an anisotropic conductive adhesive capable of providing conduction only in a vertical direction.
続端子は、はんだによって接合されていることを特徴と
する請求項１記載の半導体装置。3. The semiconductor device according to claim 1, wherein the upper surface connection terminal and the lower surface connection terminal are joined by solder.
部以外の上面に設けられた上面部接続端子と、下面に設
けられた外部接続用端子と、を有する第一の配線基板を
形成し、 前記第一の配線基板の前記凹部内に第一の半導体素子を
搭載し、該第一の半導体素子と前記上面部接続端子の
間、前記第一の半導体素子と前記外部接続用端子の間あ
るいは前記上面部接続端子と前記外部接続用端子の間の
うちの少なくとも二つを電気的に接続して第一構造体を
構成し、 前記第一構造体とは別に、前記上面部接続端子に対応す
る下面部接続端子を下面に有した第二の配線基板を形成
し、 前記第二の配線基板上に第二の半導体素子を搭載し、該
第二の半導体素子を前記下面部接続端子と電気的に接続
して第二構造体を構成し、 その後、前記第一構造体と前記第二構造体とを互いに重
ね合わせて一体化するとともに、その際に前記上面部接
続端子と前記下面部接続端子とを上下方向にのみ導通が
得られる異方導電接着剤によって接合して、前記第二の
半導体素子を前記第一の半導体素子と前記外部接続用端
子との少なくとも一方と電気的に接続することを特徴と
する半導体装置の製造方法。4. A first wiring board having a concave portion provided near the center of the upper surface, upper surface connection terminals provided on the upper surface other than the concave portion, and external connection terminals provided on the lower surface. A first semiconductor element is mounted in the concave portion of the first wiring board, and the first semiconductor element and the external connection terminal are provided between the first semiconductor element and the upper surface connection terminal. At least two of the first and second connection portions are electrically connected to each other to form a first structure, and the top connection terminal is separate from the first structure. Forming a second wiring substrate having a lower surface connection terminal corresponding to the lower surface, mounting a second semiconductor element on the second wiring substrate, and mounting the second semiconductor element on the lower surface connection terminal Electrically connected to the first structure to form a second structure. Along with the second structure and superimposed and integrated together, at this time, the upper surface connection terminal and the lower surface connection terminal are joined by an anisotropic conductive adhesive that provides conduction only in the vertical direction, A method of manufacturing a semiconductor device, comprising: electrically connecting the second semiconductor element to at least one of the first semiconductor element and the external connection terminal.
部以外の上面に設けられた上面部接続端子と、下面に設
けられた外部接続用端子と、を有する第一の配線基板を
形成し、 前記第一の配線基板の前記凹部内に第一の半導体素子を
搭載し、該第一の半導体素子と前記上面部接続端子の
間、前記第一の半導体素子と前記外部接続用端子の間あ
るいは前記上面部接続端子と前記外部接続用端子の間の
うちの少なくとも二つを電気的に接続して第一構造体を
構成し、 前記第一構造体とは別に、前記上面部接続端子に対応す
る下面部接続端子を下面に有した第二の配線基板を形成
し、 前記第二の配線基板上に第二の半導体素子を搭載し、該
第二の半導体素子を前記下面部接続端子と電気的に接続
して第二構造体を構成し、 その後、前記第一構造体と前記第二構造体とを互いに重
ね合わせて一体化するとともに、その際に前記上面部接
続端子と前記下面部接続端子とをはんだによって接合し
て、前記第二の半導体素子を前記第一の半導体素子と前
記外部接続用端子との少なくとも一方と電気的に接続す
ることを特徴とする半導体装置の製造方法。5. A first wiring board having a concave portion provided near the center of the upper surface, upper surface connection terminals provided on the upper surface other than the concave portion, and external connection terminals provided on the lower surface. A first semiconductor element is mounted in the concave portion of the first wiring board, and the first semiconductor element and the external connection terminal are provided between the first semiconductor element and the upper surface connection terminal. At least two of the first and second connection portions are electrically connected to each other to form a first structure, and the top connection terminal is separate from the first structure. Forming a second wiring substrate having a lower surface connection terminal corresponding to the lower surface, mounting a second semiconductor element on the second wiring substrate, and mounting the second semiconductor element on the lower surface connection terminal Electrically connected to the first structure to form a second structure. The second structure is overlapped with each other and integrated, and at this time, the upper surface connection terminal and the lower surface connection terminal are joined by soldering, and the second semiconductor element is connected to the first semiconductor. A method for manufacturing a semiconductor device, comprising: electrically connecting at least one of an element and the external connection terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17078698A JP2000012770A (en) | 1998-06-18 | 1998-06-18 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17078698A JP2000012770A (en) | 1998-06-18 | 1998-06-18 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000012770A true JP2000012770A (en) | 2000-01-14 |
Family
ID=15911351
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17078698A Pending JP2000012770A (en) | 1998-06-18 | 1998-06-18 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000012770A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005260138A (en) * | 2004-03-15 | 2005-09-22 | Matsushita Electric Ind Co Ltd | Board device |
| JP2009129975A (en) * | 2007-11-20 | 2009-06-11 | Spansion Llc | Semiconductor device and its manufacturing method |
-
1998
- 1998-06-18 JP JP17078698A patent/JP2000012770A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005260138A (en) * | 2004-03-15 | 2005-09-22 | Matsushita Electric Ind Co Ltd | Board device |
| JP2009129975A (en) * | 2007-11-20 | 2009-06-11 | Spansion Llc | Semiconductor device and its manufacturing method |
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