JPS59107563A - スタテイツク型半導体メモリ装置 - Google Patents

スタテイツク型半導体メモリ装置

Info

Publication number
JPS59107563A
JPS59107563A JP57216825A JP21682582A JPS59107563A JP S59107563 A JPS59107563 A JP S59107563A JP 57216825 A JP57216825 A JP 57216825A JP 21682582 A JP21682582 A JP 21682582A JP S59107563 A JPS59107563 A JP S59107563A
Authority
JP
Japan
Prior art keywords
substrate
resistor
forming
poly
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57216825A
Other languages
English (en)
Inventor
Shoji Hanamura
花村　昭次
Osamu Minato
湊　修
Toshio Sasaki
敏夫 佐々木
Shuichi Yamamoto
秀一 山本
Toshiaki Masuhara
増原　利明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57216825A priority Critical patent/JPS59107563A/ja
Priority to EP83112313A priority patent/EP0111307A3/en
Priority to KR1019830005883A priority patent/KR840007313A/ko
Publication of JPS59107563A publication Critical patent/JPS59107563A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20—Resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
    • H01L27/0738—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors in combination with resistors only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/15—Static random access memory [SRAM] devices comprising a resistor load element

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、半導体装置に係り、特に、集積度を飛躍的に
向上するのに好適なスタティック型半導体メモリ装置に
関する。
〔従来技術〕
従来のスタティック型半導体メモリ装置のメモリセル構
成法のうち、抵抗を負荷とするものとして第１図に示す
ものが知られている。同図において、１は電・η線（電
位ｖｃｃ）、２および３は負荷抵抗、４および５は電荷
蓄積ノード、６は接地線（電位Ｖｓｓ）、７はワード線
、８および９はデータ線、１０および１１は駆動ＭＯ８
）ランジスタ（以下ＭＯ８Ｔという）、１２および１３
は情報転送ＭＯ８Ｔである。従来、上記電源線１は、Ｍ
Ｏ８Ｔ１０〜１３のゲートを形成するものと同じ高不純
物濃度の多結晶シリコン１を用いて形成し、また、負荷
抵抗２および３は、同条結晶ンリコン層の一部を、真性
半導体として残す、あるいは低不純物濃度とすることに
より形成していた。すなわち、ＭＯ８ＴＩ　Ｏ〜１３の
ゲート電極、電＃＠１、オヨび負荷抵抗２．３は、同一
平面上に形成されていた。このため、十分な高密度集積
化が困難であるという欠点があった。
〔発明の目的〕
本発明の目的は、上記した欠点を除き、十分な高密度集
積化を可能とした半導体メモリ装置を提供することにあ
る。
〔発明の概要〕
甲、在、半導体素子間分離領域の形成技術として、基板
表面に、小面積の深い穴を形成する技術が報告されてい
る。本発明は、この技術を応用し、一端を電源に接続さ
れた抵抗を、半導体基板深さ方向に小面積で形成しよう
とするものである。
実施例 以丁、本発明の一実楢例を第２図により説明する。本実
唯例では、高濃度第１導電型半導体基板２１上の第２導
電型ウェル層２２の表面部分に、高濃度第１導ｉ１！型
のドレインおよびソース領域２３．２４と多結晶シリコ
ンのゲート電極２５から成るＭＯ８ＴＱｏが構成されて
いる。Ｑ、ｏのドレイン領域２３および電源電位をとる
基板２１の間には、ウェル層２２とは！化膜等の絶縁物
２６で分離された多結晶シリコン等の物質から成る抵抗
２７が設けられている。同図において、ゲー）を極およ
び抵抗となる多結晶シリコンの上部は、ドレインおよび
ソース領域形成時に導入される不純物により、また、抵
抗体下部の多結晶シリコン層は高濃度基板かられき上が
る不純物により、それぞれ第１導電型層となり、金属電
極等とのオーミック・コンタクトが可能となる。ここで
、基板２１およびＱＤのノースを、それぞれＶｃｃ＋’
Ｖｓ８電位にとれば、抵抗２７およびＱｏけ、第１図の
２、ＩＯＫ相当する素子となり、インバータが構成され
る。したがって、他に同様のインバータを一対設け、こ
れらの間でフリップ・フロップ回路構成をとり、さらに
情報転送トランジスタを設けることにより、第１図に示
したスタティック型メモリセルを構成すΔことができる
。
〔発明の効果〕
本発明によれば、従来、半導体表面に構成していた負荷
抵抗を、基板内の深さ方向に構成できること、寸だ、メ
モリセル間を貫いて基板表面上に配置する電源線を設け
る必要がなくなること、により、メモリセルを高密度に
集積化できる効襲がある。
【図面の簡単な説明】
、第１図は、高抵抗を負荷とするスタティック型半導体
メモリセルの回路図、第２図は本発明の実施例の一部断
面図である。 １・・・電源線、２，３・・・負荷抵抗、４．訃・・Ｔ
荷蓄積ノード、６・・・接地線、７・・・ワー）”、Ｉ
Ｊ、８．９・・・データ線、１０．１１・・・駆動ＭＯ
８）ラン・ジスタ、１２．１３・・・転送ＭＯ８）ラン
ジスタ、２１・・・高年）仲働濃度基板、２２・・・ウ
ェル層、２３・・・ドレイン領域、２４・・・ノース領
域、２５・・・ゲート電″ボ、２６・・・絶縁物、２７
・・・抵抗体。 代理人　弁理士　薄田利幸：；７ン：ｚ蹟 ■　１　　図 乙 右　？　霞 ｃ

Claims (1)

    【特許請求の範囲】
  1. 電荷蓄積ノードへの電荷の補給を抵抗を介して行なうス
    タティック型半導体メモリ装置において、該抵抗を、半
    導体基板内の深さ方向に設け、一端を電荷蓄積ノードに
    、他端を電源電位にとった基板に接続することを特徴と
    するスタティック型半導体メモリ装装置。
JP57216825A 1982-12-13 1982-12-13 スタテイツク型半導体メモリ装置 Pending JPS59107563A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP57216825A JPS59107563A (ja) 1982-12-13 1982-12-13 スタテイツク型半導体メモリ装置
EP83112313A EP0111307A3 (en) 1982-12-13 1983-12-07 Semiconductor integrated circuit having a buried resistor
KR1019830005883A KR840007313A (ko) 1982-12-13 1983-12-12 매입저항(埋入抵抗)을 가진 반도체 집적회로(半導體集積回路)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57216825A JPS59107563A (ja) 1982-12-13 1982-12-13 スタテイツク型半導体メモリ装置

Publications (1)

Publication Number Publication Date
JPS59107563A true JPS59107563A (ja) 1984-06-21

Family

ID=16694478

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57216825A Pending JPS59107563A (ja) 1982-12-13 1982-12-13 スタテイツク型半導体メモリ装置

Country Status (3)

Country Link
EP (1) EP0111307A3 (ja)
JP (1) JPS59107563A (ja)
KR (1) KR840007313A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4890144A (en) * 1987-09-14 1989-12-26 Motorola, Inc. Integrated circuit trench cell

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0391123A3 (en) * 1989-04-04 1991-09-11 Texas Instruments Incorporated Extended length trench resistor and capacitor
DE102008060470A1 (de) 2008-12-05 2010-06-10 Henkel Ag & Co. Kgaa Reinigungsmittel
US8956938B2 (en) 2012-05-16 2015-02-17 International Business Machines Corporation Epitaxial semiconductor resistor with semiconductor structures on same substrate
CN111370474B (zh) * 2020-04-23 2023-10-24 上海华虹宏力半导体制造有限公司 沟槽栅器件的栅极串联电阻

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2148175A1 (de) * 1971-09-27 1973-04-05 Siemens Ag Integrierte halbleiterschaltung
DE2947311C2 (de) * 1978-11-24 1982-04-01 Hitachi, Ltd., Tokyo Integrierte Halbleiterschaltung

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4890144A (en) * 1987-09-14 1989-12-26 Motorola, Inc. Integrated circuit trench cell

Also Published As

Publication number Publication date
EP0111307A3 (en) 1985-11-06
EP0111307A2 (en) 1984-06-20
KR840007313A (ko) 1984-12-06

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