JPS59104539U - Chippukiyariya - Google Patents
ChippukiyariyaInfo
- Publication number
- JPS59104539U JPS59104539U JP20100882U JP20100882U JPS59104539U JP S59104539 U JPS59104539 U JP S59104539U JP 20100882 U JP20100882 U JP 20100882U JP 20100882 U JP20100882 U JP 20100882U JP S59104539 U JPS59104539 U JP S59104539U
- Authority
- JP
- Japan
- Prior art keywords
- chip
- external connection
- connection terminals
- cavity
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Combinations Of Printed Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来の最も典型的なチップキャリアの構造う示
す斜視図、第2図と第3図は本考案に基づく新しいチッ
プキャリアの構造の一実施例を示す断面図および裏面図
である。−
図において1.1はチップ基板、2はキャビティ、3は
半導体集積回路チップ、4は接続パッド、5は外部接続
端子、6は接続部、7は中央接続パッド、8はスルーホ
ール、9は中央接続部、10は中央外部接続端子をそれ
ぞれ示す。FIG. 1 is a perspective view showing the most typical conventional chip carrier structure, and FIGS. 2 and 3 are a cross-sectional view and a rear view showing an embodiment of the new chip carrier structure based on the present invention. - In the figure, 1.1 is a chip board, 2 is a cavity, 3 is a semiconductor integrated circuit chip, 4 is a connection pad, 5 is an external connection terminal, 6 is a connection part, 7 is a central connection pad, 8 is a through hole, 9 is a The center connection portion and 10 indicate the center external connection terminal, respectively.
Claims (1)
と、チップ基板、および該チップ基板上に形成され、か
つ前記チップキャビティの底面より前記チップ基板の表
面と側面を経て裏面に設けられた接続部に達する複数の
外部接続端子より構成されたチップキャリアにおいて、
さらに前記チップキャビティの底面よりスルーホールあ
るいはピアホールを介して前記チップ基板の裏面の中央
部に設けられた前記外部接続端子の接続部より大型の中
央接続部に連接した単数あるいは複数の中央外部接続端
子を有することを特徴とするチップキャリア。A chip cavity that accommodates and mounts a semiconductor integrated circuit chip, a chip substrate, and a plurality of connecting parts formed on the chip substrate and extending from the bottom surface of the chip cavity through the front surface and side surfaces of the chip substrate to the connecting portion provided on the back surface. In a chip carrier composed of external connection terminals,
Furthermore, one or more central external connection terminals are connected from the bottom surface of the chip cavity to a central connection section larger than the connection section of the external connection terminals provided at the center of the back surface of the chip substrate through a through hole or a peer hole. A chip carrier characterized by having.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20100882U JPS59104539U (en) | 1982-12-28 | 1982-12-28 | Chippukiyariya |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20100882U JPS59104539U (en) | 1982-12-28 | 1982-12-28 | Chippukiyariya |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59104539U true JPS59104539U (en) | 1984-07-13 |
Family
ID=30426515
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP20100882U Pending JPS59104539U (en) | 1982-12-28 | 1982-12-28 | Chippukiyariya |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59104539U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2005013359A1 (en) * | 2003-07-31 | 2005-02-10 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device |
-
1982
- 1982-12-28 JP JP20100882U patent/JPS59104539U/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2005013359A1 (en) * | 2003-07-31 | 2005-02-10 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device |
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