JPS59101878A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS59101878A JPS59101878A JP21095782A JP21095782A JPS59101878A JP S59101878 A JPS59101878 A JP S59101878A JP 21095782 A JP21095782 A JP 21095782A JP 21095782 A JP21095782 A JP 21095782A JP S59101878 A JPS59101878 A JP S59101878A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor substrate
- back surface
- diode
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 239000010936 titanium Substances 0.000 claims description 5
- 229910052709 silver Inorganic materials 0.000 claims description 4
- 239000004332 silver Substances 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 7
- 238000009792 diffusion process Methods 0.000 abstract description 6
- 229910052751 metal Inorganic materials 0.000 abstract description 3
- 239000002184 metal Substances 0.000 abstract description 3
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 238000007740 vapor deposition Methods 0.000 abstract description 2
- 239000011521 glass Substances 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 210000003127 knee Anatomy 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置に係シ、特にＰＩＮ構造を有する半
導体基、板の裏面の電極構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a semiconductor substrate having a PIN structure and an electrode structure on the back surface of the substrate.
ＰＩＮ構造を有する従来の半導体素子は、第１図に示す
ように、外部との引き出し電極を得るための裏面の金属
として、第１層にチタン（Ｔｉ）層７、第２層に金（Ａ
ｕ）層８．第３層に金銀（ＡｕＡ、 ）層９．主表面の
第４層に銀（Ａｇ）層１０を用いている。一方、反対側
の表面には、抵抗値ＩＫΩ以上を有する半導体基板１に
部分的に、半導体基板１とは逆の導電型の拡散層こと、
半導体基板１と同一型の導電型の拡散層４とが形成され
、この表面に酸化保護膜２、さらに窒化膜５が形成、さ
れ次に拡散層３と接触する表面引き出し電極が形成され
る。As shown in FIG. 1, a conventional semiconductor element having a PIN structure has a titanium (Ti) layer 7 as the first layer and a gold (A
u) Layer 8. Gold and silver (AuA, ) layer 9. A silver (Ag) layer 10 is used as the fourth layer on the main surface. On the other hand, on the opposite surface, a diffusion layer of a conductivity type opposite to that of the semiconductor substrate 1 is partially formed on the semiconductor substrate 1 having a resistance value of IKΩ or more;
A diffusion layer 4 of the same conductivity type as the semiconductor substrate 1 is formed, an oxide protective film 2 and a nitride film 5 are formed on this surface, and then a surface extraction electrode in contact with the diffusion layer 3 is formed.
このよりなＰＩＮ構造を有する半導体素子の利用領域は
最近拡大されつつあシ、特にガラス容器に組み込まれた
ＰＩＮダイオードの原価低減は必然になってきている。The area of application of semiconductor elements having this rigid PIN structure has been expanding recently, and it has become inevitable to reduce the cost of PIN diodes, especially those incorporated in glass containers.
現有のガラス容器で、最大の原価低減方法はダブル・ヒ
ートシンク・ダイオード（ＤＨＤ）化による組立方式で
あるが、この方法は工程中非常な高温（６００℃乃至６
５０℃）処理を必要とする。したがって、第１図に示す
ような、裏面にある電極メタル構成では、Ａｕ層８がＴ
ｉ層７を通過し、高抵抗を有する半導体基板１に拡散さ
れてしまい、特性不良を起とす原因となった。そのため
、ガラス容器に組込む場合も、アノード部とカソード部
とを別個に加工し、その後半導体素子に高温を加えない
（４５０℃以下）方法で組立を行なっていたが、いずれ
にしても熱に対する特性の経時変化が改善されず、高信
頼度を確保することができないという欠点があった。The biggest cost reduction method for existing glass containers is the assembly method using double heat sink diodes (DHD), but this method uses extremely high temperatures (600°C to 600°C) during the process.
50°C) treatment is required. Therefore, in the electrode metal configuration on the back side as shown in FIG.
It passed through the i-layer 7 and was diffused into the semiconductor substrate 1 having high resistance, causing poor characteristics. Therefore, when assembling it into a glass container, the anode and cathode parts were processed separately and then assembled using a method that did not apply high temperatures to the semiconductor element (below 450°C). However, there was a drawback that the change over time was not improved and high reliability could not be ensured.
本発明の目的は、前記欠点を改善したＰＩＮ構造を有す
る半導体装置を提供するものである。An object of the present invention is to provide a semiconductor device having a PIN structure that improves the above drawbacks.
本発明は、ＰＩＮ構造を有する半導体素子の裏面に、Ｔ
・からなる第１層を設け、この上にＡｇか一！
らなる第２層を設けた電極を備えたことを特徴とする半
導体装置にある。The present invention provides T
・A first layer consisting of Ag or one is provided on top of this! A semiconductor device characterized by comprising an electrode provided with a second layer consisting of:
以下図面を参照して本発明の詳細な説明する。The present invention will be described in detail below with reference to the drawings.
第２図は本発明の一実施例の半導体装置を示す断面図で
ある。同図において、表面がわけ前記第１図の場合と同
一である。裏面がわにおいて、蒸着またはスパッタによ
シ任意な厚さのＴｉ層１７とＡｇ層１８とが形成される
。FIG. 2 is a sectional view showing a semiconductor device according to an embodiment of the present invention. In this figure, the surface is the same as that shown in FIG. 1 above. On the back side, a Ti layer 17 and an Ag layer 18 of arbitrary thickness are formed by vapor deposition or sputtering.
このように、本発明によれば、ＴｉＮＡｇ層の構造にす
ることによって裏面の電極メタルが半導体基板のシリコ
ン中−＼拡散されることなく、また組立工程の簡単なり
ＨＤ化も実施され、安価で信頼性の高いＰＩＮダイオー
ドが得られるといり利点がある。As described above, according to the present invention, by using the TiNAg layer structure, the electrode metal on the back side is not diffused into the silicon of the semiconductor substrate, and the assembly process is simplified and HD can be implemented at low cost. The advantage is that a highly reliable PIN diode can be obtained.
尚、ここではパイ（π）型ダイオードについて説明した
が、これに限るものではなく４、ニー−（ν）型ダイオ
ードについても同様に可能なことはいうまでもない。It should be noted that although a pi (π) type diode has been described here, the present invention is not limited to this, and it goes without saying that a knee (v) type diode can also be used in the same manner.
第１図は従来のＰＩＮ構造を有するダイオードの断面図
で、第２図は本発明の一実施例のダイオードの断面図で
ある。同図において、
１・・・・・・高抵抗を有する半導体基板、２・・・・
・・酸化保護膜、３・・・・・・半導体基板とは逆の導
電型の拡散層、４・・・・・・半導体基板と同−型の導
電型の拡散層、５・・・・・・窒化膜、６・・・・・・
表面引出し電極、７．１７・・・・・・Ｔｉ層、８・・
・・・・札層、９・・・・・・ＡｕＡｇ層、１０゜１８
・・・・・・Ａ８層。FIG. 1 is a sectional view of a diode having a conventional PIN structure, and FIG. 2 is a sectional view of a diode according to an embodiment of the present invention. In the figure, 1...a semiconductor substrate having high resistance, 2...
... Oxidation protective film, 3... Diffusion layer of the opposite conductivity type to the semiconductor substrate, 4... Diffusion layer of the same conductivity type as the semiconductor substrate, 5... ...Nitride film, 6...
Surface extraction electrode, 7.17...Ti layer, 8...
...Bill layer, 9...AuAg layer, 10°18
...A8 layer.
Claims (1)
その上の第２層に銀を使用した電極を有することを特徴
とする半導体装置。Titanium is used as the first layer on the back side of the semiconductor substrate having a PIN structure.
A semiconductor device characterized by having an electrode using silver in a second layer thereon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21095782A JPS59101878A (en) | 1982-12-01 | 1982-12-01 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21095782A JPS59101878A (en) | 1982-12-01 | 1982-12-01 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59101878A true JPS59101878A (en) | 1984-06-12 |
Family
ID=16597907
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21095782A Pending JPS59101878A (en) | 1982-12-01 | 1982-12-01 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59101878A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06350109A (en) * | 1993-06-10 | 1994-12-22 | Nec Corp | Pin structure semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4940065A (en) * | 1972-08-17 | 1974-04-15 | ||
| JPS4940673A (en) * | 1972-08-22 | 1974-04-16 |
-
1982
- 1982-12-01 JP JP21095782A patent/JPS59101878A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4940065A (en) * | 1972-08-17 | 1974-04-15 | ||
| JPS4940673A (en) * | 1972-08-22 | 1974-04-16 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06350109A (en) * | 1993-06-10 | 1994-12-22 | Nec Corp | Pin structure semiconductor device |
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