JPS5965476A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5965476A
JPS5965476A JP17666482A JP17666482A JPS5965476A JP S5965476 A JPS5965476 A JP S5965476A JP 17666482 A JP17666482 A JP 17666482A JP 17666482 A JP17666482 A JP 17666482A JP S5965476 A JPS5965476 A JP S5965476A
Authority
JP
Japan
Prior art keywords
metal
film
gallium
bonding
ohmic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17666482A
Other languages
Japanese (ja)
Inventor
Akira Ogawa
小川　昭
Kazunori Fukuma
福間　和則
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP17666482A priority Critical patent/JPS5965476A/en
Publication of JPS5965476A publication Critical patent/JPS5965476A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/452—Ohmic electrodes on AIII-BV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/05105—Gallium [Ga] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/0518—Molybdenum [Mo] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To secure excellent bondability for the titled semiconductor device by a method wherein the bonding pad of gallium is formed by providing a wiring in such a manner that a bonding metal is extended to the point above the insulating film located on a semiconductor substrate, thereby enabling to provide a long diffusion distance between the gallium and the bonding pad. CONSTITUTION:An N type region 7 is formed on a gallium arsenide substrate 6 by performing a selective ion implantation, and then a low temperature oxide film 8 and an electrode hole 9 are formed. Then, a gold-germanium alloy film (ohmic metal) 10 is formed on said electrode hole 9 by performing a vapor-deposition, a platinum film (high melting point metal) 11 is vapor-deposited, and a patterning is performed on the ohmic metal 10 and the high melting point metal 11. Subsequently, a heat treatment is performed for the formation of an ohmic contact. As a result, the ohmic contact between the N type region and the alloy film 10 is formed, and an aluminum film 12 is vapor-deposited thereon. This aluminum film 12 is contacted by covering a metal 11 and, at the same time, a bonding metal pad is formed by extending said aluminum film 12 on the low temperature oxide film 8.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は半導体装置、特にガリウムを含有した半導体基
板を用いた半導体装置の電極のボンディング性を良好に
しうる技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a technique for improving the bonding properties of electrodes of a semiconductor device, particularly a semiconductor device using a semiconductor substrate containing gallium.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

半導体装置において、電極のオーミックコンタクトはコ
ンタクトメタルを蒸着した後、熱処理を施すこ□とによ
って得ることができる。このコンタクトメタルとしては
、例えば半導体基板がガリウム砒素あものである場合、
金とゲルマニウムの合金が用いられる。ところで、この
オーミックコンタクトを形成する際、半導体基板中にガ
リウムが含有されていると、当該ガリウムが電極表面に
偏析してしまい、組立時におけるワイヤボンディングの
接着性が著しく低下するという問題がある。In a semiconductor device, an ohmic contact between electrodes can be obtained by depositing a contact metal and then subjecting it to heat treatment. For example, when the semiconductor substrate is made of gallium arsenide, the contact metal may be
An alloy of gold and germanium is used. By the way, when forming this ohmic contact, if gallium is contained in the semiconductor substrate, there is a problem that the gallium segregates on the electrode surface and the adhesion of wire bonding during assembly is significantly reduced.

かかる欠点を防止するため、従来では次のような手法を
用いていた。すなわち、第１図に示すように、ホニル□
素子゛の場合、ボンディングメタル４とオーミックコン
タクトメタル２との間に高融点メタル３を介在させ、半
導体基板ｌからのガリウムの拡散を防止する構造として
いた。なお、５は絶縁用の酸化膜を示している。In order to prevent such drawbacks, the following methods have conventionally been used. That is, as shown in Figure 1, Honil □
In the case of the device, a high melting point metal 3 was interposed between the bonding metal 4 and the ohmic contact metal 2 to prevent gallium from diffusing from the semiconductor substrate 1. Note that 5 indicates an oxide film for insulation.

しかしながら、上記従来の構造をとったとしても、依然
メして組立時の熱履歴などによるガリウムの拡散を効果
的に阻止することができず、そのためワイヤーボンディ
ングを良好に行ない得ないという問題があった。However, even with the above conventional structure, it is still not possible to effectively prevent gallium diffusion due to thermal history during assembly, and therefore wire bonding cannot be performed properly. Ta.

〔発明の目的〕[Purpose of the invention]

そこで、本発明はガリウムを含有する半導体装、　　置
において、良好なボンディング性を有する電極を具備す
る半導体装置を提供することを目的とする。Therefore, an object of the present invention is to provide a semiconductor device containing gallium, which is provided with an electrode having good bonding properties.

〔発明の概要〕[Summary of the invention]

上記目的を達成するために、本発明の半導体装置ハ、ボ
ンデインクメタルを半導体基板上の絶縁膜上まで延在さ
せて配線することによりガリウムのポンディングパッド
を形成し、それによってガリウムとポンディングパッド
までの拡散距離を長く形成した点に特徴を有する。In order to achieve the above object, the semiconductor device of the present invention (c) forms a gallium bonding pad by extending and wiring a bonded ink metal onto an insulating film on a semiconductor substrate, thereby bonding the gallium and bonding pads. It is characterized by a long diffusion distance to the pad.

〔発明の効果〕〔Effect of the invention〕

上記した構成を有する本発明によれば、ガリウムのボン
ティングパッドまでの拡散距離を長く形成したことによ
り、組立時の加熱に伴って生じるガリウムの拡散が半導
体基板の上面にとどまってポンディングパッドまで及ば
ないため、ポンディングパッドが合金化されず、したが
って極めて良好なボンディング性を確保することができ
る。According to the present invention having the above configuration, by forming a long diffusion distance of gallium to the bonding pad, the diffusion of gallium caused by heating during assembly remains on the upper surface of the semiconductor substrate and reaches the bonding pad. Therefore, the bonding pad is not alloyed, and therefore extremely good bonding properties can be ensured.

〔発明の実施例〕[Embodiments of the invention]

以下、図面を参照して本発明の一実施例について説明す
る。An embodiment of the present invention will be described below with reference to the drawings.

第２図に示すように、ガリウム砒素基板（以下、単に基
板という。）ｇ゛に選択的なイオン打込みによってＮ影
領域７を形成し、次に低温酸化膜８を形成し次に電極孔
９を形成する。次いで、電極孔９に金とゲルマニウムと
の合金膜（オーミツクメｌ　ル）　１０を３ｏｏｏＸの
厚さで蒸着により形成し、かつ白金膜（高融点メタル）
１】を１ｏｏｏＸの厚さで林着し、これらオーミックメ
タル１０および高融点メタル１１のパターニングを行う
。As shown in FIG. 2, an N shadow region 7 is formed on a gallium arsenide substrate (hereinafter simply referred to as a substrate) by selective ion implantation, then a low temperature oxide film 8 is formed, and then an electrode hole 9 is formed. form. Next, a gold and germanium alloy film (ohmic metal) 10 is formed in the electrode hole 9 to a thickness of 300X by vapor deposition, and a platinum film (high melting point metal) is formed in the electrode hole 9.
1] is deposited to a thickness of 1oooX, and these ohmic metals 10 and high melting point metals 11 are patterned.

次に第３図に示すように、４００Ｃの水素雰囲気中にて
５分間、オーミックコンタクト形成のための熱処理を施
す。その結果、Ｎ影領域７と合金膜１０とがオーム性接
触が形成される。次に、その上ニアルミニウム膜１２を
１μｍの厚さで蒸着する。Next, as shown in FIG. 3, heat treatment is performed for 5 minutes in a hydrogen atmosphere at 400 C to form an ohmic contact. As a result, ohmic contact is formed between the N shadow region 7 and the alloy film 10. Next, a NiAluminum film 12 is deposited thereon to a thickness of 1 μm.

このアルミニウム膜１２は高融点メタル１１を祷って接
触するとともに低温酸化膜８上に延在させてボンディン
グメタルパッドを形成する。This aluminum film 12 is in contact with the high melting point metal 11 and extends over the low temperature oxide film 8 to form a bonding metal pad.

かくして、アルミニウム膜１２を延在させたことによシ
、ガリウムのポンディングパッド１２までの拡散距離が
長くなり、ポンディングパッド１２０合金化な防止でき
る。その結果、良好なボンディング性を確保しうるもの
である。Thus, by extending the aluminum film 12, the diffusion distance of gallium to the bonding pad 12 becomes longer, and it is possible to prevent the bonding pad 120 from forming an alloy. As a result, good bonding properties can be ensured.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のホール素子の協□極構造を示す縦断面、 第２−１、第３図は本発明による半導体装置の構造を製
造工程順に示しｆＣ縦断面図でるる。 ６・・・半導体基板 ８・・・低温酸化膜 ９・・・開孔部 １０・・・合金膜（オーミックメタル）１１・・・高融
点メタル １２・・・アルミニウム膜（ボンディングメタル）出願
人代理人　　猪　股　　　清 燃　（図 馬２　図 ５３　図FIG. 1 is a vertical cross-sectional view showing the cooperative electrode structure of a conventional Hall element, and FIGS. 2-1 and 3 are fC vertical cross-sectional views showing the structure of a semiconductor device according to the present invention in the order of manufacturing steps. 6...Semiconductor substrate 8...Low temperature oxide film 9...Opening portion 10...Alloy film (ohmic metal) 11...High melting point metal 12...Aluminum film (bonding metal) Applicant's representative person boar

Claims (1)

【特許請求の範囲】[Claims] ガリウムを含有する半導体基板と、この半導体基板上に
設けられ一部に開孔を有する絶縁膜と、前記開孔に設け
られたオーミックメタルと、このオーミックメタル上に
設けられた高融点メタルと、この高融点メタルを覆って
接触しつつ前記絶縁膜上に延在されたボンディングメタ
ルと、を備えたことを特徴とする半導体装置。a semiconductor substrate containing gallium, an insulating film provided on the semiconductor substrate and having a hole in a portion, an ohmic metal provided in the hole, and a high melting point metal provided on the ohmic metal; A semiconductor device comprising: a bonding metal extending over the insulating film while covering and contacting the high melting point metal.
JP17666482A 1982-10-07 1982-10-07 Semiconductor device Pending JPS5965476A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17666482A JPS5965476A (en) 1982-10-07 1982-10-07 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17666482A JPS5965476A (en) 1982-10-07 1982-10-07 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5965476A true JPS5965476A (en) 1984-04-13

Family

ID=16017540

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17666482A Pending JPS5965476A (en) 1982-10-07 1982-10-07 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5965476A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02143531A (en) * 1988-11-25 1990-06-01 Hitachi Ltd Semiconductor device
EP0460531A1 (en) * 1990-06-07 1991-12-11 Siemens Aktiengesellschaft Contact metallisation on semiconductor material
WO2022230250A1 (en) * 2021-04-30 2022-11-03 ソニーセミコンダクタソリューションズ株式会社 Production method for semiconductor device and semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02143531A (en) * 1988-11-25 1990-06-01 Hitachi Ltd Semiconductor device
EP0460531A1 (en) * 1990-06-07 1991-12-11 Siemens Aktiengesellschaft Contact metallisation on semiconductor material
WO2022230250A1 (en) * 2021-04-30 2022-11-03 ソニーセミコンダクタソリューションズ株式会社 Production method for semiconductor device and semiconductor device

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