JPS5897841A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5897841A
JPS5897841A JP56196488A JP19648881A JPS5897841A JP S5897841 A JPS5897841 A JP S5897841A JP 56196488 A JP56196488 A JP 56196488A JP 19648881 A JP19648881 A JP 19648881A JP S5897841 A JPS5897841 A JP S5897841A
Authority
JP
Japan
Prior art keywords
emitter
check pattern
region
aperture
width
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56196488A
Other languages
Japanese (ja)
Inventor
Shuji Kanamori
金森　修二
Masao Honjo
本城　眞佐雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56196488A priority Critical patent/JPS5897841A/en
Publication of JPS5897841A publication Critical patent/JPS5897841A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To allow the detection of the yield in a halfway process, by providing a region having the width approx. the same as that of an emitter region of the element part in a lattice form on a check pattern. CONSTITUTION:An emitter aperture part in a lattice form is immediately under a polycrystalline Si 60, and the emitter width is the same as that of the element part. In other words, an insulation oxide film 40 is formed on a substrate 10 having the base region 30, and, at the same time as the formation of emitter aperture, an aperture is applied on the check pattern part. Thereat, the width of the aperture of the check pattern part is designed the same width as the emitter aperture of the element part and formed in a lattice form. The probe for measurement can be contacted on a polycrystalline Si layer 60. With the polycrystalline Si layer 60 as the diffusion source, an emitter region 70 is formed. Therefore, if the emitter region of the element part is not omitted, the emitter aperture is not applied even in a check pattern resulting in an open state. Accordingly, the electrical characteristic is not allowed, and thus an omission state can be confirmed.

Description

【発明の詳細な説明】 本発明は半導体装置に関し、特に超高周波微細素子のチ
ェ、クパターンに−するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and in particular to a check pattern of ultra-high frequency fine elements.

超高周波用のトランジスタは、その特性上の要求からベ
ース、エミッタ間距離やエミ、り幅ヲ狭くすると同時に
拡散深さを浅くする必要がある。Due to the characteristics requirements of ultra-high frequency transistors, it is necessary to reduce the base-emitter distance and emitter width as well as the diffusion depth.

このため、エミッタ不純物を含んだ多結晶シリコンをエ
ミッタ拡散源として使う技術が知られている。又、二定
ツタ及びペースが微細パターンであることから引出し電
極構造になっておシ、このため、ウェハースの段進工程
での特性チェックのためにチェックパターンが会費であ
る。For this reason, a technique is known in which polycrystalline silicon containing emitter impurities is used as an emitter diffusion source. In addition, since the two fixed vines and paces are fine patterns, they have an extraction electrode structure, and therefore, check patterns are required for checking the characteristics in the wafer advancing process.

第１図（ａ）、Φ）は従来用いられているチェックパタ
ーンの正面図及びＡ−Ａ’方向構造断面図である。すな
わち、Ｎ型基板１にチェックパターン部のペース領域と
なるＰ型不純物領域３′　を選択拡散法によシ形成する
。このベース領域形成は、熱拡散法よシもイオン注入法
によ〕不純物拡散を行った方が浅い接合を安定に形成す
ることができる。FIG. 1(a), Φ) is a front view and a cross-sectional view of the structure in the direction AA' of a conventionally used check pattern. That is, a P-type impurity region 3', which will become a space region for a check pattern portion, is formed on an N-type substrate 1 by selective diffusion. In forming this base region, a shallow junction can be stably formed by performing impurity diffusion by thermal diffusion method or by ion implantation method.

次に、Ｎ型エミッタ不純物を含んだ多結晶シリコンＮＪ
Ｉ６’　　よシ拡散を行うことによシチェックパターン
部のＮ型エミッタ領域７′　が形成され、ＮＰＮ型トラ
ンジスタ構造が得られる。このチェックパターンによシ
１、ウニ１１−ス製造工程での逆耐電圧、直流電流増幅
率ｈＦＦｉ　等の電気的特性を確認することができ、途
中工程での品質管理を行うことができる。Next, polycrystalline silicon NJ containing N-type emitter impurities
By diffusing I6', an N-type emitter region 7' of the check pattern portion is formed, and an NPN-type transistor structure is obtained. By using this check pattern, electrical characteristics such as reverse withstand voltage and DC current amplification factor hFFi can be confirmed during the manufacturing process of the base 1 and the sea urchin 11, and quality control can be performed during intermediate processes.

第２図（ａ）〜（１）は従来のチェ、クパターンを有す
る素子部の脚造工穣を示す構造断Ｗｉ図である。す＆１
）ち、Ｎ１１＃−導体＆＆１主１１１Ｋｊ８縁駿化展２
をマスクとして選択拡散法によシペース領域３を形成す
る。このときのベース接合深さを〜ＩＰ相度とするため
、イオン注入法が用いられる。次に、肥縁酸化農４を成
長するわけだが、このときベース接合が大きく動かない
ために極力低温で成長するのが望ましい（第２図（Ｃ）
）。FIGS. 2(a) to 2(1) are structural cross-sectional views showing the leg construction of an element portion having a conventional checkered pattern. Su&1
) N11#-Conductor &&1 Main 111Kj8 Enshunka Exhibition 2
The space region 3 is formed by a selective diffusion method using as a mask. In order to set the base junction depth at this time to ~IP phase, an ion implantation method is used. Next, the Ferment Oxidation Plant 4 is grown, but at this time it is desirable to grow it at as low a temperature as possible so that the base junction does not move significantly (Fig. 2 (C)
).

チェックパターンのベース領域社、第２図（ロ）によシ
絶縁駿化膜２を開孔し、素子部と同時にイオン注入によ
１形成される。第２図（ｄ）は写真蝕刻法によシエミッ
タ領域のための開孔を絶縁ｊｉ４に施したところである
。チェックパターン部のエミッタ用開孔も同時に形成さ
れている。超高周波トランジスタの工れ、ツタ幅は〜ｌ
ｐｍ程度である。従って、抜は幅のコントロールが非常
に難しいため歩留りはこの工程で決定される。これに比
しチェ、クパターンのエミッタ領域紘探針による測定を
可能にするため、数＋μｍと大きい。そζで、エミッタ
形成用の絶縁酸化ｊ［４に形成されるチェックパターン
部の開孔も大壷い。この倉め、Ａ−、’−オ素子１１１
０エイツタ用一孔が鉋けていなくて１、チェックパター
ン部のそれ紘簡単に抜けることになシ、この結果素子部
の特性歩留シを推定するの拡不可能である。In the base region of the check pattern, as shown in FIG. 2(b), a hole is formed in the insulating film 2, and 1 is formed by ion implantation at the same time as the element portion. FIG. 2(d) shows a hole formed in the insulation ji4 for the emitter region by photolithography. Emitter openings in the check pattern section are also formed at the same time. The machining and vine width of ultra-high frequency transistors is ~l
It is about pm. Therefore, since it is very difficult to control the width during punching, the yield is determined by this process. In comparison, the emitter region of the check pattern is large, several micrometers, in order to enable measurement using a probe. Therefore, the opening in the check pattern portion formed in the insulating oxide layer J[4 for emitter formation is also large. This store, A-,'-O element 111
Since the hole for the 0-eighter is not drilled, the hole in the check pattern part cannot be easily drilled out, and as a result, it is impossible to estimate the characteristic yield of the element part.

次にエミッタ拡散源となるＮｇ不純物を含んだ多結晶シ
リコン層５を形成しく第２図（ｅ）　）　、写真蝕刻法
によシエミッタ闘孔部を覆う所定のパターンの多結晶シ
リコン層６を形成する・（第２図（ｆ））。Next, a polycrystalline silicon layer 5 containing Ng impurities, which will serve as an emitter diffusion source, is formed (FIG. 2(e)), and a polycrystalline silicon layer 6 with a predetermined pattern covering the emitter hole is formed by photolithography. (Figure 2 (f)).

このときのエツチング方法は、ウェットエッチよシもド
ライエッチの方が抜は幅バラツキが小さいため用いられ
ている。As for the etching method used at this time, dry etching is used because it has smaller width variations than wet etching.

１１２図＠紘、チェックパターンによシミ魚釣特性を測
定しながら所定のエミッタ接合を有するエミッタ領域７
を形成している所である。このときのエミッタ開孔窓は
抜けがばらついているがチェックパターンでは、特性バ
ラツキを推定できない。Figure 112 @Hiro, Emitter region 7 with a predetermined emitter junction while measuring stain fishing characteristics by check pattern
It is the place where the At this time, the emitter aperture window varies in its omission, but the check pattern cannot estimate the variation in characteristics.

第２図（ｈ）はベースコンタクト用の窓あけを行った所
、第２図（り社エミッタ、ベー　ス１１＆８，９ｔ−形
成した所である。Figure 2(h) shows the location where the window for the base contact was made, and Figure 2(h) shows the location where the emitter bases 11 & 8, 9t were formed.

以上のように１超高周波トランジスタは〜１μｍ程度の
エミツタ幅で複数のスリットを有してお）、エミッタ形
成工程での抜は輻コントロールが離しいにもかかわらず
、チェックパターン部のエミッタ用一孔が大きいために
素子部の電気的特性をチェックパターンによシ検出でき
ず、との結果、歩留シが低迷していた。As mentioned above, one ultra-high frequency transistor has an emitter width of about 1 μm and multiple slits), and although it is difficult to control the radiation in the emitter formation process, the emitter width in the check pattern area is Because the holes were large, the electrical characteristics of the element part could not be detected using the check pattern, resulting in low yields.

本発明の目的は、従来の製造方法でチェックパターンの
構造を変えることによシ途中工程での歩留シを検出する
ことが可能なチェックパターンを有する半導体装置を提
供することになる。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a check pattern that can detect yield failure in an intermediate process by changing the structure of the check pattern using a conventional manufacturing method.

すなわち本発明によるチェックパターン紘、素子部のエ
ミッタ領域と＃１ぼ同じ幅を有する領域を格子状に設け
たもので、以下図面←よシ本発明を詳述する。That is, the check pattern according to the present invention is formed by providing a region having a width approximately the same as the emitter region of the element portion in a grid pattern.The present invention will be described in detail below with reference to the drawings.

第３図（ａ）、０））紘本発明の一実施例を示すチェッ
クパターンの正面図及びＡ−＾方向構造断面図である。FIG. 3(a), 0)) Hiro is a front view and a cross-sectional view of the structure in the A-^ direction of a check pattern showing an embodiment of the present invention.

図中、多結晶シリコン６０の直下は格子形の工きツタ開
孔部を有している。このときのエミッタ幅鉱素子部のそ
れと同じである。すなわち、ｊＩ２図と同様な製法でベ
ース領域３０を有する基板ｌＯ上に絶縁酸化１！４０を
形成し、エミッタ川霧孔形成と同時にチェックパターン
部ＫＭ孔を施す。このとき、チェックパターン部の開孔
の幅を素子部のエミッタ用開孔と同じ幅に設計し、かつ
第３図（ａ）のように格子状にする。チェックパターン
部の開孔な格子状にするのは、通常チェックパターン部
が素子部よシもその面積が小さいため、エミッタ周囲長
を大きくして素子部の電流層Ｉ＠率ｂＦＩ特性尋によシ
近い特性として素子部の電気的特性を検知するためであ
る。また、絢定用の探針は多結晶シリコン層６０にあて
れによい。この多結晶シリコン層６０を拡散源としてエ
ミッタ領域７０を形成する。In the figure, directly below the polycrystalline silicon 60 is a lattice-shaped ivy opening. The emitter width is the same as that of the mineral element portion at this time. That is, an insulating oxide film 1!40 is formed on the substrate IO having the base region 30 by the same manufacturing method as shown in FIG. At this time, the width of the apertures in the check pattern section is designed to be the same width as the emitter apertures in the element section, and is shaped like a lattice as shown in FIG. 3(a). The reason why the check pattern part is made into an open lattice shape is because the area of the check pattern part is usually smaller than that of the element part. This is to detect the electrical characteristics of the element portion as characteristics similar to those shown in FIG. In addition, the probe for measurement can be easily applied to the polycrystalline silicon layer 60. Emitter region 70 is formed using polycrystalline silicon layer 60 as a diffusion source.

従って、素子部のエミッタ領域が抜けていなければチェ
ックパターンでもエミッタ細孔がなされずにオープン状
態となるため、電゛気的特性が不可能となシ抜は状１の
確動が可能である。また、ウェハース内での特性バラツ
キも推定することが可能となる。さらに、素子部と同じ
エミツタ幅を有している丸めエミッタ・ベース接合の曲
率は等しくなシ、従来のチェックパターンと素子部の電
気的特性相関バラツキが小さくなるため積置の良いコン
トロールが可能となる。Therefore, if the emitter region of the element part is not missing, the emitter pore will not be formed even in the check pattern and will be in an open state, so it is possible to ensure the hole is in the state 1 where the electrical characteristics are impossible. . Furthermore, it is also possible to estimate variations in characteristics within a wafer. Furthermore, the curvature of the rounded emitter-base junction, which has the same emitter width as the element part, is equal, which reduces the variation in electrical characteristics between the conventional check pattern and the element part, making it possible to better control the stacking. Become.

以上、ＮＰＮトランジスタによシ本実施例を説明し九が
ＰＮＰ　）ランジスタでも同・様であることは言うまで
もない。The present embodiment has been described above using an NPN transistor, but it goes without saying that the same applies to a PNP transistor.

【図面の簡単な説明】[Brief explanation of the drawing]

１１１図（ａ）、（ｂ）は従来のチェックパターン部の
平面図およびｈ−Ｒ方向断面図でおる。第２図（ａ）乃
至（ｉ）＃ｉ超為周波用トランジスタの素子部を示す製
造工程断向図である。第３図（ａ）、Φ）は本発明の一
実施例を示すチェックパターン部の平面図およびＡ−Ａ
＠方向断面図である。 １・・・Ｐ蓋基板（コレクタ）、２，４，４０・・・・
・艶縁酸化婁、３・・・素子部のベース領域、３’、３
０ζ・・チェックパターン部のベース領域、５・・・多
結晶シリコン層、６・・・素子部のエミッタ用多結晶シ
リコン層、６．６０・・・チェックパターン部のエミッ
タ用多結晶シリコン層、７・・・素子部のエミッタ領域
、７’、７０・・・チェックパターン部のエミッタ領域
、８・・・エミッタ電極、９・・・ベース電極。 （α） （ｂン ＣＣ） （ｉｌ） （ｅ） ＜ｊ） （ｇ） （Ｌ） ！＃２　図FIGS. 111(a) and 111(b) are a plan view and a sectional view taken along the line h-R of a conventional check pattern section. FIGS. 2(a) to 2(i) are sectional views showing the manufacturing process of the element part of the #i ultratransistor frequency transistor. FIG. 3(a), Φ) is a plan view of a check pattern section showing an embodiment of the present invention, and A-A
It is a sectional view in the @ direction. 1...P lid substrate (collector), 2, 4, 40...
・Glossy edge oxidation, 3...Base area of element part, 3', 3
0ζ...Base region of check pattern section, 5...Polycrystalline silicon layer, 6...Polycrystalline silicon layer for emitter of element section, 6.60...Polycrystalline silicon layer for emitter of check pattern section, 7... Emitter region of element section, 7', 70... Emitter region of check pattern section, 8... Emitter electrode, 9... Base electrode. (α) (bn CC) (il) (e) <j) (g) (L)! #2 Diagram

Claims (1)

【特許請求の範囲】[Claims] 不純物を有する多結晶半導体層下の絶縁〜に設けられた
周孔が素子部の多結晶半導体層下の絶縁層に設けられた
それと＃よは同じ幅を有し、かつ格子状に設けられてい
るチェックパターンを有することを特徴とする半導体装
置。The peripheral holes provided in the insulating layer under the polycrystalline semiconductor layer containing impurities have the same width as those provided in the insulating layer under the polycrystalline semiconductor layer of the element portion, and are provided in a lattice shape. A semiconductor device characterized in that it has a check pattern.
JP56196488A 1981-12-07 1981-12-07 Semiconductor device Pending JPS5897841A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56196488A JPS5897841A (en) 1981-12-07 1981-12-07 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56196488A JPS5897841A (en) 1981-12-07 1981-12-07 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5897841A true JPS5897841A (en) 1983-06-10

Family

ID=16358609

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56196488A Pending JPS5897841A (en) 1981-12-07 1981-12-07 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5897841A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS492485A (en) * 1972-04-19 1974-01-10
JPS5099271A (en) * 1973-12-28 1975-08-06

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS492485A (en) * 1972-04-19 1974-01-10
JPS5099271A (en) * 1973-12-28 1975-08-06

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