JPS5896737A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5896737A JPS5896737A JP19826481A JP19826481A JPS5896737A JP S5896737 A JPS5896737 A JP S5896737A JP 19826481 A JP19826481 A JP 19826481A JP 19826481 A JP19826481 A JP 19826481A JP S5896737 A JPS5896737 A JP S5896737A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- mask
- film
- patterns
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000000034 method Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 239000011521 glass Substances 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 4
- 150000004767 nitrides Chemical class 0.000 claims description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 230000001590 oxidative effect Effects 0.000 claims 1
- 238000007796 conventional method Methods 0.000 abstract description 3
- 230000007423 decrease Effects 0.000 abstract description 3
- 239000010408 film Substances 0.000 abstract 8
- 230000003247 decreasing effect Effects 0.000 abstract 3
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 2
- 239000010409 thin film Substances 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 8
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Weting (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は半導体装置の製造方法、特に酸化膜段差部で
の焼付は解像力を向上させるだめの方法に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for improving resolution by printing on stepped portions of an oxide film.
一般に半導体装置９例えば高周波トランジスタにおいて
は、高周波特性の向上を図るために、ボンディングパッ
トなどの外部電極配線領域直下の酸化膜をできる限９厚
く設計するのが有利であるが、一方、酸化膜厚が厚くな
ればなるほど大きな酸化膜段差を生じ、活性化領域のパ
ターン形成が困難になる。すなわち、従来は、ベースオ
ーミックコンタクトの開孔部直下に、この開口部と同程
度の大きさのパターンで、ベース領域よりも高濃度の異
なる導電性の拡散領域を形成して、ベース抵抗を下げる
方法が採用されており、この拡散領域は通常、微細パタ
ーンに設計され、これが微細になればなるほど酸化膜厚
を薄くしなければならず、また反面、前記したように外
部電極配線領域直下の酸化膜厚はできる限り厚くする必
要がある。Generally, in a semiconductor device 9, for example, a high frequency transistor, it is advantageous to design the oxide film directly under the external electrode wiring area such as the bonding pad 9 to be as thick as possible in order to improve the high frequency characteristics. The thicker the oxide film becomes, the larger the oxide layer step becomes, making it difficult to pattern the active region. In other words, conventionally, a diffusion region of a different conductivity with a higher concentration than the base region is formed directly under the opening of the base ohmic contact in a pattern of the same size as the opening to lower the base resistance. This diffusion region is usually designed into a fine pattern, and the finer the pattern, the thinner the oxide film must be. The film thickness needs to be as thick as possible.
そしてこれらの双方を満足させるために、最近の高周波
トランジスタでは、第１図（ａ）および（ｂ）に示すよ
うに、外部電極配線領域に該当する半導体基板（１）上
の酸化膜（２ａ）のみを厚く、活性領域に該当する酸化
膜（２ｂ）をその上に薄く形成する。In order to satisfy both of these requirements, recent high-frequency transistors have an oxide film (2a) on the semiconductor substrate (1) corresponding to the external electrode wiring area, as shown in FIGS. 1(a) and (b). A thin oxide film (2b) corresponding to the active region is formed thereon.
またこの状態で前記拡散領域を形成するのには、第１図
（ｂ）にみられるように、ホトレジスト膜（３）。Further, in order to form the diffusion region in this state, as shown in FIG. 1(b), a photoresist film (3) is used.
普通は０ＭＲ８３レジストを塗布し、その上にガラスマ
スク（４）を密着させ、例えば紫外線（５）を照射して
焼付けを行なう。こ＼で（１）はガラスマスク（４）に
設けられたパターン寸法である。そしてまたこのように
ガラスマスクを通して紫外線を照射するマスクアライメ
ント装置には、一般に密着露光方式と投影露光方式とが
あるが、高周波トランジスタのように焼付は解像力を重
要視する半導体素子には前者密着露光方式によるマスク
アライメント装置が利用される。しかしこの装置を用い
た場合にも、焼付けに使用される紫外線（５）が完全な
平行光線でないために、ガラスマスクとホトレジストの
密着性が悪いと、焼付は解像力の低下を免れず、このだ
めに前記したように酸化膜段差が大きい場合には、当然
密着力が悪くなって設計通りのパターンを得られなくな
る。すなわち、第１図（ｃ）は前記焼付は後、現像、酸
化膜エツチング、ホトレジスト除去などの工程を経て得
た拡散領域形成のためのパターン（６）を示している。Normally, an 0MR83 resist is applied, a glass mask (4) is placed on top of the resist, and then, for example, ultraviolet light (5) is irradiated to perform baking. Here, (1) is the pattern dimension provided on the glass mask (4). Mask alignment equipment that irradiates ultraviolet rays through a glass mask generally includes a contact exposure method and a projection exposure method, but the former is used for semiconductor devices such as high-frequency transistors, where printing is focused on resolution. A mask alignment device based on this method is used. However, even when using this device, the ultraviolet rays (5) used for printing are not perfectly parallel rays, so if the adhesion between the glass mask and the photoresist is poor, the printing will inevitably result in a decrease in resolution. As mentioned above, if the oxide film level difference is large, the adhesion will naturally deteriorate, making it impossible to obtain a pattern as designed. That is, FIG. 1(c) shows a pattern (6) for forming a diffusion region obtained after the above-mentioned baking through steps such as development, oxide film etching, and photoresist removal.
この拡散領域の設計寸法は、とりも直さずガラスマスク
（４）でのパターン寸法（１）であるが、こ＼で得たパ
ターン（６）の寸法（１１）は、酸化膜段差などにより
密着力が低下して露光かぶりを生ずるためにかなり小さ
な寸法（ｌ〉１１）となり、寸法基準単位が１μｍ前後
になると、もはや解像できなくなって、この状態ではさ
きに述べたベースオーミックコンタクト直下の拡散領域
形成が不能となるものでおった。The design dimensions of this diffusion region are the pattern dimensions (1) of the glass mask (4), but the dimensions (11) of the pattern (6) obtained here are due to the close contact due to the oxide film step etc. As the power decreases and exposure fog occurs, the dimensions become quite small (l>11), and when the dimension standard unit becomes around 1 μm, it is no longer possible to resolve, and in this state, the diffusion directly below the base ohmic contact mentioned earlier. This made it impossible to form a region.
この発明は従来のこのような欠点を改善するためになさ
れたものであり、以下、この発明に係わる半導体装置の
製造方法の一実施例を、第２図（ａ）ないしｆｇ）を参
照して詳細に説明する。This invention was made to improve these conventional drawbacks, and an embodiment of the method for manufacturing a semiconductor device according to the invention will be described below with reference to FIGS. 2(a) to 2f). Explain in detail.
この第２図（ａ）ないしくｇ）はこの実施例方法を工程
順に示している。この実施例方法では、まず半導体基板
（１）上に窒化膜（２１）を形成した上で、この窒化膜
（２１）上の活性領域形成部に相当する部分にホトレジ
スト膜（３）を残しく同図（ａ））、かっこのホトレジ
スト膜（３）をマスクにして、例えばプラズマエツチン
グなどのドライプロセス技術によシ、活性領域形成部以
外の窒化膜（２１）を部分的２選択的にエツチング除去
する（同図（ｂ））。FIGS. 2(a) to 2(g) show the method of this embodiment in the order of steps. In this embodiment method, a nitride film (21) is first formed on a semiconductor substrate (1), and then a photoresist film (3) is left on the nitride film (21) in a portion corresponding to the active region formation portion. In the same figure (a), using the photoresist film (3) in parentheses as a mask, the nitride film (21) other than the active region forming area is partially selectively etched by dry process technology such as plasma etching. ((b) in the same figure).
ついでこの状態で熱酸化を行なう。すなわち。Then, thermal oxidation is performed in this state. Namely.
窒化膜（２１）を残して熱酸化すると、窒化膜（２１）
で被われた部分、換言すると活性領域形成部には酸素が
供給されず酸化が進行しないが、それ以外の部分、この
場合は外部電極配線領域形成部には窒化膜（２１）がな
くて酸化が進行し、厚い酸化膜（２ａ）が形成され（同
図（ｃ））、その後、残されて不要となる窒化膜（２１
）を適宜に除去する（同図（ｄ））。When thermally oxidized leaving the nitride film (21), the nitride film (21)
In other words, oxygen is not supplied to the active region formation area and oxidation does not proceed, but other parts, in this case the external electrode wiring area formation area, do not have the nitride film (21) and oxidation does not occur. progresses, a thick oxide film (2a) is formed (FIG. 2(c)), and then an unnecessary nitride film (21) is left behind.
) is removed as appropriate ((d) in the same figure).
しかしてこの場合、同図（ｄ）からも明らかなように、
酸化膜（２ａ）は、シリコン基板（１）の界面（力を中
心にして、基板（１）の内側と外側とに亘って形成され
ることになり、その厚さを例えば１ｏ、ｏｏｏＡとする
と、前記した従来の場合には、この厚さ１０．０ＯＯＡ
がそのま＼酸化膜段差となっていたが、この例の場合に
は、通常、基板内側へ４．ｏｏｏｉ、外側へ６．ｏｏｏ
Ｘ、程度づつ酸化されることになり、こ＼での酸化膜段
差は６，０００λ程度、すなわち従来のＸ程度となる。However, in this case, as is clear from the same figure (d),
The oxide film (2a) will be formed at the interface (force) of the silicon substrate (1), on the inside and outside of the substrate (1), and if its thickness is, for example, 1o, oooA. , in the conventional case described above, this thickness is 10.0OOA.
However, in this example, 4. is normally applied to the inside of the substrate. oooi, outward 6. ooooo
The oxide film is oxidized by a degree of X, and the oxide film step difference here is about 6,000λ, that is, about X of the conventional one.
次に前記したとおり、高周波トランジスタにおいてはそ
の高周波特性を向上させるため、ベースオーミック開孔
部直下にこれと同程度の大きさのパターンで、ベース領
域よりも高濃度の拡散領域を形成してそのベース抵抗を
下げる目的のもとに、これらの上にさらに酸化膜（２ｂ
）を形成する（同図（Ｃ））。さらに続いてこの酸化膜
（２ｂ）上には従来と同様にしてホトレジスト膜（３）
を塗布し、かつこれにガラスマスク（４）を密着させ、
マスクアライメント装置で紫外線（５）を照射して焼付
けを行ない（同図（ｆ））、その後、現像、酸化膜エツ
チング、ホトレジスト除去などの工程を経て、拡散領域
形成のだめのパターン（６）を得る（同図（ｇ））。こ
＼で得られたパターン（６）の寸法は、ガラスマスク（
４）に設定されているパターン寸法（１）とほとんど同
じ寸法（４）となる。すなわち、少なくとも（ｌ＞４ン
Ｉｔ ）の関係にある。Next, as mentioned above, in order to improve the high-frequency characteristics of a high-frequency transistor, a diffusion region with a higher concentration than the base region is formed in a pattern of about the same size just below the base ohmic opening. For the purpose of lowering the base resistance, an oxide film (2b
) is formed ((C) in the same figure). Furthermore, a photoresist film (3) is formed on this oxide film (2b) in the same manner as before.
and apply a glass mask (4) on it,
Baking is performed by irradiating ultraviolet rays (5) with a mask alignment device ((f) in the same figure), and then through processes such as development, oxide film etching, and photoresist removal, a pattern (6) for forming a diffusion region is obtained. (Figure (g)). The dimensions of the pattern (6) obtained here are as follows:
The pattern size (4) is almost the same as the pattern size (1) set in 4). That is, there is a relationship of at least (l>4<It>).
従ってこの実施例方法の場合、このようにして形成され
る高周波トランジスタは、外部電極配線領域直下の酸化
膜を厚く形成しても、酸化膜段差が従来の約６割である
ために微細パターンの形成が容易で、高性能化を図り得
るのである。Therefore, in the case of the method of this embodiment, even if the oxide film directly under the external electrode wiring area is formed thickly, the high-frequency transistor formed in this way has a fine pattern because the oxide film step is about 60% of the conventional one. It is easy to form and can achieve high performance.
なお前記実施例は高周波トランジスタの製造について説
明したが、集積回路など、他の半導体装置の製造にも適
用できることは勿論である。Although the above embodiments have been described with respect to the manufacture of high-frequency transistors, it is of course applicable to the manufacture of other semiconductor devices such as integrated circuits.
以上詳述したようにこの発明方法によれば、従来方法に
比較して外部電極配線領域直下の酸化膜厚は同じであっ
ても、活性領域形成部との酸化膜段差を充分に小さくで
きるために、たとえ超微細パター７の焼付は形成におい
ても、従来はどの露光がぶりを生ずる慣れがなく、設計
値通りのパターン形成が容易に可能である。As detailed above, according to the method of the present invention, even if the thickness of the oxide film directly under the external electrode wiring area is the same as in the conventional method, the difference in level between the oxide film and the active region forming area can be made sufficiently small. In addition, even when forming the ultra-fine pattern 7 by printing, there is no conventional practice that any exposure causes blurring, and it is easy to form a pattern according to the designed value.
第１図（ａ）ないしくＣ）は従来例による高周波トラン
ジスタの製造工程を説明する断面図、第２図（ａ）ない
しくｇ）はこの発明方法の一実施例を適用した高周波ト
ランジスタの製造工程を順次に示す断面図である０
（１）・・・・半導体基板、（２ａ）、（ｚｂ）・・・
・酸化膜、（２１）・・・・窒化膜、（３）・・・・ホ
トレジスト膜、（４）・・・・ガラスマスク、（５）・
・・・紫外線、（６）・・・・パターン。
代理人 葛野信−（ほか１名）
第１図
第２図
第２図
１1(a) to C) are cross-sectional views illustrating the manufacturing process of a high-frequency transistor according to a conventional example, and FIGS. 2(a) to 2(g) show manufacturing of a high-frequency transistor using an embodiment of the method of the present invention. 0 (1)...Semiconductor substrate, (2a), (zb)...
・Oxide film, (21)...Nitride film, (3)...Photoresist film, (4)...Glass mask, (5)...
...Ultraviolet light, (6)...pattern. Agent Makoto Kuzuno (1 other person) Figure 1 Figure 2 Figure 2 Figure 1
Claims (1)
形成する工程と、ついでこれを熱酸化して前記活性領域
形成部以外の外部電極配線領域形成部に厚い酸化膜を形
成する工程と、残された前記窒化膜を除去する工程と、
これらの上に薄い酸化膜を形成する工程と、その後これ
らの上にホトレジスト膜を塗布し、ガラスマスクを密着
焼付けし、現像、酸化膜エツチングおよびホトレジスト
除去などを経て、前記薄い酸化膜上にパターン開孔部を
形成する工程とを含むことを特徴とする半導体装置の製
造方法。a step of selectively forming a nitride film on a portion corresponding to the formation of an active region on a semiconductor substrate; and a step of thermally oxidizing the nitride film to form a thick oxide film in a portion of the external electrode wiring region other than the active region formation portion. , removing the remaining nitride film;
A process of forming a thin oxide film on these, then coating a photoresist film on these, baking a glass mask in close contact with the film, developing, etching the oxide film, and removing the photoresist, and then forming a pattern on the thin oxide film. 1. A method of manufacturing a semiconductor device, comprising the step of forming an opening.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19826481A JPS5896737A (en) | 1981-12-04 | 1981-12-04 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19826481A JPS5896737A (en) | 1981-12-04 | 1981-12-04 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5896737A true JPS5896737A (en) | 1983-06-08 |
Family
ID=16388237
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19826481A Pending JPS5896737A (en) | 1981-12-04 | 1981-12-04 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5896737A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9513551B2 (en) | 2009-01-29 | 2016-12-06 | Digiflex Ltd. | Process for producing a photomask on a photopolymeric surface |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5344181A (en) * | 1976-10-05 | 1978-04-20 | Fujitsu Ltd | Production of semiconductor device |
| JPS553649A (en) * | 1978-06-22 | 1980-01-11 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Semiconductor device production |
-
1981
- 1981-12-04 JP JP19826481A patent/JPS5896737A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5344181A (en) * | 1976-10-05 | 1978-04-20 | Fujitsu Ltd | Production of semiconductor device |
| JPS553649A (en) * | 1978-06-22 | 1980-01-11 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Semiconductor device production |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9513551B2 (en) | 2009-01-29 | 2016-12-06 | Digiflex Ltd. | Process for producing a photomask on a photopolymeric surface |
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