JPS5891641A - Semiconductor device of high withstand voltage - Google Patents
Semiconductor device of high withstand voltageInfo
- Publication number
- JPS5891641A JPS5891641A JP18953381A JP18953381A JPS5891641A JP S5891641 A JPS5891641 A JP S5891641A JP 18953381 A JP18953381 A JP 18953381A JP 18953381 A JP18953381 A JP 18953381A JP S5891641 A JPS5891641 A JP S5891641A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- layer
- anionic
- impurity region
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000012535 impurity Substances 0.000 claims abstract description 15
- 125000000129 anionic group Chemical group 0.000 claims abstract description 9
- 230000010354 integration Effects 0.000 abstract description 7
- 239000000969 carrier Substances 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 32
- 230000015556 catabolic process Effects 0.000 description 14
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920003217 poly(methylsilsesquioxane) Polymers 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/408—Electrodes ; Multistep manufacturing processes therefor with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】 発明の技術分野 本発明は、高耐圧半導体装置に関する。[Detailed description of the invention] Technical field of invention The present invention relates to a high voltage semiconductor device.
発明の技術的背景とその問題点
従来、高耐圧半導体装置は、例えば第１図（４）及び同
図（Ｂ）に示す如く、Ｎｆｉ半導体層１，１′とｐｍ半
導体層２，２′とで形成されたＰＮ接合表面での電解集
中による局部的降伏を抑制して高耐圧を得るためにその
局面にメサ面３，３′を形成した構造を有している。而
して、メサ面３゜３／は、ガラス、シリコーン樹脂等の
絶縁部材で被覆されている。しかしながら、このような
メす構造を採用した高耐圧半導体装置は、製造時に基板
を構成するウエクの表面に凹凸ができ易く、所定の耐圧
を備えたものを高い歩留で製造できない欠点があった。Technical Background of the Invention and Problems Thereto Conventionally, high voltage semiconductor devices have been constructed using Nfi semiconductor layers 1, 1' and pm semiconductor layers 2, 2', as shown in FIG. 1 (4) and FIG. 1 (B), for example. In order to obtain a high breakdown voltage by suppressing local breakdown due to electrolytic concentration on the surface of the PN junction formed by the PN junction, it has a structure in which mesa surfaces 3 and 3' are formed on the surface of the PN junction. The mesa surface 3° 3/ is covered with an insulating material such as glass or silicone resin. However, high-voltage semiconductor devices that employ this type of female structure tend to have unevenness on the surface of the substrate that makes up the substrate during manufacturing, making it impossible to manufacture devices with a predetermined breakdown voltage at a high yield. .
このような欠点を解消するために（第２図に示す如（％
Ｎ型半導体基板４の所定領域にｐｖ不純物領域５を形成
し、この不純物領域５を囲むように所定間隔を設けてガ
ードリング層６ｔ−２重、３重に形成した高耐圧半導体
装置ｌが開発されている。このような高耐圧半導体装Ｗ
ｔＬは、第３図に示す如＜、’ｉｒ−トリ／ダ層ｄ・・
・６の数を仕様に応じて増加し、空乏層１の広がシを大
龜（することによりて耐圧の向上を図っているが、ガー
ドリング層６・・・６の増加に伴って素子の集積度が低
下する欠点がある。また、第４図に示す如く、不純物領
域５及びガードリング層６を含む半導体基板４０表ＥＩ
Ｋ形成された酸化膜９中にはＮａ 等が混入し易いた
め、このＮａ＋等による基板４内の多数キャリアの引き
寄せによって表面領域での空乏層８ａの広がシが小さぐ
なシ耐圧を低下する欠点がありた。In order to eliminate these drawbacks (as shown in Figure 2),
A high breakdown voltage semiconductor device 1 has been developed in which a PV impurity region 5 is formed in a predetermined region of an N-type semiconductor substrate 4, and a guard ring layer 6t--double or triple layer is formed at a predetermined interval so as to surround this impurity region 5. has been done. Such a high voltage semiconductor device W
tL is as shown in FIG.
・The number of guard ring layers 6 is increased according to the specifications, and the expansion of the depletion layer 1 is increased to improve breakdown voltage, but as the number of guard ring layers 6... Also, as shown in FIG.
Since Na, etc. are easily mixed into the K-formed oxide film 9, the depletion layer 8a spreads in the surface region due to the attraction of majority carriers in the substrate 4 by this Na+, etc., which lowers the withstand voltage. There was a drawback.
このためガードリング層６を設けた高耐圧半導体装置ｌ
において、集積度を上げてしかも耐圧を十分に向上させ
ることが従来の解決すべき技術課題とされていた。For this reason, a high voltage semiconductor device l provided with a guard ring layer 6
In the past, the technical problem to be solved was to increase the degree of integration and sufficiently improve the withstand voltage.
発明の目的
本発明は、集積度及び耐圧が高く、しかも製造が容易な
高耐圧半導体装置を提供するものである。OBJECTS OF THE INVENTION The present invention provides a high voltage semiconductor device that has a high degree of integration and high voltage resistance, and is easy to manufacture.
発明の概要
本発明は、基板内の多数キャリアと反発する陰イオン性
の絶縁層を基板の表面に形成することによって、高集積
度の下に空乏層の広が９を十分に大きくシ、耐圧の向上
を達成し九高圧耐□１ 半導体装置をその要旨とす
るものである。SUMMARY OF THE INVENTION The present invention makes it possible to sufficiently increase the spread of the depletion layer 9 and withstand voltage under high integration density by forming an anionic insulating layer on the surface of the substrate that repels majority carriers within the substrate. The gist of this is a semiconductor device with nine high voltage resistance □1.
以下、本発明の実施例について図面を参照して説明する
。Embodiments of the present invention will be described below with reference to the drawings.
発明の実施例 第５図は、本発明の一実施例の断面図である。Examples of the invention FIG. 5 is a cross-sectional view of one embodiment of the present invention.
図中２０は、Ｎ−型半導体基板である。この半導体基板
２００所定領域には、Ｐ＋型の不純物領域２１が形成さ
れている。また、半導体基板２０には、所定間隔を設け
て不純物領域２１を囲むようＫＰ型のガードリング層２
２が形成されている。半導体基板２０の表面には、不純
物領域２１と半導体基板２０の領域とで形成されたＰＮ
Ｗ！合表面及びガードリング層２２０表面を覆うように
陰イオン性の絶縁層２３が形成されている。In the figure, 20 is an N-type semiconductor substrate. In a predetermined region of this semiconductor substrate 200, a P+ type impurity region 21 is formed. Further, a KP type guard ring layer 2 is formed on the semiconductor substrate 20 so as to surround the impurity region 21 at a predetermined interval.
2 is formed. On the surface of the semiconductor substrate 20, there is a PN formed by the impurity region 21 and the region of the semiconductor substrate 20.
W! An anionic insulating layer 23 is formed to cover the joint surface and the guard ring layer 220 surface.
こむで、−陰イオン性の絶縁層２３の形成方法としては
、第６図に示す如く、不純物領域２１とガードリング層
２２を含む半導体基板２０の表面に酸化膜ＪＪａを形成
し、次いで、リンゲッターを施して酸化ｊ［ｊ ３ ａ
上にリンゲッタ一層ＪＪｂを形成した後、例えばＣ，Ｖ
、Ｄ、法（ｃｈ・−ｍｉｅａｌ Ｖａｐｏｒ Ｄ＠ｐｏ
ｓｌｔｉｏｎ法）によシリンダ、タ一層ｓｓｂ上Ｋ Ｐ
ＳＧ膜ｊｊｃを積層し、再びリンダツタ−処理及びＰｇ
Ｇ膜２３ｅの形成を施して陰イオン性の絶縁層２Ｊを得
るようｋしたものが望ましい。As shown in FIG. 6, the method for forming the -anionic insulating layer 23 is to form an oxide film JJa on the surface of the semiconductor substrate 20 including the impurity region 21 and the guard ring layer 22, and then phosphorus. Apply a getter to oxidize j [j 3 a
After forming a ring getter layer JJb on top, for example, C, V
, D, law (ch・-mieal Vapor D@po
sltion method) on the cylinder, one layer on the ssb K P
The SG film jjc is laminated, and then subjected to the Lindatsuta treatment and Pg
It is preferable to form the G film 23e to obtain the anionic insulating layer 2J.
また、リンゲッター処理及びＰ８Ｇ膜２３＠の形成回数
は、最終的に得られる素子の耐圧を決定するものであＦ
）、５０ｏｖ程度の耐圧の素子を得る場合には２回、５
００〜１ｏｏｏ ｖの耐圧の素子を得る場合は３〜４回
、１０００〜１５００ Ｖの耐圧の素子を得る場合には
３〜５回施すのが望ましい。Furthermore, the number of times the ring getter treatment and the P8G film 23@ are formed determines the breakdown voltage of the device finally obtained.
), twice to obtain an element with a withstand voltage of about 50 ov, and 5
It is desirable to apply the process 3 to 4 times to obtain an element with a breakdown voltage of 00 to 100 V, and 3 to 5 times to obtain an element with a breakdown voltage of 1000 to 1500 V.
また、絶縁層２３の厚さも最終的に形成する素子の耐圧
を左右する因子であシ、３００Ｖ程度の耐圧を得る場合
には０．８＃１１Ｅ１以上の厚さとし、５００ｖ程度の
耐圧を得る場合にｌｌ１１．２μｍ以上の厚さに設定す
るのが望ましい。In addition, the thickness of the insulating layer 23 is also a factor that affects the breakdown voltage of the element to be finally formed.When obtaining a breakdown voltage of about 300V, the thickness should be 0.8#11E1 or more, and when obtaining a breakdown voltage of about 500V, the thickness should be 0.8#11E1 or more. It is desirable to set the thickness to 11.2 μm or more.
ま九、ＰＳＧ膜２３＠中の９ノ濃度は、耐圧及びＰＮ接
合のリーク電流の発生に影響を及はすものであシ、耐圧
を向上させてリーク電流の発生を抑えるように１×１０
２０〜３ｘ１０りの濃度に設定するのが望ましい。Nine, the concentration of 9 in the PSG film 23 has an effect on the breakdown voltage and the generation of leakage current in the PN junction.
It is desirable to set the density to 20 to 3×10.
こＯように構成された高耐圧半導体装置り工によれば、
絶縁層２Ｊが陰イオン性になるように形成されて偽るの
で、ガードリング層２２の数を少なくした状態で、絶縁
層２３と半導体基板２０中の多数キャリアの電気的な反
発によって不純物領域２１とガードリング層２２の直下
に形成される空乏層２５の広が〕を大きくし、耐圧を十
分に向上させることができる。しかも、ガードリング層
２２の数は、従来の装置のように多くする必要がないの
で素子の占有面積を小さくして集積度を向上させること
ができる。また、メす構造に代ってガードリング構造を
採用しているので、製造が極めて容易である。According to a high-voltage semiconductor device engineer configured in this way,
Since the insulating layer 2J is formed to be anionic, the electrical repulsion of the majority carriers in the insulating layer 23 and the semiconductor substrate 20 causes the impurity region 21 to The spread of the depletion layer 25 formed directly under the guard ring layer 22 can be increased, and the withstand voltage can be sufficiently improved. Moreover, since the number of guard ring layers 22 does not need to be increased as in the conventional device, the area occupied by the device can be reduced and the degree of integration can be improved. Furthermore, since a guard ring structure is adopted instead of a female structure, manufacturing is extremely easy.
発明の詳細
な説明した如く、本発明に係る高耐圧半導体装置によれ
ば、集積度及び耐圧の向上を図って、しかもその製造が
容易であふ等顕著な効果を有するものである。As described in detail, the high breakdown voltage semiconductor device according to the present invention improves the degree of integration and breakdown voltage, is easy to manufacture, and has many remarkable effects.
第１図（４）及び同図（Ｂ）は、従来のメサ構造を採用
した高耐圧半導体装置の断面図、第２図は、ガードリン
グ層を設けた従来の高耐圧半導体装置の断面図、第３図
は、同装置の空乏層の広がりを示す説明図、第４図は同
装置の表面に形成された絶縁層中の不純物と空乏層の広
がシの関係を示す説明図、第５図は、本発明の一実施例
の断面図、第６図は、同実施例の半導体装置の製造方法
を示す説明図である。
２０・・・半導体基板、２１・・・不純物領域、２２・
・・ガードリング層、２３・・・絶縁層、２３ａ・・・
酸化膜、ＪＪｂ・・・リング、タ一層、２３ｃ・・・Ｐ
ＳＧ膜、ノーＬ・・・高耐圧半導体装置、２５・・・空
乏層。FIGS. 1(4) and 1(B) are cross-sectional views of a conventional high-voltage semiconductor device employing a mesa structure, and FIG. 2 is a cross-sectional view of a conventional high-voltage semiconductor device provided with a guard ring layer. FIG. 3 is an explanatory diagram showing the spread of the depletion layer of the same device, FIG. 4 is an explanatory diagram showing the relationship between impurities in the insulating layer formed on the surface of the device and the spread of the depletion layer, and FIG. The figure is a sectional view of one embodiment of the present invention, and FIG. 6 is an explanatory diagram showing a method of manufacturing a semiconductor device of the same embodiment. 20... Semiconductor substrate, 21... Impurity region, 22.
...Guard ring layer, 23...Insulating layer, 23a...
Oxide film, JJb...ring, single layer, 23c...P
SG film, no L...high voltage semiconductor device, 25...depletion layer.
Claims (1)
と、該不純物領域と所定間隔を設けて前記基板に形成さ
れたＰ型ガードリング層と、前記不純物領域と前記基板
とで形成されたＰＮ接合表面及び前記ガードリング層を
含む前記基板上に形成された陰イオン性の絶縁層とを具
備することを特徴とする高耐圧半導体装置。A P-type impurity region formed in a predetermined region of an N-type semiconductor substrate, a P-type guard ring layer formed on the substrate with a predetermined distance from the impurity region, and the impurity region and the substrate. A high voltage semiconductor device comprising: a PN junction surface; and an anionic insulating layer formed on the substrate including the guard ring layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18953381A JPS5891641A (en) | 1981-11-26 | 1981-11-26 | Semiconductor device of high withstand voltage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18953381A JPS5891641A (en) | 1981-11-26 | 1981-11-26 | Semiconductor device of high withstand voltage |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5891641A true JPS5891641A (en) | 1983-05-31 |
Family
ID=16242887
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18953381A Pending JPS5891641A (en) | 1981-11-26 | 1981-11-26 | Semiconductor device of high withstand voltage |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5891641A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4799100A (en) * | 1987-02-17 | 1989-01-17 | Siliconix Incorporated | Method and apparatus for increasing breakdown of a planar junction |
| CN102217070A (en) * | 2009-09-03 | 2011-10-12 | 松下电器产业株式会社 | Semiconductor device and method for producing same |
-
1981
- 1981-11-26 JP JP18953381A patent/JPS5891641A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4799100A (en) * | 1987-02-17 | 1989-01-17 | Siliconix Incorporated | Method and apparatus for increasing breakdown of a planar junction |
| CN102217070A (en) * | 2009-09-03 | 2011-10-12 | 松下电器产业株式会社 | Semiconductor device and method for producing same |
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