JPS60153157A - Bi-polar ic - Google Patents
Bi-polar icInfo
- Publication number
- JPS60153157A JPS60153157A JP908584A JP908584A JPS60153157A JP S60153157 A JPS60153157 A JP S60153157A JP 908584 A JP908584 A JP 908584A JP 908584 A JP908584 A JP 908584A JP S60153157 A JPS60153157 A JP S60153157A
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- surge
- diode
- shadow
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000002955 isolation Methods 0.000 claims abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 238000009413 insulation Methods 0.000 claims description 5
- 230000010354 integration Effects 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 6
- 230000015556 catabolic process Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、高いサージ耐圧を有するバイポーラ集積回路
に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to bipolar integrated circuits with high surge withstand voltage.
従来例の構成とその問題点
バイポーラ集積回路のサージ耐圧を高めるため、サージ
吸収用のダイオードを内蔵させた構造が広く採用されて
いる。Conventional Structures and Their Problems In order to increase the surge withstand voltage of bipolar integrated circuits, structures incorporating surge absorption diodes have been widely adopted.
第１図および第２図は、負のサージ電圧および正のサー
ジ電圧を吸収するためにバイポーラ集積回路の中に作り
込まれたダイオードの構造を示す断面図である。負のサ
ージ電圧を吸収するためのダイオードは、第１図で示す
ように、Ｐ形シリコン基板１をアノード、Ｎ＋形埋込領
域２、Ｎ形エピタキシャル島領域ａおよびＮ＋形コンタ
クト用拡散領域４をカソードとする構造とされている。1 and 2 are cross-sectional views showing the structure of a diode built into a bipolar integrated circuit to absorb negative and positive surge voltages. As shown in FIG. 1, a diode for absorbing a negative surge voltage has a P type silicon substrate 1 as an anode, an N+ type buried region 2, an N type epitaxial island region a, and an N+ type contact diffusion region 4. It has a structure that serves as a cathode.
なお、図中５はカソード電極、６はＰ＋形絶縁分離領域
、７は二酸化シリコン膜などの絶縁膜である。In the figure, 5 is a cathode electrode, 6 is a P+ type insulation isolation region, and 7 is an insulating film such as a silicon dioxide film.
一方、正のサージ電圧を吸収するだめのダイオードは、
第２図で示すように、Ｎ形エピタキシャル島領域３１を
カソードとし、この中にアノードとなるＰ影領域８を作
り込み、さらに、Ｎ＋形コンタクト用拡散領域９にカソ
ード電極１０を設け、この電極をバイポーラ集積回路内
で最も高い電源電圧（■ｃｃ）ラインへ接続するととも
に、アノードとなるＰ影領域８にアノード電極１１を設
けた構造となっている。すなわち、これらのダイオード
の作り込みにより、負のサージ電圧をシリコン基板１を
通して接地点へ、一方、正のサージ電圧を電源電圧ライ
ンへ逃がす効果が奏される。On the other hand, the diode that absorbs positive surge voltage is
As shown in FIG. 2, the N type epitaxial island region 31 is used as a cathode, a P shadow region 8 which becomes an anode is formed in this, and a cathode electrode 10 is provided in the N+ type contact diffusion region 9, and this electrode is connected to the highest power supply voltage (cc) line in the bipolar integrated circuit, and an anode electrode 11 is provided in the P shadow region 8 which serves as an anode. That is, by incorporating these diodes, the negative surge voltage is released through the silicon substrate 1 to the ground point, while the positive surge voltage is released to the power supply voltage line.
ところで、このようなサージ対策が施されたバイポーラ
集積回路では、各端子の電位が電源電圧（■ｃｏ）を越
えない限りは上記の効果が発揮されるが、動作時に、端
子のいずれかの電位が電源電圧（■ｃｃ）を越える状態
が成立すると、ダイオードにより電源電圧ラインが短絡
されることになる。By the way, in a bipolar integrated circuit with such surge countermeasures, the above effect is exhibited as long as the potential of each terminal does not exceed the power supply voltage (■co), but during operation, if the potential of any of the terminals If a condition exists in which the voltage exceeds the power supply voltage (cc), the power supply voltage line will be short-circuited by the diode.
このため、このような回路状態の成立する可能性がある
バイポーラ集積回路には、上記のダイオード構造による
サージ対策を施すことができなかった０
発明の目的
本発明は、通常の動作時に、端子電圧が電源電圧を越え
る状態が成立しても、サージ耐圧を高める効果が確実に
奏されるバイポーラ集積回路の提供を目的とするもので
ある。For this reason, surge countermeasures using the diode structure described above cannot be applied to bipolar integrated circuits in which such a circuit state may occur. It is an object of the present invention to provide a bipolar integrated circuit that can reliably achieve the effect of increasing the surge withstand voltage even if the voltage exceeds the power supply voltage.
シャル島領域内に、Ｐ影領域の作り込みでダイオード接
合が形成され、前記Ｎ形エピタキシャル島領域を外部端
子に直接接続される回路部分に接続し、前記Ｐ影領域を
接地点に接続した構造を具備したものである。この構造
によれば、Ｐ影領域の作り込みで形成されたダイオード
接合、Ｎ形エピタキシャル島領域とＰ形半導体基板間の
ＰＮ接合ならびにこれらの接合容量が並列に接続された
等価回路が得られ、接合容量によるサージ電荷の吸収と
ＰＮ接合の降伏特性によるサージ電荷の側路がなされる
ことになる。A structure in which a diode junction is formed by creating a P shadow region in the shell island region, the N type epitaxial island region is connected to a circuit part directly connected to an external terminal, and the P shadow region is connected to a ground point. It is equipped with the following. According to this structure, a diode junction formed by creating a P shadow region, a PN junction between an N type epitaxial island region and a P type semiconductor substrate, and an equivalent circuit in which these junction capacitances are connected in parallel can be obtained. Surge charges are absorbed by the junction capacitance and bypassed by the breakdown characteristics of the PN junction.
実施例の説明
第３図は、本発明のバイポーラ集積回路内に作り込まれ
たサージ対策回路部の構造の−・例を示す断面図であシ
、図示するように、Ｎ形エピタキシャル島領域３３の中
に、一部が１形絶縁分離領域６と重なる関係を成立させ
てＰ影領域１２が作り込まれ、壕だ、Ｎ形エピタキシャ
ル島領域３．３の他部分にはＮ＋形コンタクト用拡散領
域１３が作り込捷れ、さらに、この領域には電極１４が
設けられている。なお、Ｐ影領域１２は、バイポーラト
ランジスタのベース領域の形成工程で同時に作す込み、
ｌＮ＋形コンタクト用拡散領域１３は、エミッタ領域の
形成工程で同時に作り込めばよい、。DESCRIPTION OF EMBODIMENTS FIG. 3 is a cross-sectional view showing an example of the structure of a surge countermeasure circuit built into a bipolar integrated circuit according to the present invention. A P shadow region 12 is formed in the 1-type insulating isolation region 6 so that a part thereof overlaps with the 1-type insulation isolation region 6, and a trench is formed in the other part of the N-type epitaxial island region 3.3. A region 13 is folded and an electrode 14 is provided in this region. Note that the P shadow region 12 is formed at the same time as the formation process of the base region of the bipolar transistor.
The 1N+ type contact diffusion region 13 may be formed at the same time as the emitter region formation process.
この構造によれば、ダイオードのアノード領域となるＰ
影領域１２が、Ｐ＋形絶縁分離領域６を通してＰ形シリ
コン基板１に接続される。しだがって、この部分の等価
回路は、第４図で示すように、Ｐ形シリコン基板１と電
極１４との間に、Ｎ形エピタキシャル島領域３３とＰ形
領域捗の間のＰＮ接合で形成されるダイオードＤ２およ
びこれらのダイオードの接合容量Ｃ１，Ｃ２が並列に接
続されたものとなる。そして、電極１４を外部端子と直
接接続される回路部分へ接続するならば、サージ電荷が
コンデンサＣ１，Ｃ２からなる大きな接合容量を介して
Ｐ形シリコン基板１へ交流的に流れ、また、ダイオード
Ｄ１．Ｄ２の逆耐電圧を越えるサージ電圧が印加された
ときには、これらのダイオードの降伏特性に従って、こ
れらを通してサージ電荷がＰ形シリコン基板１へ流れる
。According to this structure, P becomes the anode region of the diode.
A shadow region 12 is connected to the P type silicon substrate 1 through the P+ type isolation region 6 . Therefore, as shown in FIG. 4, the equivalent circuit of this part is a PN junction between the P-type silicon substrate 1 and the electrode 14, and between the N-type epitaxial island region 33 and the P-type region. The formed diode D2 and the junction capacitances C1 and C2 of these diodes are connected in parallel. If the electrode 14 is connected to a circuit part that is directly connected to an external terminal, surge charges will flow to the P-type silicon substrate 1 in an alternating current manner through the large junction capacitance formed by the capacitors C1 and C2, and the diode D1 ．． When a surge voltage exceeding the reverse withstand voltage of D2 is applied, a surge charge flows through these diodes to the P-type silicon substrate 1 according to their breakdown characteristics.
第虫図は、Ｎ形エピタキシャル島領域３３とＰ影領域１
２との間のＰＮ接合の面積の変化とサージ耐圧との関係
を相対的に示した図であり、サージ耐圧が、ＰＮ接合面
積のほぼ１／２乗に比例して向上することが確認された
。The worm diagram shows the N-type epitaxial island region 33 and the P shadow region 1.
2 is a diagram showing a relative relationship between the change in the area of the PN junction between the two and the surge withstand voltage, and it is confirmed that the surge withstand voltage improves approximately in proportion to the 1/2 power of the PN junction area. Ta.
以上の説明では、Ｐ影領域１２をＰ＋形絶縁分離領域６
を介してＰ形シリコン基板１へ接続した構造を説明した
が、Ｐ影領域１２は、接地点へ接続されればよく、配線
層あるいは金属細線を用いる接続方法を採用してもよい
。In the above explanation, the P shadow region 12 is defined as the P+ type insulation isolation region 6.
Although the structure in which the P-type silicon substrate 1 is connected to the P-type silicon substrate 1 through the P-type silicon substrate 1 has been described, the P-shaded region 12 only needs to be connected to a ground point, and a connection method using a wiring layer or a thin metal wire may be adopted.
発明の効果
本発明のバイポーラ集積回路では、トランジスタのコレ
クタベース接合と等価な接合でダイオードが形成され、
したがって、その耐圧は、コレクタベース間耐圧（Ｂｖ
ＣＢＯ）と等しくなる。通常のバイポーラ集積回路では
、コレクタペース間耐圧（ＢｖｃＢｏ）は約６０Ｖ以上
はあり、コレクタ基板間耐圧（ＢｖＣ８Ｏ）よりも低い
ものの、電源電圧（ｖＣｃ）よりは十分に高く、端子電
圧が電源電圧を越える状態のもとでもサージ保護の効果
が奏される。原理的には、端子電圧がコレクタベース間
耐圧（ＢｖｃＢｏ）に達する状態となるまでサージ保護
効果をうろことが可能である。Effects of the Invention In the bipolar integrated circuit of the present invention, a diode is formed with a junction equivalent to the collector-base junction of a transistor,
Therefore, its breakdown voltage is the collector-base breakdown voltage (Bv
CBO). In a normal bipolar integrated circuit, the collector-to-board breakdown voltage (BvcBo) is approximately 60V or more, which is lower than the collector-to-board breakdown voltage (BvC8O), but is sufficiently higher than the power supply voltage (vCc), and the terminal voltage is higher than the power supply voltage. Surge protection is effective even under conditions exceeding In principle, it is possible to maintain the surge protection effect until the terminal voltage reaches the collector-base breakdown voltage (BvcBo).
第１図および第２図は、バイポーラ集積回路内に作り込
まれるサージ吸収用ダイオードの従来の構造例を示す図
、第３図は、本発明のパイボーラサージ劇圧との関係を
示す図である。
１ Ｐ形シリコン基板、２ ・Ｎ＋形埋込領域、３，３
２．３３・・−Ｎ形エピタキシャル島領域、４，９．１
３− ・Ｎ＋形コンタクト用拡散領域、５，１０．１４
− カソード電極、ｅ−Ｐ＋形絶縁分離領域、７−・−
絶縁膜、８．１２ ・ Ｐ影領域（アノード）、１１
・・・アノード電極、Ｄｌ、Ｄ２・・・ダイオード、Ｃ
４，Ｃ２−・ 接合容量。
代理人の氏名 弁理士 中 尾 敏 男 ＆Ｓか１名第
１図
第４図
第 ５ 図
糧肯面槓ＳFIGS. 1 and 2 are diagrams showing conventional structural examples of surge absorbing diodes built into bipolar integrated circuits, and FIG. 3 is a diagram showing the relationship with the extreme pressure of the pibora surge of the present invention. be. 1 P-type silicon substrate, 2 ・N+ type buried region, 3, 3
2.33...-N type epitaxial island region, 4,9.1
3- ・Diffusion region for N+ type contact, 5, 10.14
− Cathode electrode, e-P+ type insulation isolation region, 7−・−
Insulating film, 8.12 ・P shadow area (anode), 11
...Anode electrode, Dl, D2...Diode, C
4, C2-・ Junction capacitance. Name of agent: Patent attorney Toshio Nakao & S or one person Figure 1 Figure 4 Figure 5
Claims (3)
ャル島領域内に、Ｐ影領域の作シ込みでダイオード接合
が形成され、外部端子に直接接続される回路部分へ前記
Ｎ形エピタキシャル島領域を接続し、さらに、前記Ｐ影
領域を接地点へ接続してなるサージ保護構造を具備する
ことを特徴とするバイポーラ集積回路。(1) A diode junction is formed in the N-type epitaxial island region formed on the P-type silicon substrate by forming a P shadow region, and the N-type epitaxial island region is connected to the circuit portion directly connected to an external terminal. A bipolar integrated circuit, further comprising a surge protection structure in which the P shadow region is connected to a ground point.
を通したＰ形シリコン基板への接続でなされていること
を特徴とする特許請求の範囲第１項に記載のバイポーラ
集積回路。(2) The bipolar integration according to claim 1, wherein the connection of the P shadow region to the ground point is made by connection to the P type silicon substrate through the type 1 insulation isolation region. circuit.
徴とする特許請求の範囲第１項に記載のバイポーラ集積
回路。(3) The bipolar integrated circuit according to claim 1, wherein the P shadow area is an area equivalent to the base area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP908584A JPS60153157A (en) | 1984-01-20 | 1984-01-20 | Bi-polar ic |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP908584A JPS60153157A (en) | 1984-01-20 | 1984-01-20 | Bi-polar ic |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60153157A true JPS60153157A (en) | 1985-08-12 |
Family
ID=11710776
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP908584A Pending JPS60153157A (en) | 1984-01-20 | 1984-01-20 | Bi-polar ic |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60153157A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62291163A (en) * | 1986-06-11 | 1987-12-17 | Oki Electric Ind Co Ltd | Semiconductor integrated circuit device |
| JP2010171134A (en) * | 2009-01-21 | 2010-08-05 | Denso Corp | Protection device for integrated circuit |
-
1984
- 1984-01-20 JP JP908584A patent/JPS60153157A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62291163A (en) * | 1986-06-11 | 1987-12-17 | Oki Electric Ind Co Ltd | Semiconductor integrated circuit device |
| JP2010171134A (en) * | 2009-01-21 | 2010-08-05 | Denso Corp | Protection device for integrated circuit |
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